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X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
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DTSTART;TZID=America/Los_Angeles:20180503T150000
DTEND;TZID=America/Los_Angeles:20180503T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14517-1525359600-1525363200@www.cecs.uci.edu
SUMMARY:"Efficient Acceleration of Computation Using Associative In-memory Processing"
DESCRIPTION:Title: “Efficient Acceleration of Computation Using Associative In-memory Processing”\nSpeaker: Hasan Erdem Yantir\, University of California\, Irvine \nDate and Time: Monday\, May 14\, 2018 at 9:00AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi (Chair)\, Ahmed Eltawil\, Rainer Doemer \nAbstract: \nThe complexity of the computational problems is rising faster than the computational platforms’ capabilities. This forces researchers to find alternative paradigms and methods for efficient computing. One promising paradigm is accelerating compute-intensive kernels using in-memory computing accelerators since memory is the major bottleneck that limits the amount of parallelism and performance of a system and dominates energy consumption in computation. Leveraging the memory intensive nature of big data applications\, an in-memory-based computation system can be presented where logic can be replaced by memory structures\, virtually eliminating the need for memory load/store operations during computation. The massive parallelism enabled by such a paradigm results in highly scalable structures. \nThe present thesis is studied against this background. The objective is to conduct a broad perspective research on in-memory computing. For this purpose\, associative computing architectures (i.e.\, Associative Processors\, or AP) are built by both traditional (SRAM) and emerging (ReRAM) memory technologies together with their corresponding software frameworks. For ReRAM-based APs\, the reliability concerns coming with the emerging memories are resolved. Architectural innovations are developed to increase the energy efficiency. Furthermore\, approximate computing approach is introduced for APs to perform efficient/low-power approximate in-memory computing for the tasks which can tolerate some accuracy lost.  The works also propose a novel two-dimensional in-memory computing architecture to cope with the existing deficiencies of the traditional one-dimensional AP architectures.
URL:https://www.cecs.uci.edu/event/efficient-acceleration-of-computation-using-associative-in-memory-processing/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180507T150000
DTEND;TZID=America/Los_Angeles:20180507T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14518-1525705200-1525708800@www.cecs.uci.edu
SUMMARY:"Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks"
DESCRIPTION:Title: “Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks”\nSpeaker: Roger Piqueras Jover\, Security Researcher at Bloomberg LP \nDate and Time: Tuesday\, May 15 at 10:00 a.m. \nLocation: Donald Bren Hall 3011 \nAbstract:  \nThe Long Term Evolution (LTE) is the latest mobile communications standard being deployed globally to provide connectivity to billions of mobile devices\, from personal cell-phones to all types of critical systems\, such as self-driving cars\, medical appliances and industrial IoT sensors. As such\, the security of this communication standard is of paramount importance. However\, there is concerning inherent protocol security threats in LTE due to the large amount of unauthenticated and unprotected messages exchanged between a base station and a mobile device prior to the authentication security handshake. \nOpen source implementations of the LTE standards rapidly matured within the last couple of years. This\, in combination with sophisticated yet low cost software radio hardware\, fueled a new wave of security research that identified numerous protocol security issues in LTE that could allow an adversary to deny the service of mobile endpoints and track the location of users. This talk will summarize an ongoing effort on protocol-fuzzing LTE mobile networks using open-software tools. The protocol exploits against mobile endpoints that were discovered two years ago will be discussed as an introduction to the new systematic approach to protocol-fuzz LTE networks\, introducing as well a series of new potential exploits in the uplink\, against the network infrastructure and mobile devices outside of the radio range of the adversary. \nFinally\, these LTE protocol exploits are analyzed in the context of the recently (December 2017) published first release of the 3GPP 5G specifications (3GPP Rel. 15) for the 5G Radio Access Network (5G New Radio) and Core Network (5G System). Unfortunately\, not only most protocol-aware radio jamming issues and LTE protocol exploits are still a potential threat\, but there is a large number of new pre-authentication messages and new fields to already existing messages that could open the doors to further 5G-specific exploits. \nBiography: \nRoger Piqueras Jover is a Wireless Security Research Scientist and Security Architect at the CTO Security Architecture team of Bloomberg LP\, where he leads projects on mobile/wireless security and is actively involved in hardware security\, network security\, machine learning and anomaly/fraud detection. Previous to Bloomberg\, he spent 5 years at the AT&T Security Research Center (AT&T SRC)\, where he led the research area on wireless and LTE mobile network security and received numerous awards for his work. \nRoger holds 17 issued patents on mobile and wireless security\, has co-authored manuscripts in numerous top communications and security conferences and is the Technical Co-Chair for the ongoing IEEE 5G Summit series. \nRoger holds a Dipl. Ing. from Politechnical University of Catalunya (Barcelona\, Spain)\, a Master’s in Electrical and Computer Engineering from University of California Irvine and a Master’s/MPhil and EBD (Everything But Dissertation) in Electrical Engineering from Columbia University. \nFor a much more detailed biography\, details on his wireless security work on LTE\, 5G\, LoRaWAN and other technologies\, one can refer to http://rogerpiquerasjover.net/
URL:https://www.cecs.uci.edu/event/protocol-fuzzing-mobile-networks-with-open-source-tools-to-enhance-the-security-of-lte-and-5g-mobile-networks/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14524-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:“Self-aware Computing: Combining Learning and Control to Manage Complex\, Dynamic Systems”
DESCRIPTION:<stThese self-aware systems are distinguished by awareness of user goals and operating environment; they continuously monitor themselves and adapt their behavior and foundational models to ensure the goals are met despite the challenges of complexity (diverse hardware resources to be managed) and dynamics (unpredictable changes in input workload or resource availability). In this talk\, I will describe how to build self-aware systems through a combination of control theoretic and machine learning techniques. I will then show how this combination enables new capabilities\, like increasing system robustness\, reducing application energy\, and meeting latency requirements even with no prior knowledge of the application. Finally\, these LTE protocol exploits are analyzed in the context of the recently (December 2017) published first release of the 3GPP 5G specifications (3GPP Rel. 15) for the 5G Radio Access Network (5G New Radio) and Core Network (5G System). Unfortunately\, not only most protocol-aware radio jamming issues and LTE protocol exploits are still a potential threat\, but there is a large number of new pre-authentication messages and new fields to already existing messages that could open the doors to further 5G-specific exploits. \nBiography: \nHenry Hoffmann is an Associate Professor in the Department of Computer Science at the University of Chicago. He was granted early tenure in 2018. At Chicago he leads the Self-aware computing group (or SEEC project) and conducts research on adaptive techniques for power\, energy\, accuracy\, and performance management in computing systems. He received the DOE Early Career Award in 2015. He has spent the last 17 years working on multicore architectures and system software in both academia and industry. He completed a PhD in Electrical Engineering and Computer Science at MIT where his research on self-aware computing was named one of the ten “World Changing Ideas”  by Scientific American in December 2011. He received his SM degree in Electrical Engineering and Computer Science from MIT in 2003. As a Masters student he worked on MIT’s Raw processor\, one of the first multicores. Along with other members of the Raw team\, he spent several years at Tilera Corporation\, a startup which commercialized the Raw architecture and created one of the first manycores (Tilera was sold for $130M in 2014). His implementation of the BDTI Communications Benchmark (OFDM) on Tilera’s 64- core TILE64 processor still has the highest certified performance of any programmable processor. In 1999\, he received his BS in Mathematical Sciences with highest honors and highest distinction from UNC Chapel Hill. \n 
URL:https://www.cecs.uci.edu/event/self-aware-computing-combining-learning-and-control-to-manage-complex-dynamic-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14525-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:SIMD Assisted Fault Detection and Fault Attack Mitigation
DESCRIPTION:Name: Zhi Chen\nDate: May 15\, 2018 \nTime: 2:30pm \nLocation: Donald Bren Hall 3011 \nCommittee: Professor Alex Nicolau (Chair)\, Alex Veidenbaum\, Nikil Dutt \nAbstract: \nModern processors continue to aggressively scale down the feature size and reduce voltage levels to run faster and be more energy efficient. However\, this trend also poses significant reliability concern as it makes transistors more susceptible to soft errors. Soft errors are transient. Although they don’t impair the computing systems permanently\, these errors can corrupt the output of a program or even crash the entire system. Hardware or software redundant techniques could be used to detect errors during the execution of a program. However\, hardware redundancy\, e.g. DMR (dual-modular redundancy) and TMR (triple-modular redundancy)\, leads to significant area overhead and very high energy cost. Software redundancy\, e.g. instruction duplication\, has lower performance and energy penalty and  virtually no hardware cost by sacrificing a small degree of error coverage. Yet commodity processors generally don’t require “five-nines” reliability as they are not mission-critical. Instead\, performance and energy consumption have more priority. This dissertation proposes a novel approach to instruction duplication\, which exploits the redundancy within SIMD instructions. The key idea is to pack the original data and its duplicate in the different lanes of the same vector register instead of executing two scalar instructions separately as these registers are underutilized on most applications. The proposed solution is implemented in the LLVM compiler as a stand-alone pass. Evaluation on a host of benchmarks reveal that proposed SIMD-based error detection technique causes much less performance\, code size\, and energy overheads.\n\nThis dissertation further extends the proposed approach as a countermeasure to protect cryptographic algorithms. These algorithms are widely adopted in modern processors and embedded systems to protect information. A number of popular cryptographic algorithms in the Libgcrypt library are protected using the SIMD-based instruction duplication technique. A large amount of errors are injected to these algorithms. The results show that almost all injected faults can be detected with reasonable performance and code size cost.\n 
URL:https://www.cecs.uci.edu/event/simd-assisted-fault-detection-and-fault-attack-mitigation/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180517T150000
DTEND;TZID=America/Los_Angeles:20180517T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14526-1526569200-1526572800@www.cecs.uci.edu
SUMMARY:Reflective On-Chip Resource Management Policies for Energy-Efficient Heterogeneous Multiprocessors
DESCRIPTION:Name: Tiago Mück\nDate: May 16\, 2018 \nTime: 2:00pm \nLocation: Donald Bren Hall 2011 \nCommittee: Nikil Dutt (Chair)\, Alex Nicolau\, Tony Givargis \nAbstract: \nEffective exploitation of power-performance tradeoffs in heterogeneous many-core platforms (HMPs)\, requires intelligent on-chip resource management at different layers\, in particular at the operating system level. Operating systems need to continuously analyze the application behavior and find a proper answer for questions such as: What is the most power efficient core type to execute the application without violating its performance requirements? or Which option is more power-efficient for the current application: an out-of-order core at a lower frequency or an inorder core at a higher frequency?\nUnfortunately\, existing operating systems (e.g. Linux) do not offer mechanisms to properly address these questions and therefore are unable to fully exploit architectural heterogeneity for scalable energy-efficient execution of dynamic workloads.\nThis dissertation proposes a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software.\n\nThe general idea of reflection is to change your actions based on both external feedback and introspection (i.e.\, self-assessment).\n\n\nFrom a practical computer system perspective\, reflection means performing resource management actions considering both sensing information (e.g.\, readings from performance counters\, power sensors\, etc.) to assess the current system state\, as well as models to predict the behavior of the system before performing an action.\nIn this context\, this dissertation describes MARS\, a Middleware for Adaptive Reflective computer Systems. MARS consists of a framework and a set of models for creating reflective resource managers. MARS is implemented and evaluated on top a real Linux-based platform. Furthermore\, MARS also provides an offline simulation infrastructure for fast prototyping of policies and large-scale or long-term policy evaluation.\n\nExperimental evaluation shows that MARS’s models allow different policies for task mapping and dynamic voltage scaling to be seamlessly integrated\, resulting in up-to 1.8x energy efficiency improvements without performance degradation when compared to vanilla Linux.
URL:https://www.cecs.uci.edu/event/reflective-on-chip-resource-management-policies-for-energy-efficient-heterogeneous-multiprocessors/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180521T150000
DTEND;TZID=America/Los_Angeles:20180521T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14527-1526914800-1526918400@www.cecs.uci.edu
SUMMARY:"One does not need a Village to make a Billion Gate ASIC\, only a family if Synchoros VLSI Design Style is adopted"
DESCRIPTION:Name: Ahmed Hemani\nDate and Time: June 6\, 2018 at 4:00 p.m. \nLocation: Engineering Hall 2430 \nCommittee: Nikil Dutt (Host) \nAbstract: \nNorman Jouppi while introducing the record long list of authors of Google’s TPU paper at ISCA 2017 remarked – one needs a village to make a chip. This talk proposes a VLSI design method that holds promise of getting the same work done with just a family. This new VLSI design method is based on two principles\, one is to raise the abstraction of physical design to micro-architecture level from the present day boolean level standard cells and the second is to adopt a synchoros VLSI design style that enables composition by abutment to eliminate logic and physical synthesis for the end user. \nThe proposed method raises the abstraction of physical design to micro-architecture level by adopting coarse grain reconfigurable logic for computation\, storage and interconnect. All variations in function\, capacity\, architecture and degree of parallelism are realised by clustering and configuration of the coarse grain reconfigurable cells that we call as SiLago blocks – Silicon Lego Blocks. The micro-architecture level SiLago blocks replace boolean level standard cells as the atomic building blocks of the VLSI systems. These CGRA fabrics are domain specific – inner modem\, outer modem\, scratchpad memory\, dynamic programming\, NOCs\, infrastructural elements like RISC system controller\, PLL/CGU\, RGU\, DRAM control etc. Each CGRA fabric is holistically customized for its domain\, not just for computation but also for control\, interconnect\, address generation\, local storage etc. \nThe CGRAs provide an architecturally regular basis for a synchoros VLSI design style. Synchoricity is derived from the Greek word “choros” for space. The way synchronous systems divide time uniformly with clock ticks and enables temporal composition\, synchoros systems divide space uniformly with grids and enables spatial composition. All SiLago blocks are synchoros or ratiochoros and bring out all their interconnects to periphery on grid at right place and on right metal layer to enable composition by abutment of valid neighbours. \nThe net result of adopting the above two principles is that as soon as a design is refined down to micro-architecture level\, the dimension and position of every single wire segment and transistor is known with certainty in the 100 million gate design. Unlike standard cells\, where the position of standard cells and wires connecting them is left to physical synthesis\, in synchoros design style these aspects are parametrically hardened. Global wires like power grid\, clocks\, resets\, NOCs are not synthesised\, they emerge as a result of the abutment process. This enables automation of system models down to GDSII to create custom\, spatially distributed functional hardware\, i.e.\, ASICs with just a family. \nA proof of concept synthesis flow exists for transforming applications\, hierarchy of algorithms\, to GDSII and a path for system level to GDSII is well defined and is being implemented. System-level implies interacting applications. \nBiography: \nAhmed Hemani is Professor in Electronic Systems Design at School of ICT\, KTH\, Kista\, Sweden. His current areas of research interests are massively parallel architectures and design methods and their applications to scientific computing and autonomous embedded systems inspired by brain. In past he has contributed to high-level synthesis – his doctoral thesis was the basis for the first high-level\nsynthesis product introduced by Cadence called visual architect. He has also pioneered the Networks-on-chip concept and has contributed to clocking and low power architectures and design methods. He has extensively worked in industry including National Semiconductors\, ABB\, Ericsson\, Philips Semiconductors\, Newlogic. He has also been part of three start-ups.
URL:https://www.cecs.uci.edu/event/one-does-not-need-a-village-to-make-a-billion-gate-asic-only-a-family-if-synchoros-vlsi-design-style-is-adopted/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180530T150000
DTEND;TZID=America/Los_Angeles:20180530T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14528-1527692400-1527696000@www.cecs.uci.edu
SUMMARY:"Are there any questions?"
DESCRIPTION:Name: Yale Patt\nDate and Time: Thursday\, June 7 at 2:00 p.m. – 3:00 p.m. \nLocation: Engineering Hall 2430 \nAbstract:  \nToo many seminars can be characterized as 50 minutes of lecture\, followed by 5 minutes of questions. …and the first question makes it clear that nothing the speaker said in the 50 minutes was at all interesting to the audience. So\, we will take the opposite approach: 5 minutes of lecture\, followed by 50 minutes of questions. 5 minutes of lecture just to set the tone. Where the questions will take us is anybody’s guess. It will probably have something to do with computer architecture\, historical or current\, but it may venture off into something political …or at least politically correct. \nBiography: \nYale Patt is a Professor of Electrical and Computer Engineering and the Ernest\nCockrell\, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He divides his\ntime between teaching the freshman and senior courses and his advanced graduate course in\nmicroarchitecture\, working with his PhD students\, and consulting in the microprocessor industry.\nHe earned obligatory degrees from reputable universities and has received more than his share of\nawards for his research and teaching. Patt has spent much of his career pursuring aggressive ILP\,\nout-of-order\, and speculative computer architectures\, such as HPSm. He has a Fellow of both the\nIEEE and ACM\, and a member of the National Academy of Engineering. He received his master’s\nand Ph.D. degrees in Electrical Engineering from Stanford University.
URL:https://www.cecs.uci.edu/event/are-there-any-questions/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
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