BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CECS
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20160313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20161106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171221T150000
DTEND;TZID=America/Los_Angeles:20171221T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14513-1513868400-1513872000@www.cecs.uci.edu
SUMMARY:“Hierarchial Non-Intrusive In-Situ  Requirements Monitoring for Embedded Systems”
DESCRIPTION:Title:“Hierarchial Non-Intrusive In-Situ Requirements Monitoring for Embedded Systems”\nSpeaker: PhD Candidate Minjun Seo\, University of Arizona\, Tuscon \nDate and Time: Thursday\, December 21\, 2017 at 2:00PM-3:00PM \nLocation:  Engineering Hall 2430 \nAbstract: \nAccounting for all operating conditions of a system at the design stage is typically infeasible for complex systems. In-situ runtime monitoring and verification can enable a system to introspectively ensure the system is operating correctly in the presence of dynamic environment\, to rapidly detect failures\, and to provide detailed execution traces to find the root cause thereof. Two key challenges faced in using in-situ runtime verification for embedded systems include 1) efficiently defining and automatically constructing a requirements model for embedded system software and 2) minimizing the runtime overhead of observing and verifying the runtime execution adheres to the requirements model. In this talk\, we present a methodology to construct a hierarchical runtime monitoring graph from system requirements specified us- ing multiple UML sequence diagrams\, which are already commonly used in software development. We further present the design of on-chip hardware that nonintrusively monitors the system at runtime to ensure the execution matches the requirements model. We evaluate the proposed methodology using a case study of a fail-safe autonomous vehicle subsystem and analyze the relationship between event coverage\, detection rate\, and hardware requirements. \nBiography: \nMinjun Seo is a Ph.D. Candidate in the Department of Electrical and Computer Engineering at the University of Arizona.  His current research focuses on efficient specification and implementation of in-situ requirements monitoring of embedded systems. His research interests also include design tools and optimization methods supporting efficient verification hardware\, FPGAs\, and HW/SW co-design. Mr. Seo received a B.S. in Computer Science and Engineering in 2006 and a M.S. in Computer Science in 2008 from Kyungnam University.
URL:https://www.cecs.uci.edu/event/hierarchial-non-intrusive-in-situ-requirements-monitoring-for-embedded-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171128T150000
DTEND;TZID=America/Los_Angeles:20171128T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14510-1511881200-1511884800@www.cecs.uci.edu
SUMMARY:"I/O Optimization for Mobile Flash Storage"
DESCRIPTION:Title: “I/O Optimization for Mobile Flash Storage”\nSpeaker: Prof. Chun Jason Xue\, City University of Hong Kong \nDate and Time: Tuesday\, December 5\, 2017 at 10:00AM-11:00AM \nLocation: DBH 3011 \nAbstract: \nNAND flash memory is the primary choice of data storage for mobile devices due to its high performance\, shock resistance and low power consumption. However\, compared to high-end solid-state drives\, mobile flash storage does not have the luxury of sophisticated hardware and firmware features because of the resource-constraint limits. Instead\, mobile flash storage often equipped with scarce built-in RAM\, slow embedded processors and low-cost flash memories\, all of which make it a challenge to apply traditional techniques for I/O performance improvements. This talk presents a couple of work that we have done recently to optimize I/O for Mobile Flash Storage. First\, this talk will introduce a novel I/O scheduling approach to improve demand-based page-level mapping cache performance. This technique generates mapping cache friendly I/O workloads by strengthening I/O locality at host I/O scheduler. Both temporal locality and spatial localities are taken into consideration for I/O scheduling. Second\, this talk will present a lightweight data compression technique at the flash controller to reduce write pressure on mobile flash storage. It first characterizes data compressibility based on real smartphones\, and the analysis shows that write traffics bound to mobile storage volumes are highly compressible. This technique is the first to investigate firmware-based data compression for mobile flash storage without adding extra data compression hardware. Experimental results demonstrate the proposed techniques outperform state-of-the-art schemes in terms of I/O latency and flash memory lifespan. \nBiography: \nDr. Chun Jason Xue is an Associate Professor at City University of Hong Kong Computer Science Department. His research interests include non-volatile memories\, embedded and real time systems. He is currently Associate Editor for ACM Transaction on Embedded Computing Systems\, Associate Editor for ACM Transaction on CPS\, Associated Editor for ACM Transaction on Storage. He was the TPC co-chair for LCTES 2015\, TPC co-char for ISVLSI 2016\, and has served as TPC members in premiere conferences such as DAC\, DATE\, RTSS\, RTAS\, CODES\, EMSOFT and ISLPED.
URL:https://www.cecs.uci.edu/event/i-o-optimization-for-mobile-flash-storage/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171120T150000
DTEND;TZID=America/Los_Angeles:20171120T160000
DTSTAMP:20231011T193349Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T193349Z
UID:14509-1511190000-1511193600@www.cecs.uci.edu
SUMMARY:Daniel D. Gajski has been conferred with the EDA-Award 2017 by edacentrum
DESCRIPTION:from: https://m.pressebox.de/boxid/881033\nIn recognition of his outstanding lifetime contributions and achievements in research\, development\, and application in the domain of Electronic Design Automation (EDA)\, edacentrum confers the first edacentrum EDA Contribution Award to Prof. Daniel D. Gajski on November 12th \,2017. \nDaniel D. Gajski is one of the most influential scientists in EDA with more than 40 years of intensive engagement in industry and academia. He developed principles for structured design of electronic systems\, implemented these principles by means of languages and tools\, and proved their wide industrial applicability. \nThe “Y-Chart” is likely one of the most cited illustrations in electronic system design. It structures the design space and locates design states\, processes\, tasks and tools. Wolfgang Nebel\, vice chairman of edacentrum handed out the award… more details
URL:https://www.cecs.uci.edu/event/daniel-d-gajski-has-been-conferred-with-the-eda-award-2017-by-edacentrum/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171114T150000
DTEND;TZID=America/Los_Angeles:20171114T160000
DTSTAMP:20231011T190709Z
CREATED:20231011T190702Z
LAST-MODIFIED:20231011T190709Z
UID:14501-1510671600-1510675200@www.cecs.uci.edu
SUMMARY:"Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems"
DESCRIPTION:Title: “Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems”\nSpeaker: Majid Namaki Shoushtari\, University of California\, Irvine \nDate and Time: Tuesday\, November 7\, 2017 at 11:00AM-12:00PM \nLocation: Donald Bren Hall 2011 \nAbstract:\nThe growing computing demands of emerging application domains such as Recognition/Mining/Synthesis (RMS)\, visual computing\, wearable devices and the Internet of Things (IoT) has driven the move towards manycore architectures to better manage tradeoffs among performance\, energy efficiency\, and reliability.\nThe memory hierarchy of manycore architectures has a major impact on their overall performance\, energy efficiency and reliability. We identify three major problems that make traditional memory hierarchies unattractive for manycore architectures and their data-intensive workloads: (1) they are power hungry and not a good fit for manycores in face of dark silicon\, (2) they are not adaptable to the variable workload’s requirements and memory behavior\, and (3) they are not scalable due to coherence overheads. \nThis thesis argues that many of these inefficiencies are the result of software-agnostic hardware-managed memory hierarchies. Application semantics and behavior captured in software can be exploited to more efficiently manage the memory hierarchy. This thesis exploits some of this information and proposes a number of techniques to mitigate the aforementioned inefficiencies in two broad contexts: (1) explicit management of hybrid cache-SPM memory hierarchy\, and (2) exploiting approximate computing to improve the energy efficiency of the memory hierarchy.\nWe first present the required hardware and software support for a software-assisted memory hierarchy that is composed of distributed memories which can be partitioned between caches and SPMs at runtime. We discuss our SPM APIs\, the protocol needed for data movements\, and our approach for explicit management of shared data.\nNext\, we augment caches and SPMs in this hierarchy with approximation support in order to improve the energy efficiency of the memory subsystem when running approximate programs.\nFinally\, we discuss a quality-configurable memory approximation strategy using formal control theory that adjusts the level of approximation at runtime depending on the desired quality for the program’s output. \n 
URL:https://www.cecs.uci.edu/event/software-assists-to-on-chip-memory-hierarchy-of-manycore-embedded-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171114T080000
DTEND;TZID=America/Los_Angeles:20171115T170000
DTSTAMP:20231026T194430Z
CREATED:20191126T204419Z
LAST-MODIFIED:20231026T194430Z
UID:15648-1510646400-1510765200@www.cecs.uci.edu
SUMMARY:Amir Rahmani Won Best Paper Award at MobiHealth 2017
DESCRIPTION:At the 7th EAI International Conference on Wireless Mobile Communication and Healthcare (MobiHealth) between November 14-15\, 2017\, in Vienna\, Austria\, Professor Amir Rahmani won the Best Paper Award with paper “Enhancing the Self-Aware Early Warning Score System through Fuzzified Data Reliability Assessment’. Congrats Prof. Rahmani!
URL:https://www.cecs.uci.edu/event/amir-rahmani-won-best-paper-award-at-mobihealth-2017/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171107T150000
DTEND;TZID=America/Los_Angeles:20171107T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190701Z
LAST-MODIFIED:20231011T190708Z
UID:14499-1510066800-1510070400@www.cecs.uci.edu
SUMMARY:"Network Resource Management in Cyber-Physical Systems"
DESCRIPTION:Title: “Network Resource Management in Cyber-Physical Systems”\nSpeaker: Dr. Xiabo Sharon Hu\, University of Notre Dame\, USA \nDate and Time: Friday\, November 17\, 2017 at 2:00PM-3:00PM \nLocation: ICS 432 \nAbstract: \nA cyber-physical system (CPS) is a system built from close integration of computational fabrics and physical components. Examples of such systems include avionic systems\, industrial control and civil infrastructure monitoring. In a CPS\, sensors and actuators are used to monitor and control the physical components while the computational fabrics determine the control values for the actuators based on the sensed data. All CPSs require timely delivery of sensed data from sensors to the computing fabrics and control signals from the computing fabrics to actuators. Managing the limited resources (e.g.\, computation power and communication bandwidth) to meet the timing requirements in a CPS is a challenging task. Even more challenging is that CPSs should degrade gracefully in the presence of various external disturbances such as failure in critical civil infrastructures and malicious attacks. \nIn this talk\, I first give a general introduction of WNCSs and the challenges that they present to network resource management. In particular\, I will discuss the complications due to external disturbances and the need for dynamic data-link layer scheduling. I then highlight our recent work that aims at tackling this challenge. Our work balances the scheduling effort between a gateway (or access points) and the rest of the nodes in a network. It paves the way towards decentralized network resource management in\norder to achieve scalability. Experimental implementation on a wireless test bed further validates the applicability of our proposed research. I will end the talk outlining our on-going effort in this exciting and growing area of research. \nXiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana\, USA. Her research interests include low-power system design\, real-time embedded systems\, circuit and architecture design with emerging technologies\, and hardware/software co-design. She has published more than 300 papers in these areas\, and received the Best Paper Award from the Design Automation Conference in 2001 and from the IEEE Symposium\non Nanoscale Architectures in 2009. She is the General Chair of Design Automation Conference in 2018. She is an Associate Editor for ACM Transactions on Cyber- Physical Systems\, and also served as Associate Editor for IEEE Transactions on VLSI\, etc. Sharon Hu is a Fellow of the IEEE. \nBiography: \nXiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana\, USA. She also holds a joint appointment in the department of Electrical Engineering at the same university. She received B.S. degree from Tianjin University\, China\, M.S. degree from Polytechnic University of New York\, and Ph.D. degree from Purdue University. She worked for General Motors Research Labs for almost 4 years before she started her academic career. Between 1993 and 1996\, she was an assitant professor in the department of Electrical and Computer Engineering at Western Michigan University\, Kalamazoo\, Michigan\, USA. \nHer research interests include analysis and design of low power\, real-time\, and embedded systems\, computing with emerging technologies\, and computational medicine. She has published more than 200 referred papers in these areas and received numerous research grants from both the U.S. government agencies and private industry. She received the CAREER award from U.S. National Science Foundation in 1997. She received the Best Paper Award from the ACM/IEEE Design Automation Conference in 2001 and from the IEEE Symposium on Nanoscale Architectures in 2009. Another paper of hers was named one of “The Most Influential Papers of 10 Years Design\, Automation\, and Test in Europe Conference (DATE)”. \nSharon is currently Associate Editor for ACM Transactions on Embedded Computing and Co-Chair of the Technical Program Committee of 2014 Design Automation Conference (DAC). She also served as Associate Editor for IEEE Transactions on VLSI and ACM Transactions on Design Automation of Electronic Systems. She has served as guest editors for several different journals/magazines such as the IEEE Computer Magazine and IEEE Transactions on Industrial Informatics. She was the Technical Program Co-Chair of the 9th International Symposium on Hardware/Software Codesign (CODES’2001) and the General Co-Chair of the same conference in 2002. She also served or is serving on the program committee of a number of conferences such as Design Automation Conference (DAC)\, International Conference on Computer-Aided Design (ICCAD)\, Design\, Automation and Test in Europe Conference )DATE)\, IEEE Real-Time Systems Symposium (RTSS)\, and IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)\, etc. \nAt the University of Notre Dame\, Sharon had been the Director of Graduate Studies for 10 years in the department of Computer Science and Engineering\, and was Senior Assistant Provost for ND International between 2012–2013. Currently\, she is the Associate Dean for Professional Development at the Graduate School. \n \n 
URL:https://www.cecs.uci.edu/event/network-resource-management-in-cyber-physical-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171107T150000
DTEND;TZID=America/Los_Angeles:20171107T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190701Z
LAST-MODIFIED:20231011T190708Z
UID:14500-1510066800-1510070400@www.cecs.uci.edu
SUMMARY:CECS Evening Reception in Association with ICCAD
DESCRIPTION:This event will take place on the UCI campus on Sunday\, November 12\, after 4pm.\nLocation: 6th floor of Donald Bren Hall\, building 314 on the UCI campus map (https://communications.uci.edu/documents/pdf/UCI_16_map_campus_core.pdf) \nTentative agenda: \n5pm  –  Welcome by Prof. Fadi Kurdahi (CECS Director) \n–  Opening Address\, Dr. Sanjiv Narayan (MC) \n–  Speakers:\nProf. Wolfgang Rosenstiel (University of Tuebingen\, Germany)\nProf. Frank Vahid (University of California\, Riverside)\nProf. Yale N. Patt (The University of Texas at Austin)\nProf. Rainer Doemer (University of California\, Irvine) \n–  Toast and cake cutting \n6pm  –  Socializing \nIn order to get to the event location\, we suggest to share a ride with Uber or Lyft. Please use this as the target address: \nDonald Bren Hall (DBH)\,\nUniversity of California\, Irvine\nEngineering Ct\,\nIrvine\, CA 92617 \nDriving Directions: \nIf you are driving to the event\, we suggest putting the following into your GPS navigation software (or Anteater Dr & E Peltason Dr intersection): \nAnteater Parking Structure\,\nIrvine\, California 92697 \nGeneral driving directions from ICCAD (Irvine Marriot): \n\nProceed south on Von Karman Ave.\nTurn left onto Campus Dr.\nTurn right onto E Peltason Dr.\nTurn right into the parking structure at Anteater Dr.\n\nFrom there\, DBH is just a short walk west of the structure. \n \nWe look forward to meeting you at the reception this Sunday afternoon! \nSunny greetings from Irvine\, \nCECS Event Organizing Committee
URL:https://www.cecs.uci.edu/event/cecs-evening-reception-in-association-with-iccad/
LOCATION:CA
CATEGORIES:Other Events
ATTACH;FMTTYPE=image/gif:https://cecs.uci.edu/files/2023/10/aps-to-dbh-x5trbf.tmp_.gif
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171106T150000
DTEND;TZID=America/Los_Angeles:20171106T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190700Z
LAST-MODIFIED:20231011T190708Z
UID:14497-1509980400-1509984000@www.cecs.uci.edu
SUMMARY:“ThirdEye: Visual Assist for Grocery Shopping”
DESCRIPTION:Title: “ThirdEye: Visual Assist for Grocery Shopping”\nSpeaker: Prof. Vijaykrishnan Narayanan\, Pennsylvania State University\, USA \nDate and Time: Wednesday\, November 15\, 2017 at 11:00AM-12:00PM \nLocation: 2430 Engineering Hall \nAbstract: \nShopping is widely considered as a relaxing leisure activity. However\, grocery shopping can be a frustrating experience for those with visual impairment. While getting to a grocery shop itself is not as much of a challenge for them\, locating and picking the items in the grocery shelf becomes a task as challenging as picking a needle from the haystack. Imagine picking up five items for your dinner recipe from a typical grocery store in the US that carries around 35\,000 unique items and can have more than 30 aisles spanning 45\,000 square meters. This talk will showcase synergistic advances in algorithms\, architectures and interface design for assisting those with visual impairment to do shopping. We will specifically focus on new non-boolean hardware approaches to significantly impact the energy-efficiency of the overall system. \nBiography: \nVijay Narayanan is a Distinguished Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is the director of the NSF Expeditions-in-Computing Program on Visual Cortex on Silicon and a thrust leader for the DARPA-MARCO LEAST Center. He has published more than 400 papers and won several awards in recognition of his research in power-aware systems\, embedded systems and computer architecture. He is a fellow of IEEE and ACM. \n 
URL:https://www.cecs.uci.edu/event/thirdeye-visual-assist-for-grocery-shopping/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T185012Z
CREATED:20231031T185012Z
LAST-MODIFIED:20231031T185012Z
UID:15732-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Mohsen Imani Received Best Paper Nomination at ACM DAC 2019
DESCRIPTION:Assistant Professor Mohsen Imani received Best Paper Nomination at ACM Design Automation Conference 2019 for his research paper titled\, “Locality-based Encoding for Energy-Efficient Brain-Inspired Hyperdimensional Computing.” Congrats Prof. Imani!
URL:https://www.cecs.uci.edu/event/mohsen-imani-received-best-paper-nomination-at-acm-dac-2019/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T182948Z
CREATED:20231031T182948Z
LAST-MODIFIED:20231031T182948Z
UID:15688-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Quoc-Viet Dang Won Dean’s Honoree for Excellence in Undergraduate Teaching
DESCRIPTION:Assistant Professor Quoc-Viet Dang won Dean’s Honoree for Excellence in Undergraduate Teaching under the Henry Samueli School of Engineering for his excellence in undergraduate teaching and engaging in pedagogical research in the field of e-learning and data analysis. Congrats!
URL:https://www.cecs.uci.edu/event/quoc-viet-dang-won-deans-honoree-for-excellence-in-undergraduate-teaching/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T182758Z
CREATED:20231031T182758Z
LAST-MODIFIED:20231031T182758Z
UID:15684-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Mohammad Al Faruque Awarded Distinguished Early-Career Faculty Award for Research
DESCRIPTION:Professor Mohammad Al Faruque was awarded Distinguished Early-Career Faculty Award for Research by UCI Academic Senate for outstanding contributions in his discipline through his research. Congrats!
URL:https://www.cecs.uci.edu/event/mohammad-al-faruque-awarded-distinguished-early-career-faculty-award-for-research/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T182254Z
CREATED:20231031T182239Z
LAST-MODIFIED:20231031T182254Z
UID:15679-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Mohammad Al Faruque Won Early Career Faculty Award for Research
DESCRIPTION:Professor Mohammad Al Faruque wont the Early Career Faculty Award for Research for Henry Samueli School of Engineering for his research contributions in the area of embedded systems. Congrats Prof. Al Faruque!
URL:https://www.cecs.uci.edu/event/mohammad-al-faruque-won-early-career-faculty-award-for-research/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T182037Z
CREATED:20171031T182029Z
LAST-MODIFIED:20231031T182037Z
UID:15675-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Qi Alfred Chen Receives Rackham Predoctoral Fellowship
DESCRIPTION:Assistant Professor Qi Alfred Chen receives Rackham Predoctoral Fellowship for his security research in smart systems and IoT. Congrats Prof. Chen!
URL:https://www.cecs.uci.edu/event/qi-alfred-chen-receives-rackham-predoctoral-fellowship/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T181652Z
CREATED:20171031T181644Z
LAST-MODIFIED:20231031T181652Z
UID:15671-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Daniel Gajski Won EDA Contribution Award
DESCRIPTION:Professor Daniel Gajski won the EDA Contribution Award for his outstanding lifetime contributions and achievements in research\, development and application of electronic design automation (EDA). Congrats Prof. Gajski!
URL:https://www.cecs.uci.edu/event/daniel-gajski-won-eda-contribution-award/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T181744Z
CREATED:20171031T181412Z
LAST-MODIFIED:20231031T181744Z
UID:15667-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Nikil Dutt Won CS @ Illinois 2017 Distinguished Educator Award
DESCRIPTION:Professor Nikil Dutt won CS @ Illinois 2017 Distinguished Educator Award. Prof. Dutt was recognize for his contributions to embedded systems and architecture research\, his mentoring of many successful Ph.D. advisees (who themselves have won many awards)\, as well as his teaching. Congrats Prof. Dutt!
URL:https://www.cecs.uci.edu/event/nikil-dutt-won-cs-illinois-2017-distinguished-educator-award/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T181722Z
CREATED:20171031T181124Z
LAST-MODIFIED:20231031T181722Z
UID:15663-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Tony Givargis Receives ICS Dean's Award
DESCRIPTION:Professor of Computer Science Tony Givargis won ICS Dean’s Award for Donald Bren School of ICS for his service as the former ICS Associate Dean for Student Affairs. Congrats Prof. Givargis!
URL:https://www.cecs.uci.edu/event/tony-givargis-receives-ics-deans-award/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171003T150000
DTEND;TZID=America/Los_Angeles:20171003T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14495-1507042800-1507046400@www.cecs.uci.edu
SUMMARY:"Application Mapping Methodologies for NoC-Based MPSOCs"
DESCRIPTION:Title: “Application Mapping Methodologies for NoC-Based MPSOCs”\nSpeaker: Jürgen Teich\, Friedrich-Alexander Universität Erlangen-Nürnberg (FAU) \nDate and Time: Tuesday\, November 14\, 2017 at 3:00PM-4:00PM \nLocation: DBH 4011 \nAbstract:  \nIn this talk\, we give an overview of novel techniques for systematically mapping applications to NoC-based multi-core architectures\n(MPSoCs). Complex applications requiring heterogenous processing resources are often described by task graphs\nwith data dependencies. Here\, the nodes represent actors or tasks which are typically activated periodically based on the\navailability of data. One prominent domain of applications fitting this model is stream processing. Here\, it is often important to guarantee\neither bandwidth or execution time requirements. But more recently\, also security\, energy and reliability aspects impose\nconstraints on the mapping of the tasks as well as their communication to cores\, respectively routes in the underlying NoC. \nConcerning mapping methodologies\, we first present a class of algorithms that perform “Self-Embedding”. The idea is here that\na source node issues a request to find appropriate resources to embed its sucessor tasks\, and so on.\nThe next class of techniques introduced is called “Hybrid Application Mapping (HAM)”. Here\, a careful analysis and\ncharacterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time)\nphase called “Design Space Exploration (DSE)”. At run-time\, the operating system then only needs to search within such\npre-analysed constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction.\nWe present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that\ndeadlines or throughput requirements will be automatically met for streaming applications.\nFinally\, we conclude with a discussion on resource constellations that may satisfy certain security requirements on an MPSoC. \nBiography: \nJürgen Teich is with Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)\, Germany\, where he is directing\nthe Chair for Hardware/Software Co-Design since 2003. He received the M.S. degree (Dipl.-Ing.; with honors)\nfrom the University of Kaiserslautern\, Germany in 1989 and the Ph.D. degree (Dr.-Ing.; summa cum laude)\nfrom the University of Saarland\, Saarbruecken\, Germany\, in 1993. In 1994\, he joined the DSP design group of Prof. E. A. Lee\nin the Department of Electrical Engineering and Computer Sciences (EECS)\, University of California at\nBerkeley (PostDoc). From 1995 to 1998\, he held a position at the Institute of Computer Engineering and\nCommunications Networks Laboratory (TIK)\, ETH Zurich\, Switzerland with his Habilitation\non the topic of `Synthesis and Optimization of Digital Hardware/Software Systems’ in 1996.\nFrom 1998 to 2002\, he was Full Professor in the Electrical Engineering and Information Technology\nDepartment\, University of Paderborn\, Germany. \nHis current research focuses on electronic design automation of embedded systems\nwith emphasis on hardware/software co-design\, reconfigurable computing and multi-core systems.\nProf. Teich has organized various ACM/IEEE conferences/symposia as Program Chair\nincluding CODES+ISSS´07\, FPL´08\, ASAP´10\, and DATE´2016.\nHe serves regularly as a TPC member of many program committees including DAC\, ASP-DAC\, ICCAD\, FPL\,\nASAP\, FPT\, FPGA\, RECONFIG\, ESTIMEDIA\, VLSI Design\, GECCO\, EMO\, RTSS\, etc.\nHe also serves in the editorial board of journals including ACM TODAES\, IEEE Design and Test and JES and has\nedited two text books on Hardware/Software Co-Design and recently a Handbook on this topic (Springer). \nProf. Teich is involved in many interdisciplinary projects on basic research as well as industrial projects.\nFrom 2003-2009\, he was an elected board member (Fachkollegiat) of the Deutsche Forschungsgemeinschaft (DFG)\nfor the area of Computer Architecture and Embedded Systems. He has been the initiator and\ncoordinator of the DFG priority programme 1148 on “Reconfigurable Computing”.\nSince 2010\, he has also been the principal coordinator of the Transregional\nResearch Center 89 “Invasive Computing” funded by the German Research Foundation (DFG).\nIn 2011\, he was elected member of the Academia Europaea. \n 
URL:https://www.cecs.uci.edu/event/application-mapping-methodologies-for-noc-based-mpsocs/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171003T150000
DTEND;TZID=America/Los_Angeles:20171003T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14496-1507042800-1507046400@www.cecs.uci.edu
SUMMARY:“Detecting Hardware Trojans Hidden in Unspecified Design Functionality”
DESCRIPTION:Title: “Detecting Hardware Trojans Hidden in Unspecified Design Functionality”\nSpeaker: Dr. Nicole Fern\, University of California\, Santa Barbara \nDate and Time: Thursday\, November 16th\, 2017 at 2:00PM-3:00PM \nLocation: Donald Bren Hall 3011 \nAbstract: \nTraditional verification methods and metrics attempt to answer the question: does my design correctly perform the intended functionality?  This talk will look at hardware verification from a security perspective\, which demands the verification effort answer an additional question: does my design perform malicious functionality in addition to the intended functionality?  The talk will motivate through examples why Hardware Trojans modifying only unspecified design functionality are both powerful and stealthy.  RTL don’t cares and idle cycles in on-chip bus protocols are two examples of unspecified functionality vulnerable to malicious modification that this talk will explore in depth.  This talk will also detail how to formulate the Trojan detection problem as a satisfiability problem in order to leverage existing formal verification tools to highlight Trojans hidden in unspecified functionality. \nBiography:  \nNicole Fern received her undergraduate degree in Electrical Engineering from The Cooper Union for the Advancement of Science and Art and her PhD degree in the ECE department at UC Santa Barbara under the advisement of Professor Tim Cheng.  She is now a post-doc at UC Santa Barbara.  Her thesis work focused on developing techniques to verify the absence of Hardware Trojans in unspecified design functionality.  Her current research interests include investigating security issues in emerging memory technologies and at the hardware/software boundary. \n  \n 
URL:https://www.cecs.uci.edu/event/detecting-hardware-trojans-hidden-in-unspecified-design-functionality/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170910T080000
DTEND;TZID=America/Los_Angeles:20170912T170000
DTSTAMP:20231031T180803Z
CREATED:20171031T180614Z
LAST-MODIFIED:20231031T180803Z
UID:15659-1505030400-1505235600@www.cecs.uci.edu
SUMMARY:QV Dang Won Best Paper Award for Computer-Based Education\, ICEBT 2017
DESCRIPTION:Assistant Professor Quoc-Viet Dang won the Best Paper Award for the 2017 International Conference on E-Education\, E-Business and E-Technology with paper “Utilizing Latent Semantic Analysis to Provide Automated Educational Support.” Congrats QV!
URL:https://www.cecs.uci.edu/event/qv-dang-won-best-paper-award-for-computer-based-education-icebt-2017/
LOCATION:CA
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170807T150000
DTEND;TZID=America/Los_Angeles:20170807T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14494-1502118000-1502121600@www.cecs.uci.edu
SUMMARY:Part I: “Development of Low-End Embedded Processors for Some SoC Applications”    Part II: “The Application-Specific Design for Signal Processing Applications”
DESCRIPTION:Title: Part I: “Development of Low-End Embedded Processors for Some SoC Applications”Part II: “The Application-Specific Design for Signal Processing Applications” \nSpeaker: Prof. Fitzgerald Sungkyung Park\, Pusan National University\, Busan\, South Korea\nProf. Chester Park\, Konkuk University\, Seoul\, Korea \nDate and Time: Monday\, August 7\, 2017\, 2:00 PM – 3:00 PM \nLocation: Donald Bren Hall 3011 \nAbstract: \nLow-end processor cores can be utilized in various SoC applications including IoT\, wireless communication\, and machine learning.  In this short talk\, we will introduce how we designed some low-end integer cores applied to some applications such as deeply embedded IoT and WLAN MAC Soc\, and also introduce the basic design of embedded cores for neural networks. \nPart II: The application-specific design for signal processing applications tends to necessitate multi-disciplinary knowledge on system\, algorithm\, architecture and circuit levels.  In this talk\, we will introduce our application-specific design approaches for various signal processing applications.  In addition\, we discuss several design challenges involved in system-on-a-chip (SoC) design for neural networks\, regarding how to customize the on-chip bus architecture. \nBiography: \nProf. Fitzgerald Sungkyung Park took his Ph.D. degree in electronics engineering from Seoul National University\, Korea\, in 2002. He worked for Samsung Electronics from 2002 to 2004\, joined Electronics and Telecommunications Research Institute (ETRI) from 2004 to 2006\, and worked for Ericsson\, Inc.\, USA\, from 2006 to 2009\, where he developed mixed-signal circuits for radio transceivers. In 2009\, he joined the faculty of Pusan National University\, where he has worked on low-end processors and SoC for IoT and other applications. \nProf. Chester Park received his Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST)\, Korea\, in 2006. After about two years with Samsung Electronics Inc.\, Giheung\, Korea\, he joined Ericsson Research\, USA\, where he developed various signal processing algorithms for wireless communications. Since 2013\, he has been with Konkuk University\, Seoul\, Korea\, working on hardware accelerator design for signal processing algorithms. \n 
URL:https://www.cecs.uci.edu/event/part-i-development-of-low-end-embedded-processors-for-some-soc-applications-part-ii-the-application-specific-design-for-signal-processing-applications/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170731T150000
DTEND;TZID=America/Los_Angeles:20170731T160000
DTSTAMP:20231011T190638Z
CREATED:20231011T190638Z
LAST-MODIFIED:20231011T190638Z
UID:14489-1501513200-1501516800@www.cecs.uci.edu
SUMMARY:Accelerators and Enablement for Application-Specific Multicore Platforms
DESCRIPTION:Title: “Accelerators and Enablement for Application-Specific Multicore Platforms”\n\nSpeaker: Dr. Andreas Herkersdorf\, Electrical & Computer Engineering\, Technische Universität München\n\nDate and Time: Monday\, July 31\, 2017 at 2:00PM-3:00PM \nLocation: DBH 3011 \nAbstract: Multicore technology plays a pivotal role in conquering key societal challenges. For example\, safe\, ecological mobility\, wide-spread rollout of eHealth\, smart industrial automation and the development of a secure\, high-bandwidth\, low-latency mobile communication infrastructure for Industry 4.0\, all these application domains are critically dependent on high-performance\, low power and dependable computing. However\, multicore technology also comes with a number of unique challenges for industry and academia. Today\, the efficient utilization of massively parallel computing resources largely depends on the experience of individual programmers. \nApplication-specific accelerators and generic enablement building blocks for Multicore System on Chip (MCSoC) platforms are research foci at the Chair for Integrated Systems at TU München. These building blocks support a more performant\, energy efficient\, easier to use and more resilient deployment of multicore processors by application programmers and system integrators. In my talk\, I will present current and past research projects on wire-speed traffic distribution among Software Defined Networking (SDN) nodes\, interconnect virtualization for Network on Chip and processing node resilience\, efficient multicore deployment in legacy automotive CAN networks and on-chip diagnosis for effective software debugging. \nBiography: Andreas Herkersdorf is a professor at the Department of Electrical and Computer Engineering and also adjunct to the Department of Informatics at Technische Universität München (TUM). He received the diploma degree from TUM in 1987 and the Dr. degree from ETH Zurich\, Switzerland\, in 1991\, both in electrical engineering. Between 1988 and 2003\, he has been a research staff member and manager at the IBM Zurich Research Laboratory in Rüschlikon\, Switzerland. \nSince 2003\, Dr. Herkersdorf is head of the Chair for Integrated Systems at TUM. He is a senior member of the IEEE\, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer\, Elsevier and deGruyter journals for design automation\, communications electronics and information technology. His research interests include application-specific multi-processor architectures\, IP network processing\, Network on Chip\, system level SoC modeling and design space exploration methods\, and self-aware fault-tolerant computing.
URL:https://www.cecs.uci.edu/event/accelerators-and-enablement-for-application-specific-multicore-platforms/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170614T150000
DTEND;TZID=America/Los_Angeles:20170614T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190700Z
LAST-MODIFIED:20231011T190708Z
UID:14498-1497452400-1497456000@www.cecs.uci.edu
SUMMARY:"Optimizing Private Local Memories in Heterogeneous Architectures"
DESCRIPTION:Title: “Optimizing Private Local Memories in Heterogeneous Architectures”\nSpeaker: Christian Pilato\, Università della Svizzera italiana (USI)\, Lugano\, Switzerland \nDate and Time: Wednesday\, June 14\, 2017 at 11:00AM-12:00PM \nLocation: ICS 432 \nAbstract: \nModern Systems-on-Chip (SoC) architectures and state-of-the-art computing platforms that integrate CPUs with FPGAs are heterogeneous systems featuring an increasing number of hardware accelerators. Private local memories play a key role in the design of these components both with respect to performance optimization and because they are responsible for most of their area and power dissipation. Each local memory unit is usually implemented with a multibank microarchitecture based on the combined requirements of each hardware block accessing the corresponding data. However\, the creation of these multibank memory microarchitectures is not well supported by current design flows\, and the designers must perform this tedious and error-prone process manually. \nIn this talk\, I will present a system-level methodology for the generation of multi-bank memories in heterogeneous architectures. The methodology is supported by Mnemosyne\, an open-source prototype CAD tool that can be easily integrated into commercial design flows. Mnemosyneincludes various technology-aware optimizations to reduce the memory cost (area and power) by efficiently reusing the physical banks for storing different data. With Mnemosyne\,we can reduce the memory cost of single accelerators by up to 45%. Moreover\, when reusing memory IPs across accelerators\, we achieve area savings that range between 17% and 55% compared to the case where the memory elements are designed separately. \nBiography: \nChristian Pilato is a Postdoctoral Researcher at the ALaRi institute of Università della Svizzera italiana (USI)\, Lugano\, Switzerland. He received the Laurea degree in computer engineering and the Ph.D. degree in information technology from Politecnico di Milano\, Italy\, in 2007 and 2011\, respectively. From 2013 to 2016\, he was a Postdoctoral Research Scientist with the Department of Computer Science\, Columbia University\, USA. He has been visiting researcher at NanGate\, Chalmers University of Technology\, and Delft University of Technology. 
His current research interests include high-level synthesis\, reconfigurable systems and system-on-chip architectures\, with emphasis on memory aspects. He has actively participated in several projects sponsored by the European Union and DARPA\, as well as a research center supported by SRC. Dr. Pilato served as the Program Chair of the Embedded and Ubiquitous Conference (EUC) in 2014. He is currently involved in the program committees of many conferences on embedded systems\, CAD\, and reconfigurable architectures\, such as FPL\, DATE\, and CASES. He is a Member of IEEE and ACM.

URL:https://www.cecs.uci.edu/event/optimizing-private-local-memories-in-heterogeneous-architectures/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170607T150000
DTEND;TZID=America/Los_Angeles:20170607T160000
DTSTAMP:20231011T190637Z
CREATED:20231011T190637Z
LAST-MODIFIED:20231011T190637Z
UID:14488-1496847600-1496851200@www.cecs.uci.edu
SUMMARY:Mobile and Emerging Computing Systems: challenges and research opportunities
DESCRIPTION:Title: “Mobile and Emerging Computing Systems: challenges and research opportunities”\nSpeaker: Dr. Raid Ayoub\, Intel Strategic CAD Lab\, Portland\, Oregon\, USA \nDate and Time: Friday\, June 23\, 2017 at 11:00AM-12:00PM \nLocation: DBH 3011 \nAbstract: \nThe computing systems have been evolving at a fast pace and they are increasingly ubiquitous. This trend is driven by advancements in mobile technologies and emerging of Internet-of-Things (IoT) as well as new applications. However\, the complexity and diversity of these systems continue to rise\, which require transformative design automation solutions to meet stringent design metrics\, e.g. time-to-market. This talk will address research problems in mobile computing at the system level with some emphasis on energy efficiency and power budgeting of the CPU-GPU subsystem as well as user-experience related problems (e.g. skin temperature estimation and control). In addition\, this talk will discuss emerging challenges and future research problems in the domain of IoT systems with a focus on End-to-End system design. \nBiography: \nRaid Ayoub received his Ph.D. degree in computer engineering from the department of computer science and engineering\, University of California at San Diego in 2011.Currently he is a research scientist at the Strategic CAD Labs of Intel Corporation. He has published more than 30 journal and conference papers. His research interests include run-time optimizations\, dynamic control\, system modeling\, human cyber-physical systems/IoT\, dynamic power and thermal management\, machine learning\, and design automation.
URL:https://www.cecs.uci.edu/event/mobile-and-emerging-computing-systems-challenges-and-research-opportunities/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170605T150000
DTEND;TZID=America/Los_Angeles:20170605T160000
DTSTAMP:20231011T190636Z
CREATED:20231011T190636Z
LAST-MODIFIED:20231011T190636Z
UID:14487-1496674800-1496678400@www.cecs.uci.edu
SUMMARY:Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics
DESCRIPTION:Title:  “Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics”\nSpeaker: Prof. Axel Jantsch\, TU Wien \nDate and Time:  Friday\,  June 16\, 2017 at 11 A.M. \nLocation: 2430 Engineering Hall \nHost: Prof. Nikil Dutt \nAbstract: In healthcare\, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs of deterioration exist as early as 24 hours prior having a serious impact on the health of a person. As hospitalization times have to be minimized\, in-home or remote early warning systems can fill the gap by allowing in-home care while having the potentially problematic conditions and their signs under surveillance and control. This walk presents a remote monitoring and diagnostic system that provides a holistic perspective of patients and their health conditions. It discusses how the concept of self-awareness can be used in various parts of the system such as information collection through wearable sensors\, confidence assessment of the sensory data\, the knowledge base of the patient’s health situation\, and automation of reasoning about the health situation. This approach to self-awareness provides \n(i) situation awareness to consider the impact of variations such as sleeping\, walking\, running\, and resting\, \n(ii) system personalization by reflecting parameters such as age\, body mass index\, and gender\, and \n(iii) the attention property of self-awareness to improve the energy efficiency and dependability of the system via adjusting the priorities of the sensory data collection.\nBiography: \n Axel Jantsch received the Dipl.Ing. and Dr. Tech. degrees from TU Wien\, Vienna\, Austria\, in 1988 and 1992\, respectively. He was with Siemens Austria\, Vienna\, Austria\, as a system validation engineer from 1995 to 1997. From 1997 to 2002 he was an associate professor and from 2002 to 2014 he was full professor of Electronic Systems Design at the Royal Institute of Technology (KTH)\, Stockholm\, Sweden. Since 2014 he has been professor of Systems on Chip at TU Wien. He has published about 300 papers in international conferences and journals and one book in the areas of Systems on chip\, networks on chip and embedded systems. He has served on a large number of technical program committees of international conferences\, such as FDL\, DATE\, CODES ISSS\, SOC\, NOCS\, and others. He has been the TPC Chair of SSDL/ FDL 2000\, the TPC Co-Chair of CODES ISSS 2004\, the General Chair of CODES ISSS 2005\, and the TPC Co-Chair of NOCS 2009. From 2002 to 2007\, he was a subject area editor for the Journal of System Architecture. He is on the editorial board for IEEE Design and Test and for the Leibniz Transactions on Embedded Systems. He is a member of the IEEE. His main research interest is on networks on chip and self-awareness in systems on chip and embedded systems.\n\n\nView Details Here
URL:https://www.cecs.uci.edu/event/self-awareness-in-remote-health-monitoring-systems-using-wearable-electronics/
LOCATION:CA
CATEGORIES:Seminars at CECS
ATTACH;FMTTYPE=image/png:https://cecs.uci.edu/files/2023/10/axel_jantsch_seminar-iBdaHY.tmp_.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170531T150000
DTEND;TZID=America/Los_Angeles:20170531T160000
DTSTAMP:20231011T190636Z
CREATED:20231011T190636Z
LAST-MODIFIED:20231011T190636Z
UID:14486-1496242800-1496246400@www.cecs.uci.edu
SUMMARY:Quoc-Viet Dang PhD Defense
DESCRIPTION:Name: Quoc-Viet Dang\nDate: May 30\, 2017 \nTime: 02:00 P.M \nLocation: Engineering Hall 3206 \nCommittee: Professor Daniel Gajski (Chair)\, Fadi Kurdahi\, Rainer Doemer \nAbstract: \nPublic education is on the brink of a potential crisis attempting to significantly increase student enrollment while maintaining quality of education. Online courses have been proposed and debated among members of the UC regents\, numerous college administrators\, faculty\, and students. On one hand\, online education can reduce overhead while enrolling more students. Directly translating the classroom lectures and materials to an online environment does not necessarily produce equivalent student performance and satisfaction from the course compared to an in-class environment. Since there is no universal standard for online education\, erratic and inconsistent results have been achieved in terms of student performance and costs to students as well as administration. A hybrid scalable teaching and learning methodology is required by both educators and students to achieve the greatest advantages of using today’s technology and apply it toward improving student performance and participation. \nThis dissertation presents a methodology and system to provide a more individualized and responsive learning environment for students in large hybrid and online university courses while keeping overall costs and time commitment down as well as improve overall student performance. The Universal Personal Advisor\, the implemented learning design tool of this research\, is developed based on multi-disciplinary metrics and studies from the fields of Psychology\, Education\, and Engineering. A primary limiting resource for both students and instructors is time. By automating some basic key interactions that may occur between students and instructors\, hours of each individual’s time can be saved\, maximizing the quality of the available in-person interactions to occur during a course while allowing for a more scalable sized classroom environment.
URL:https://www.cecs.uci.edu/event/quoc-viet-dang-phd-defense/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170526T150000
DTEND;TZID=America/Los_Angeles:20170526T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190642Z
UID:14485-1495810800-1495814400@www.cecs.uci.edu
SUMMARY:Robust Data Hiding in Multimedia for Authentication and Ownership Protection
DESCRIPTION:Name: Farhan A. Alenizi\nDate: May 26th\, 2017 \nTime: 10:00 AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi \nAbstract: \nEstablishing robust and blind data hiding techniques in multimedia is very important for authentication\, ownership protection and security. The multimedia being used may include images\, videos and 3D mesh objects. A hybrid pyramid Discrete-Wavelet-Transform (DWT) Singular-Value-Decomposition (SVD) data hiding scheme for video authentication and ownership protection is proposed. The data being hidden will be in the shape of a main  color logo image watermark and another secondary Black and White (B&W) logo image.   The color watermark will be decomposed to Bit-Slices.   A pyramid transform is performed on the Y-frames of a video stream resulting in error images;  then\, a Discrete Wavelet Transform (DWT) process is implemented using orthonormal filter banks on these  error images\, and the Bit-Slices watermarks are inserted in one or more of the resulting subbands in a way that is fully controlled by the owner; then\, the watermarked video is reconstructed. SVD will be performed on the color watermark Bit-Slices. A secondary B&W watermark will be inserted in the main color watermark using another SVD process.     The reconstruction was perfect without attacks\, while the average Bit-Error-Rates (BER’s) achieved under attacks are in the limits of  2% for the color watermark and 5% for the secondary watermark; meanwhile\,  the mean Peak Signal-to-Noise Ratio (PSNR) is 57 dB. Furthermore\, a selective denoising filter to eliminate the noise in video frames is proposed; and the performance with data hiding is evaluated. \n  \nMoreover\, a 3D mesh blind  optimized watermarking   technique is proposed in this research. The technique relies on  the displacement process of  the vertices locations depending on the modification of the  variances of the vertices’s norms. Statistical analysis were performed to establish the proper distributions that best fit each mesh\, and hence establishing the bins sizes.   Experimental results showed that the approach is robust in terms of both the perceptual  and the quantitative  qualities. \n  \nIn conclusion\,  the degree of robustness and security  of the  proposed techniques are shown. Also the schemes that can be adopted to further enhance the performance\,  and the future work that can be done in the field are introduced. \n 
URL:https://www.cecs.uci.edu/event/robust-data-hiding-in-multimedia-for-authentication-and-ownership-protection/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170515T150000
DTEND;TZID=America/Los_Angeles:20170515T160000
DTSTAMP:20231011T190638Z
CREATED:20231011T190638Z
LAST-MODIFIED:20231011T190638Z
UID:14490-1494860400-1494864000@www.cecs.uci.edu
SUMMARY:Millimeter-wave and Sub-THz Signal Generation and Detection in Silicon Technologies
DESCRIPTION:Name: Peyman Nazari\nDate: May 15\, 2017 \nTime: 10:00 AM \nCommittee: Prof. Payam Heydari (Chair). Prof. Michael Green\, Prof. Ahmed Eltawil \nAbstract:  \nMM-wave/sub-Terahertz (THz) signal generation\, radiation\, and detection have become increasingly attractive due to its fast-growing applications in spectroscopy\, radar\, biomedical and security imaging as well as high-speed wireless communication.\n\n\nSilicon technology\, in one hand\, offering high-density signal processing capabilities due to aggressive scaling of its feature size\, and on the other hand\, allowing integration of mm-wave/THz antenna elements owing to their shrunk footprint at these bands\, is well-suited for implementation of fully-integrated multi-antenna mm-wave/THz wireless System-on-Chips (SoC’s).\n\n\nPerformance of such system is dominantly governed by the quality and efficiency of signal generation\, transmission\, and detection. Passive and active components as means of realizing these functionalities must be optimized for operation at these frequency ranges. However\, excessive loss of on-chip passive components and limited gain and output power of transistors at such high frequencies demand novel passive and active structures. Furthermore\, high level of integration implies that the co-design of front-end components leads to a better end-to-end performance\, thus a holistic design methodology must be employed. Radiation characteristics of the wireless signal must also be engineered to improve its transmission quality. For example\, circularly polarized radiation is found to be a viable choice for many imaging and communication applications by exhibiting excellent robustness against de-polarization effects.\n\n\nIn this dissertation\, silicon realization of on-chip waveguides\, as low loss mediums for high-frequency wave propagation\, is explored and implementations of low-loss cavity-backed passives are discussed. Furthermore\, a silicon-integrated IMPATT diode\, together with its fabrication and modeling is introduced as a solution for obtaining active behavior beyond fmax of transistors. Next\, a high-power/efficiency mm-wave circularly-polarized cavity-backed radiator\, employing a multi-port multi-function passive network as a resonator\, power combiner\, and antenna\, is introduced. Necessary conditions for robust operation of such multi-port oscillators/radiators are also derived. Fabricated in a 0.13µm SiGe BiCMOS process\, the prototype chip achieves 14.2dBm EIRP\, -99.3dBc/Hz phase noise at 1MHz offset\, and 5.2% DC-to-EIRP conversion efficiency which is the highest reported value among silicon-based radiators not using silicon lens or substrate processing.\n\n\nFinally\, a 210GHz low noise amplifier (LNA) is presented to address the detection challenges. This LNA\, achieves 18dB of gain\, with less than 12dB noise-figure and 3dB bandwidth of more than 15GHz\, thereby showing best performance metrics among prior work. This is achieved by incorporating circuit and EM techniques enabling simultaneous optimization of stable gain-\, noise- and bandwidth-performance parameters at this frequency range.
URL:https://www.cecs.uci.edu/event/millimeter-wave-and-sub-thz-signal-generation-and-detection-in-silicon-technologies/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170417T150000
DTEND;TZID=America/Los_Angeles:20170417T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14484-1492441200-1492444800@www.cecs.uci.edu
SUMMARY:Heterogeneous Chip Architectures for Big Data Analytics
DESCRIPTION:Title: “Heterogeneous Chip Architectures for Big Data Analytics”\nSpeaker: Houman Homayoun\, George Mason University\, Virginia \nDate and Time: Friday\, April 28\, 2017 at 11:00AM \nLocation: 2430 Engineering Hall \n \nAbstract: \nThere is a fundamental shift underway now in various industry sectors to transport their big data to the clouds\, thus increasing their efficiency and improving cash flow. In addition to traditional web service sector\, this also includes sectors such as telecommunication (e.g.\,  software defined network  applications)\, and healthcare (e.g.\, GE Cloud Health and Cloud PACS ). Cloud servers to process big data are now aggregating multiple disparate workloads with heterogeneously structured and unstructured data (image\, text\, video\, graph) with varying performance goals (batch\, streaming\, real-time\, and near-real-time). Emerging analytics applications in these domains rely heavily on specific deep machine learning and mining algorithms\, and are running complex database software stack with significant interaction with I/O and OS and sharing many inherent characteristics that are fundamentally different from traditional CPU and parallel applications. Emerging big data applications require computing resources that can efficiently scale to manage massive amounts of diverse data. However\, the rapid growth in the data yields challenges to process them efficiently using current cloud server architectures such as high performance Xeon. Furthermore\, physical design constraints\, such as power and density\, have become the dominant limiting factor for scaling out servers. To respond to these challenges\, heterogeneous architectures which integrates big and little cores with FPGA accelerators has emerged as a promising solution. In this talk\, through methodical investigation of power and performance measurements\, and comprehensive system level and micro-architectural analysis\, I first show the characterization results of emerging big data applications on big Xeon and little Atom-based servers. The characterization results across a wide range of real-world big data applications and various software stacks demonstrate how the choice of big vs little core-based server for energy-efficiency is significantly influenced by the size of data\, performance constraints\, and presence of accelerator. Furthermore\, the microarchitecture-level analysis highlights where improvement is needed in big and little core servers. \nSecond\, I will show how in a heterogeneous architecture effective mapping of Hadoop and Spark MapReduce based applications to FPGA accelerator can significantly increase the energy-efficiency and performance. The real-system results show promising kernel speedup of more than 100X and significant energy-efficiency gains. \nBiography: \nHouman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University. He also holds a joint appointment with the Department of Computer Science as well as Information Science and Technology Department. He is the director of GMU’s Green Computing and Heterogeneous Architectures (GOAL) Laboratory. Prior to joining George Mason University\, Houman spent two years at the University of California\, San Diego\, as National Science Foundation Computing Innovation (CI) Fellow awarded by the Computing Research Association (CRA) and the Computing Community Consortium (CCC). \nHouman’s research is in big data computing\, heterogeneous computing\, hardware security and trust\, and spans the areas of computer design and embedded systems\, where he has published more than 70 technical papers in the most prestigious conferences and journals on the subject. He is currently leading a number of research projects\, including the design of next generation heterogeneous architectures for big data processing\, non-volatile STT logic to prevent design reverse engineering\, heterogeneous accelerator platforms for wearable biomedical computing\, and logical vanishable design to enhance hardware security which are all funded by National Science Foundation (NSF)\, General Motors Company (GM)\, National Institute of Standards and Technology (NIST)\, Defense Advanced Research Projects Agency (DARPA)\, and Air Force Research Laboratory(AFRL). He received the 2016 GLSVLSI conference best paper award. He is currently serving as an Associate Editor of IEEE Transactions on VLSI (TVLSI). \nHouman received his PhD degree from the Department of Computer Science at the University of California\, Irvine in 2010\, an MS degree in computer engineering in 2005 from University of Victoria\, Canada and his BS degree in electrical engineering in 2003 from Sharif University of Technology.
URL:https://www.cecs.uci.edu/event/heterogeneous-chip-architectures-for-big-data-analytics/
LOCATION:CA
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170411T150000
DTEND;TZID=America/Los_Angeles:20170411T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14483-1491922800-1491926400@www.cecs.uci.edu
SUMMARY:Distinguished Lecture at CECS
DESCRIPTION:Title:  “Processor Paradigms: Evolution or Disruption and the importance of the Transformation Hierarchy Moving Forward”\nSpeaker: Prof. Yale N. Patt\, University of Texas\, Austin TX \nDate and Time: Friday\, March 31\, 2017 at 3:30 p.m. \nLocation: Donald Bren Hall 4011 \nHosts: Professor Alex Nicolau \nView Details Here
URL:https://www.cecs.uci.edu/event/distinguished-lecture-at-cecs-3/
LOCATION:CA
CATEGORIES:Other Events
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170307T150000
DTEND;TZID=America/Los_Angeles:20170307T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14482-1488898800-1488902400@www.cecs.uci.edu
SUMMARY:Optimizing Many-Threads-to-Many-Cores Mapping in Parallel Electronic System Level Simulation
DESCRIPTION:Name: Guantao Liu\nDate: March 2\, 2017 \nTime: 4:00 PM \nLocation: Engineering Hall 3206 \nCommittee: Rainer Doemer (Chair)\, Kwei-Jay Lin\, Mohammad Al Faruque \nAbstract: \nIn hardware/software co-design\, Discrete Event Simulation (DES) has been in use for decades to verify and validate the functionality of Electronic System Level (ESL) models. Since the parallel computing platforms are readily available today\, many Parallel Discrete Event Simulation (PDES) approaches are proposed to improve the simulation performance. However\, as the thread parallelism increases in ESL designs and core count multiplies on multi-core and many-core platforms\, thread-to-core mapping becomes critical in PDES. \nIn this dissertation\, we propose a computation- and communication-aware approach to optimize thread mapping for parallel ESL simulation\, with the aims of load balancing and communication minimization. As we identify that the order of dispatching parallel threads has a significant influence on the total simulation time\, and Longest Job First (LJF) shows better performance than the Linux default thread dispatch policy\, we first propose a segment- aware LJF scheduler for PDES. Our segment-aware scheduler can accurately predict the run time of the thread segments ahead\, and thus make better dispatching decisions. Next\, we define the concept of core distance for multi-core and many-core architectures\, which quantifies core-to-core communication latency and characterizes processor hierarchies. For many-core architectures using directory-based cache coherence protocols\, we observe that core-to-core transfers are not always significantly faster than main memory accesses\, and the core-to-core communication latency depends not only on the physical placement on the chip\, but also on the location of the distributed cache tag directory. Thus\, using a memory ping-pong benchmark\, we quantify the core distance on a ring-network many-core platform and propose an algorithm to optimize thread-to-core mapping in order to minimize on-chip communication overhead. Altogether\, based on a static analysis of communication patterns and core distance and a dynamic profiling of computation load\, our proposed framework utilizes a heuristic graph partitioning algorithm and automatically generates an optimized thread mapping\, which minimizes inter-chip communication overhead. In our systematic evaluation\, our approach consistently shows a significant performance gain on top of the order-of-magnitude speedup of PDES. \nThe contributions of this dissertation include a segment-aware multi-core scheduler\, core distance profiling\, a communication-aware thread mapping framework\, together with an open-source software package for Out-of-Order PDES.
URL:https://www.cecs.uci.edu/event/optimizing-many-threads-to-many-cores-mapping-in-parallel-electronic-system-level-simulation/
LOCATION:CA
CATEGORIES:PhD Defenses
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