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DTSTART;TZID=America/Los_Angeles:20170417T150000
DTEND;TZID=America/Los_Angeles:20170417T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14484-1492441200-1492444800@www.cecs.uci.edu
SUMMARY:Heterogeneous Chip Architectures for Big Data Analytics
DESCRIPTION:Title: “Heterogeneous Chip Architectures for Big Data Analytics”\nSpeaker: Houman Homayoun\, George Mason University\, Virginia \nDate and Time: Friday\, April 28\, 2017 at 11:00AM \nLocation: 2430 Engineering Hall \n \nAbstract: \nThere is a fundamental shift underway now in various industry sectors to transport their big data to the clouds\, thus increasing their efficiency and improving cash flow. In addition to traditional web service sector\, this also includes sectors such as telecommunication (e.g.\,  software defined network  applications)\, and healthcare (e.g.\, GE Cloud Health and Cloud PACS ). Cloud servers to process big data are now aggregating multiple disparate workloads with heterogeneously structured and unstructured data (image\, text\, video\, graph) with varying performance goals (batch\, streaming\, real-time\, and near-real-time). Emerging analytics applications in these domains rely heavily on specific deep machine learning and mining algorithms\, and are running complex database software stack with significant interaction with I/O and OS and sharing many inherent characteristics that are fundamentally different from traditional CPU and parallel applications. Emerging big data applications require computing resources that can efficiently scale to manage massive amounts of diverse data. However\, the rapid growth in the data yields challenges to process them efficiently using current cloud server architectures such as high performance Xeon. Furthermore\, physical design constraints\, such as power and density\, have become the dominant limiting factor for scaling out servers. To respond to these challenges\, heterogeneous architectures which integrates big and little cores with FPGA accelerators has emerged as a promising solution. In this talk\, through methodical investigation of power and performance measurements\, and comprehensive system level and micro-architectural analysis\, I first show the characterization results of emerging big data applications on big Xeon and little Atom-based servers. The characterization results across a wide range of real-world big data applications and various software stacks demonstrate how the choice of big vs little core-based server for energy-efficiency is significantly influenced by the size of data\, performance constraints\, and presence of accelerator. Furthermore\, the microarchitecture-level analysis highlights where improvement is needed in big and little core servers. \nSecond\, I will show how in a heterogeneous architecture effective mapping of Hadoop and Spark MapReduce based applications to FPGA accelerator can significantly increase the energy-efficiency and performance. The real-system results show promising kernel speedup of more than 100X and significant energy-efficiency gains. \nBiography: \nHouman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University. He also holds a joint appointment with the Department of Computer Science as well as Information Science and Technology Department. He is the director of GMU’s Green Computing and Heterogeneous Architectures (GOAL) Laboratory. Prior to joining George Mason University\, Houman spent two years at the University of California\, San Diego\, as National Science Foundation Computing Innovation (CI) Fellow awarded by the Computing Research Association (CRA) and the Computing Community Consortium (CCC). \nHouman’s research is in big data computing\, heterogeneous computing\, hardware security and trust\, and spans the areas of computer design and embedded systems\, where he has published more than 70 technical papers in the most prestigious conferences and journals on the subject. He is currently leading a number of research projects\, including the design of next generation heterogeneous architectures for big data processing\, non-volatile STT logic to prevent design reverse engineering\, heterogeneous accelerator platforms for wearable biomedical computing\, and logical vanishable design to enhance hardware security which are all funded by National Science Foundation (NSF)\, General Motors Company (GM)\, National Institute of Standards and Technology (NIST)\, Defense Advanced Research Projects Agency (DARPA)\, and Air Force Research Laboratory(AFRL). He received the 2016 GLSVLSI conference best paper award. He is currently serving as an Associate Editor of IEEE Transactions on VLSI (TVLSI). \nHouman received his PhD degree from the Department of Computer Science at the University of California\, Irvine in 2010\, an MS degree in computer engineering in 2005 from University of Victoria\, Canada and his BS degree in electrical engineering in 2003 from Sharif University of Technology.
URL:https://www.cecs.uci.edu/event/heterogeneous-chip-architectures-for-big-data-analytics/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170411T150000
DTEND;TZID=America/Los_Angeles:20170411T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14483-1491922800-1491926400@www.cecs.uci.edu
SUMMARY:Distinguished Lecture at CECS
DESCRIPTION:Title:  “Processor Paradigms: Evolution or Disruption and the importance of the Transformation Hierarchy Moving Forward”\nSpeaker: Prof. Yale N. Patt\, University of Texas\, Austin TX \nDate and Time: Friday\, March 31\, 2017 at 3:30 p.m. \nLocation: Donald Bren Hall 4011 \nHosts: Professor Alex Nicolau \nView Details Here
URL:https://www.cecs.uci.edu/event/distinguished-lecture-at-cecs-3/
LOCATION:CA
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170307T150000
DTEND;TZID=America/Los_Angeles:20170307T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14482-1488898800-1488902400@www.cecs.uci.edu
SUMMARY:Optimizing Many-Threads-to-Many-Cores Mapping in Parallel Electronic System Level Simulation
DESCRIPTION:Name: Guantao Liu\nDate: March 2\, 2017 \nTime: 4:00 PM \nLocation: Engineering Hall 3206 \nCommittee: Rainer Doemer (Chair)\, Kwei-Jay Lin\, Mohammad Al Faruque \nAbstract: \nIn hardware/software co-design\, Discrete Event Simulation (DES) has been in use for decades to verify and validate the functionality of Electronic System Level (ESL) models. Since the parallel computing platforms are readily available today\, many Parallel Discrete Event Simulation (PDES) approaches are proposed to improve the simulation performance. However\, as the thread parallelism increases in ESL designs and core count multiplies on multi-core and many-core platforms\, thread-to-core mapping becomes critical in PDES. \nIn this dissertation\, we propose a computation- and communication-aware approach to optimize thread mapping for parallel ESL simulation\, with the aims of load balancing and communication minimization. As we identify that the order of dispatching parallel threads has a significant influence on the total simulation time\, and Longest Job First (LJF) shows better performance than the Linux default thread dispatch policy\, we first propose a segment- aware LJF scheduler for PDES. Our segment-aware scheduler can accurately predict the run time of the thread segments ahead\, and thus make better dispatching decisions. Next\, we define the concept of core distance for multi-core and many-core architectures\, which quantifies core-to-core communication latency and characterizes processor hierarchies. For many-core architectures using directory-based cache coherence protocols\, we observe that core-to-core transfers are not always significantly faster than main memory accesses\, and the core-to-core communication latency depends not only on the physical placement on the chip\, but also on the location of the distributed cache tag directory. Thus\, using a memory ping-pong benchmark\, we quantify the core distance on a ring-network many-core platform and propose an algorithm to optimize thread-to-core mapping in order to minimize on-chip communication overhead. Altogether\, based on a static analysis of communication patterns and core distance and a dynamic profiling of computation load\, our proposed framework utilizes a heuristic graph partitioning algorithm and automatically generates an optimized thread mapping\, which minimizes inter-chip communication overhead. In our systematic evaluation\, our approach consistently shows a significant performance gain on top of the order-of-magnitude speedup of PDES. \nThe contributions of this dissertation include a segment-aware multi-core scheduler\, core distance profiling\, a communication-aware thread mapping framework\, together with an open-source software package for Out-of-Order PDES.
URL:https://www.cecs.uci.edu/event/optimizing-many-threads-to-many-cores-mapping-in-parallel-electronic-system-level-simulation/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170221T150000
DTEND;TZID=America/Los_Angeles:20170221T160000
DTSTAMP:20231011T190631Z
CREATED:20231011T190631Z
LAST-MODIFIED:20231011T190631Z
UID:14481-1487689200-1487692800@www.cecs.uci.edu
SUMMARY:Low Power Reliable Design using Pulsed Latch Circuits
DESCRIPTION:Name: Wael Mahmoud Elsharkasy \nDate: February 15\, 2017 \nTime: 11:00 AM \nLocation: Engineering Hall 3206 \nCommittee: Prof. Fadi J. Kurdahi\, Prof. Ahmed Eltawil\, Rainer Doemer \nAbstract: \nSystem-on-Chip (SoC) faced lots of challenges over the past decade. With nowadays applications centered around Internet-of-Everything (IoE)\, these challenges are expected to be more critical. Among these challenges are the reduction of power consumption for better energy efficiency\, the overcoming of different sources of variations to ensure reliable operation and the reduction of design area to reduce the cost and increase the integration. As a result\, chip designers find themselves facing lots of problems\, trying to build reliable systems that integrate complex level of functionality\, on a minimum die size and with a limited power budgets. Among different circuit components in every chip\, memory components are of great concern. They consume the majority of the chip area and power\, in addition to affecting the entire chip performance and reliability. These include large memory arrays\, caches\, register files and different sequential elements in the logic paths. Sequential elements play an important and critical role in modern synchronous CMOS circuits. Indeed\, they can represent up to 50% of the standard cells used in a chip. In addition\, the power consumption of the clock tree\, including these elements can be more than half of the total chip power. In addition\, they come in the second place after memory to be affected by different sources of variation. Hence\, efficient implementation of these elements is of great importance for the design of energy efficient and reliable integrated circuits. Pulsed latches have been proposed as efficient replacement of flip-flops in the implementation of sequential element. They can achieve higher performance when compared to traditional flip-flop\, and can be designed to be smaller in area and more power efficient. However\, the operation of pulsed latch is more sensitive to process\, voltage and temperature (PVT) variations. In this thesis\, we are proposing a methodology to study the reliability of pulsed latches and we have used it to evaluate the effect of PVT variations on their behavior. In addition\, novel approaches to enhance the reliability of pulsed latches without significant degradation in performance\, area or power are presented. Also\, since sequential elements can be used to build small size register files\, pulsed latch implementation of register files are discussed and compared to other traditional implementations\, including SRAM and flip-flops. In addition\, since multiport register files are very beneficial for quite few applications\, novel implementations of multiport register files are also presented. The proposed implementation is proved to highly reduce the significant overhead in area\, power and latency associated with the traditional way of designing multiport register files.
URL:https://www.cecs.uci.edu/event/low-power-reliable-design-using-pulsed-latch-circuits/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170131T150000
DTEND;TZID=America/Los_Angeles:20170131T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14479-1485874800-1485878400@www.cecs.uci.edu
SUMMARY:Runtime Memory Management in Many-core Systems
DESCRIPTION:Name: Hossein Tajik\nDate: November 15\, 2016 \nTime: 3:00PM – 4:00PM \nLocation: DBH 3011 Conference Room \nCommittee: Nikil Dutt (Chair)\, Tony Givargis\, Alex Nicolau \nAbstract: \nWith the increasing number of cores on a chip\, we are moving towards an era where many-core platforms will soon be ubiquitous. Efficient use of tens to hundreds of cores on a chip and their memory resources comes with unique challenges. \nIn this dissertation\, we propose SPMPool: a scalable platform for sharing Software Programmable Memories (SPMs). The SPMPool approach exploits underutilized memory resources by dynamically sharing SPM resources between applications running on different cores and adapts to the overall memory requirements of multiple applications that are concurrently executing on the many-core platform. We propose both central and distributed management schemes for SPMPool and study the efficiency of auction-based mechanisms in solving the memory mapping problem. We also propose offline and online memory phase detection methods in order to increase the adaptivity of memory management to temporal changes in memory requirements of a single application. The runtime memory management schemes proposed in this dissertation enable better performance and power for many-core systems.
URL:https://www.cecs.uci.edu/event/runtime-memory-management-in-many-core-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170130T150000
DTEND;TZID=America/Los_Angeles:20170130T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14492-1485788400-1485792000@www.cecs.uci.edu
SUMMARY:On Optimizing the Performance of Interference-Limited Wireless Systems
DESCRIPTION:Name: Rana A. Abdelaal\nDate: January 30\, 2017 \nTime: 1:00 PM \nLocation: Engineering Hall 3106 \nCommittee: Professor Ahmed Eltawil \nAbstract: \nMulti Input Multi Output (MIMO) technology has seen prolific use to achieve higher data rates and an improved communication experience for cellular systems. However\, one of the challenging problems in MIMO systems is interference. Interference limits the system performance in terms of rate and reliability. In this thesis\, we analyze methods that provide high performance over interference-limited wireless networks such as Long Term Evolution (LTE) and WiFi. In this thesis\, we tackle different sources of interference. One of the interference sources is the neighboring interference\, we propose methods that include an optimized solution that models the interference as correlated noise\, and uses its statistical information to jointly optimize the base station precoding and user receiver design of LTE systems. We study the benefits of exploiting interference in terms of both probability of error and signal-to-noise ratio (SNR). In addition\, we compare the proposed method with the conventional beamforming and maximum ratio combining (MRC). One of the key challenges to enable high data rates in the downlink of LTE is the precoding and receiver design. We focus primarily on the UE and the base station (BS) processing\, particularly on estimating and using the interference resulting from neighboring stations. In this thesis\, we propose a receiver design that performs well in the presence of interference. Furthermore\, we present a precoding scheme that the BS can use to maximize the signal-to-interference plus noise-ratio (SINR). An interference free scenario is used as a benchmark to evaluate the proposed system performance. In this thesis\, we optimize the performance of LTE by tackling practical considerations that affects the system performance. We present a suboptimal practical way of estimating the interference and utilizing this information on the processing techniques used at both the UE and the eNodeB sides. We focus on managing both MU-MIMO interference and other cell interference. The proposed study improves system performance even under non-perfect channel knowledge\, enabling the throughput gains promised by MU-MIMO. \nOther types of interference exist in In-band full-duplex (IBFD) communication systems. IBFD is very promising in enhancing wireless LANs\, where full-duplex access points (APs) can support simultaneous uplink (UL) and downlink (DL) flows over the same frequency channel. One of the key challenges limiting IBFD benefits is interference. In this thesis\, we also propose a scheduling technique to manage interference in wireless LANs with full-duplex capability. We focus primarily on scheduling UL and DL stations (STAs) that can be efficiently served simultaneously. \nIt is very important to apply system knowledge to reduce power and/or improve performance. Thus\, we also aim at exploring energy and power management techniques for practical wireless communication systems. An important topic for practical communication systems is handling the interference due to the power amplifier nonlinearities. Managing this type of interference is of very high importance\, especially in Orthogonal Frequency-Division Multiple Access (OFDMA) based communication systems. Although\, OFDMA is the modulation of choice due to its robustness to time-dispersive radio channels\, low-complexity receivers\, and simple combining of \nsignals from multiple transmitters in broadcast networks. The transmitter design for OFDMA is more costly\, as the Peak-to-Average Power Ratio (PAPR) of an OFDMA signal is relatively high\, resulting in the need for highly linear RF power amplifiers (PA). This problem becomes more compounded when a large number of PAs is required\, as in Massive MIMO for example. In this thesis\, we discuss the impact of PAs on cellular systems. We show the constraints that PAs introduce\, and we take these constraints into consideration while searching for the optimum set of transmitter and receiver filters. Moreover\, we highlight how Massive MIMO cellular networks can relax PAs constraints resulting in low cost PAs\, while maintaining high performance. The performance is evaluated by showing the probability of error curves and signal-to-noise-ratio curves for different transmit powers and different number of transmit antennas. Another promising topic for efficient practical communication systems is Associative processors (APs). AP is a good candidate for in-memory computation\, however it has been deemed too costly and energy hungry in the past. The advent of ultra-dense resistive memories is changing this paradigm\, allowing for efficient in-memory associative processors. However\, with high levels of integration\, issues related to power density become the bottleneck. In this thesis\, we show the potential use of the approximate computing in wireless communication systems\, specifically\, we present Fast Fourier Transform (FFT) implemented by associative processor. Results confirm that approximate computing for in-memory associative processors is a viable approach to reduce power consumption while maintaining good performance. A promising approach to save energy is through reducing the bit width\, however reducing the bit width introduces errors that may affect the performance. In this thesis\, our goal is to adjust the bit width based on the channel SNR\, aiming at achieving good performance at reduced energy consumption. The mathematical approach that analytically describes the system performance under the reduced bit width noise is presented. Based on this model\, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves performance goals at reduced energy consumption. Simulation results show that the proposed algorithms can achieve up to 45% energy savings as compared to wireless communication systems with conventional FFT. \n 
URL:https://www.cecs.uci.edu/event/on-optimizing-the-performance-of-interference-limited-wireless-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161206T150000
DTEND;TZID=America/Los_Angeles:20161206T160000
DTSTAMP:20231011T190622Z
CREATED:20231011T190622Z
LAST-MODIFIED:20231011T190622Z
UID:14476-1481036400-1481040000@www.cecs.uci.edu
SUMMARY:Scalable Runtime support for Edge-To-Cloud integration of Distributed Sensing Systems
DESCRIPTION:Name: Brett Chien\nDate: November 29\, 2016 \nTime: 10:00AM \nLocation: EH 2210 \nCommittee: Pai H. Chou (Chair) \nAbstract:  \nWhile Internet-Of-Things (IoT) has drawn more attention to researchers and the public\, to build a complete system from the edge sensing units to the cloud services requires massive amount of efforts. Researchers with strong interests in collected information are often lost in various technologies\, including distributed sensing embedded systems\, bridge devices between Internet and local network\, and data backend services. \nThis work takes a cross-system\, script-based\, and semantic-enhanced approach to address the problem of lacking suitable runtime supports. We proposed a threaded code runtime support for edge sensing systems\, a script based wrapper on Physical-to-Cyber bridges\, and scalable middleware into the backend services. \nWith proposed runtime supports\, we are able to apply distributed sensing systems into real world applications quickly and explorer insights from collected information. As a result\, a building structure monitoring system is installed and allow civil researchers to develop algorithms to prevent disaster events. Body area sensing systems such as ECG monitoring\, CO2 detection\, and body movement are developed. This enables baby screening and detect potential heart problems. The results have shown that with proposed runtime supports applications can be realized quickly and scalable.
URL:https://www.cecs.uci.edu/event/scalable-runtime-support-for-edge-to-cloud-integration-of-distributed-sensing-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161114T150000
DTEND;TZID=America/Los_Angeles:20161114T160000
DTSTAMP:20231011T190617Z
CREATED:20231011T190617Z
LAST-MODIFIED:20231011T190617Z
UID:14475-1479135600-1479139200@www.cecs.uci.edu
SUMMARY:Resource Aggregation for Collaborative Projected Video from Multiple Mobile Devices
DESCRIPTION:Name: Hung Nguyen\nDate: November 17\, 2016 \nTime: 1:30 P.M. \nLocation: EH 3206 \nCommittee: Fadi Kurdahi (Chair)\, Aditi Majumder (Co-Chair) \nAbstract:  \nWe explore and develop an embedded real time system and associated algorithms that enable an aggregation of limited resource\, low-quality\, projection-enabled mobile devices to collaboratively produce a higher quality video stream for a superior viewing experience. Such a resource aggregation across multiple projector enabled devices can lead to a per unit resource savings while moving the cost to the aggregate. \nThe pico-projectors that are embedded in mobile devices such as cell phones have a much lower resolution and brightness than standard projectors. Tiling (putting the projection area of multiple projectors in a rectangular array overlapping them slightly around the boundary) and superimposing (putting the projection area of multiple projectors right on top of each other) multiples of such projectors\, registered via automated registration through the cameras residing within those mobile devices\, result in different ways of aggregating resources across these multiple devices. Evaluation of our proof-of-concept system shows significant improvement for each mobile device in two primary factors of bandwidth usage and power consumption when using a collaborative federation of projection-embedded mobile devices. \nThe portable\, low-power\, light weight\, small size pico-projectors are key components of projection-enabled mobile devices for the future. Due to the reduction of weight and dimension and the portability nature of the projector-enabled mobile devices\, the calibrated integrated systems are prone to physical un-stabilizing of the projected image during the presentation. Thus the auto re-calibration and projected video stabilization features during the presentation time becomes essential requirements to enhance user experience. The design\, algorithm\, and implementation methods for these features will be presented in the second part of the dissertation.
URL:https://www.cecs.uci.edu/event/resource-aggregation-for-collaborative-projected-video-from-multiple-mobile-devices/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161107T150000
DTEND;TZID=America/Los_Angeles:20161107T160000
DTSTAMP:20231011T190616Z
CREATED:20231011T190616Z
LAST-MODIFIED:20231011T190616Z
UID:14472-1478530800-1478534400@www.cecs.uci.edu
SUMMARY:Low Energy\, a New Trend for Lightweight Cryptography
DESCRIPTION:Title: “Low Energy\, a New Trend for Lightweight Cryptography”\nSpeaker: Dr. Francesco Regazzoni\, ALaRI Institute of Università della Svizzera italiana\, Lugano\, Switzerland \nDate and Time:  Wednesday\, February 1\, 2017 at 11:00 a.m. \nLocation: DBH 4011 \nHost: Prof. Nikil Dutt \nAbstract: In the last decade\, several lightweight block ciphers and hash functions have been proposed. One of the metrics\, so far largely unexplored\, which has to be used to identify a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers\, this operation is the encryption of one plaintext. \nThis talk will address several approaches for reducing the energy consumption of existing block ciphers\, touching the design space of the AES algorithm\, to which few algorithmic optimizations are applied. \nThe gained experience lead to the design of Midori\, the first block cipher designed to optimize the energy consumed per bit in encryption or decryption operation. Each component of the circuit\, as well as its entire architecture of the cipher\, have been optimized for energy\, and design choices leading to low energy consumption in an electrical circuit were taken. Achieved results demonstrate that the energy consumption of Midori64 and Midori128 is much lower that current stateof the art.\n \nBiography: Dr. Francesco Regazzoni is a senior researcher at the the ALaRI Institute of Universita’ della Svizzera italiana (Lugano\, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at the ALaRI Institute of Universita’ della Svizzera italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft\, and visiting researcher at several institutions\, including NEC Labs America\, Ruhr University of Bochum\, EPFL\, and NTU Singapore. His research interests are mainly focused on embedded systems security\, covering in particular side channel attacks\, electronic design automation for security\, hardware Trojans\, low energy cryptography\, and post quantum security. He has published more than 70 journal and conference papers in the area of security and design automation\, and has been in the technical program committed of top conferences of the area. Francesco is the principal investigator and project leader at Universita’ della Svizzera italiana of the projects (SAFECrypto\, exploring lattice-based constructions as building blocks for quantum resistant cryptography)\, and CERBERO (design tools for Cyber-Physical Systems). \nView Details Here
URL:https://www.cecs.uci.edu/event/low-energy-a-new-trend-for-lightweight-cryptography/
LOCATION:CA
CATEGORIES:Seminars at CECS
ATTACH;FMTTYPE=image/png:https://cecs.uci.edu/files/2023/10/francescoreg-seminar-YBo8Ni.tmp_.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161107T150000
DTEND;TZID=America/Los_Angeles:20161107T160000
DTSTAMP:20231011T190615Z
CREATED:20231011T190615Z
LAST-MODIFIED:20231011T190615Z
UID:14470-1478530800-1478534400@www.cecs.uci.edu
SUMMARY:Prof. Mohammad A. Al Faruque receives Thomas Edison Patent Award 2016
DESCRIPTION:The Edison Patent Awards at Liberty Science Center in Jersey City. 11/3/16 Photo by John O’Boyle \nEach year the Research & Development Council of New Jersey honors the winners of the Thomas Edison Patent Awards at its annual Edison Patent Awards Ceremony & Reception in the IMAX Theater of the Liberty Science Center. Professor Al Faruque was selected as the recipient for this prestigious award for his patent in energy management in Electric Vehicle (EV) charging stations. \nThe patent\, “Network as automation platform for collaborative E-car charging at the residential premises” has provided a novel solution to solve this challenge through a  collaborative energy management strategy for the Electric Vehicle (EV) charging stations located in a residential neighborhood. The amount of energy that can be provided to the EVs connected to a single  neighboring step down transformer is limited by the connected circuit breaker at a certain point of time.  This energy management strategy will collaborate among all the EVs\, maximize the number of charged EVs and preferably reduce the local energy peaks  to the medium and low voltage electric infrastructure. \n 
URL:https://www.cecs.uci.edu/event/prof-mohammad-a-al-faruque-receives-thomas-edison-patent-award-2016/
LOCATION:CA
CATEGORIES:Awards
ATTACH;FMTTYPE=image/jpeg:https://cecs.uci.edu/files/2023/10/AlFaruqueEdisonAwards-129-ZY2dba.tmp_.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161105T150000
DTEND;TZID=America/Los_Angeles:20161105T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14478-1478358000-1478361600@www.cecs.uci.edu
SUMMARY:Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow
DESCRIPTION:Title:  “Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow”\nSpeaker: Christian Krieg\, Vienna University of Technology\, Vienna\, Austria \nDate and Time: Thursday\, November 17\, 2016 at 2:00 PM \nLocation: Donald Bren Hall 3011 \nHost:  Professor Nikil Dutt \nAbstract: We present a novel type of Trojan trigger targeted at the field-programmable gate array (FPGA) design flow. Traditional triggers base on rare events\, such as rare values or sequences. While in most cases these trigger circuits are able to hide a Trojan attack\, exhaustive functional simulation and testing will reveal the Trojan due to violation of the specification. Our trigger behaves functionally and formally equivalent to the hardware description language (HDL) specification throughout the entire FPGA design flow\, until the design is written by the place-and-route tool as bitstream configuration file. From then\, Trojan payload is always on. We implement the trigger signal using a 4-input lookup table (LUT)\, each of the inputs connecting to the same signal. This lets us directly address the least significant bit (LSB) and most significant bit (MSB) of the LUT. With the remaining 14 bits\, we realize a “magic” unary operation. This way\, we are able to implement 16 different Triggers. We demonstrate the attack with a simple example and discuss the effectiveness of the recent detection techniques unused circuit identification (UCI)\, functional analysis for nearly-unused circuit identification (FANCI) and VeriTrust in order to reveal our trigger. \nBiography: Christian Krieg received the bachelor’s and master’s degree in electrical engineering from TU Wien and is now pursuing his PhD studies on hardware security at TU Wien. His research focuses on design-level hardware Trojan design and detection. He also works on reasonable threat models for hardware Trojan attacks. Christian recently received the William McCalla best paper award for a novel hardware Trojan implementation. At a wider scope\, Christian’s research interests include cyber-physical systems security and IoT security. \nView Details
URL:https://www.cecs.uci.edu/event/malicious-lut-a-stealthy-fpga-trojan-injected-and-triggered-by-the-design-flow/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161105T150000
DTEND;TZID=America/Los_Angeles:20161105T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14480-1478358000-1478361600@www.cecs.uci.edu
SUMMARY:High Level Synthesis - Some Challenging Problems
DESCRIPTION:Title: “High Level Synthesis – Some Challenging Problems”\nSpeaker: George A. Constantinides\, Imperial College London\, UK \nDate and Time: Wednesday\, November 16\, 2016 at 11:00 A.M. \nLocation: Engineering Hall 2430 \nHost: Professor Nikil Dutt \nAbstract: High Level Synthesis – synthesis of circuits from behavioral descriptions – is a long-standing problem\, but one that appears to now have come to age. Both the demand for\, and the supply of\, quality HLS tools is now in place. However\, there are still some hard problems to be overcome in order to make HLS fully general. My research focuses on two of these: customization of memory systems to algorithms\, and customization of number representation to algorithms. After briefly introducing the work at Imperial – and encouraging PhD and postdoc applications (!) – I will spend a little time on each of these problems. In particular\, I will look at the problem of customization of memory for heap manipulating programs\, the potential of parametric analysis for synthesis of lightweight run-time scheduling changes\, and automates code refactoring for rigorously controlled accuracy / latency / area optimization. I hope to inspire the audience to consider how you may be able to contribute to these problems. \nBiography: Prof George A. Constantinides holds the Royal Academy of Engineering / Imagination Technologies Chair in Digital Computation at Imperial College London\, where he leads the Circuits and Systems research group. He has been a member of staff at Imperial since 2001. Over this time he has been the proud supervisor of 25 graduated PhD students and chaired the FPGA\, FPT\, and FPL conferences. He enjoys hard problems and espresso. \nView more here
URL:https://www.cecs.uci.edu/event/high-level-synthesis-some-challenging-problems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161104T150000
DTEND;TZID=America/Los_Angeles:20161104T160000
DTSTAMP:20231011T190622Z
CREATED:20231011T190622Z
LAST-MODIFIED:20231011T190622Z
UID:14477-1478271600-1478275200@www.cecs.uci.edu
SUMMARY:Adaptive Design: Tackling Variability Challenges in VLSI Circuits
DESCRIPTION:Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”\nSpeaker: Professor Mingoo Seok\, Columbia University\, New York \nDate:  Friday\, April 22\, 2016 \nTime:  3:00PM \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Prof. Payam Heydari \nAbstract: In this talk\, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage\, chip temperature\, manufacturing process\, and transistor aging have imposed a large amount of pessimistic margins in clock frequency\, voltage\, and device size\, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead\, in-situ\, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage\, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing\, (3) self-testing circuits and frameworks for in-field & in-situ aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented. \nBio: \nMingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University\, South Korea\, in 2005\, and the MS and PhD degree from University of Michigan in 2007 and 2011\, respectively\, all in electrical engineering. He was a member of technical staff in Texas Instruments\, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems\, including ultra-low-power computing systems\, computing systems for machine learning\, adaptive circuits and architecture\, and non-conventional computing systems. \nHe received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies\, 2005 Doctoral Fellowship from the same organization\, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013\, and IEEE Transactions on VLSI Systems since 2015.
URL:https://www.cecs.uci.edu/event/adaptive-design-tackling-variability-challenges-in-vlsi-circuits/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161004T150000
DTEND;TZID=America/Los_Angeles:20161004T160000
DTSTAMP:20231011T190615Z
CREATED:20231011T190615Z
LAST-MODIFIED:20231011T190615Z
UID:14469-1475593200-1475596800@www.cecs.uci.edu
SUMMARY:Specification and Runtime Verification of Distributed Multiprocessor Systems: Languages\, Tools and Architectures
DESCRIPTION:Name: Ahmed Nassar\nDate: September 2\, 2016 \nTime: 12:00 P.M. \nLocation: EH 3403 \nCommittee: Fadi Kurdahi (Chair)\, Rainer Doemer\, Ahmed Eltawil \nAbstract: Post-Deployment runtime verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification and testing methods. This thesis is an attempt to tackle three major barriers that need to be surmounted before RV technologies become in widespread use:\nBarrier-1: Lack of an expressive\, yet efficiently monitorable\, specification language. Distributed software behavior is projected onto an observation interface consisting of data-carrying (or parameterized) events\, such as Linux system calls including argument values\, and self-replicating deterministic finite automata (SR-DFAs) are introduced for RV purposes as well as anomaly-based intrusion detection in embedded and general-purpose software systems based on these parametric traces.\nBarrier-2: The substantial performance and power overhead of pure software RV frameworks. NUVA\, which stands for nonuniform verification architecture\, a distributed automata-based RV architecture for software specifications in the form of SR-DFAs. NUVA has been implemented over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor and can be deployed on the FPGA fabric that will reside on all next-generation processor chips. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes.\nBarrier-3: Formal specifications are hard to formulate and maintain for evolving complex embedded and general-purpose software systems. Therefore\, specification mining has long ago been envisioned to play a key role in software verification\, modification and documentation. However\, in order to scale beyond simple\, library/API-level properties having short temporal spans\, specification mining tools need to support more expressive specification languages that can capture complex\, application-level properties. This thesis introduces a bio-inspired complete specification mining methodology for SR-DFAs using an iterative and interactive mining tool\, called ParaMiner. ParaMiner relies on novel mining algorithms invoking multiple-sequence alignment (MSA) techniques to enable learning specifications from temporal slices of software behavior while overcoming the initial-state uncertainty problem.\nSR-DFAs and ParaMiner have been leveraged in a new specification-based intrusion detection (ID) framework that protects distributed\, reactive computing systems against cyberattacks having very sparse signatures\, arbitrarily long time spans and wide attack fronts. Such attacks lie outside the scope of conventional anomaly-based ID methods which typically work with short event windows and ignore manipulated data objects\, such as files and sockets. We demonstrate the effectiveness of the constructed SR-DFAs at classifying as well as resolving subtle behaviors typical of cyberattacks with varying evasion parameter values.
URL:https://www.cecs.uci.edu/event/specification-and-runtime-verification-of-distributed-multiprocessor-systems-languages-tools-and-architectures/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190612Z
CREATED:20231011T190612Z
LAST-MODIFIED:20231011T190612Z
UID:14466-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Resilience is a Critical Issue for Large-scale Platform
DESCRIPTION:Speaker:  Prof. Yves Robert\, Ecole Normale Supérieure de Lyon\, France \nTitle:  Resilience is a Critical Issue for Large-scale Platform \nDate:  Monday\, May 18\, 2015 \nTime:  11:00 a.m. – 12:00 p.m. \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost:  Prof. Jean-Luc Gaudiot \nAbstract: Resilience is a critical issue for large-scale platforms. This talk will survey fault-tolerant techniques for high-performance computing:\n– Overview of failure types and typical probability distributions\n– Brief discussion of application-specific techniques\, such as ABFT\n– The standard general-purpose technique\, checkpoint and     rollback recovery\n– Recent extensions with replication\, prediction and silent error detection\n– Relevant execution scenarios\, evaluated and compared through quantitative models.\nThe talk includes several illustrative examples and targets a general audience. \nBio: Yves Robert received his PhD degree from Institut National Polytechnique de Grenoble. He is currently a full professor in the Computer Science Laboratory LIP at ENS Lyon. He is the author of 7 books\, 130+ papers published in international journals\, and 200+ papers published in international conferences.  He is the editor of 11 book proceedings and 13 journal special issues.  He is the advisor of 28 PhD theses.  His main research interests are scheduling techniques and resilient algorithms for large-scale platforms. Yves Robert served on many editorial boards\, including IEEE TPDS.  He was the program chair of HiPC’2006 in Bangalore\, IPDPS’2008 in Miami\, ISPDC’2009 in Lisbon\, ICPP’2013 in Lyon and HiPC’2013 in Bangalore. He is a Fellow of the IEEE. He has been elected a Senior Member of Institut Universitaire de France in 2007 and renewed in 2012.  He has been awarded the 2014 IEEE TCSC Award for Excellence in Scalable Computing.  He holds a Visiting Scientist position at the University of Tennessee\, Knoxville since 2011. \n  \n 
URL:https://www.cecs.uci.edu/event/resilience-is-a-critical-issue-for-large-scale-platform/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190612Z
CREATED:20231011T190612Z
LAST-MODIFIED:20231011T190612Z
UID:14467-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Hardware Security in the Zynq All-Programmable Soc
DESCRIPTION:Title: “Hardware Security in the Zynq All-Programmable Soc”\nSpeaker: Dr. Steve Trimberger\, Xilinx \nDate:  Friday\, October 2\, 2015 \nTime:  2:00 p.m. \nLocation:  Donald Bren Hall 4011 \nHost: Prof. Fadi J. Kurdahi \nAbstract: FPGAs have grown from a simple logic replacement to fully-programmable SoC\, with multi-core CPU subsystems\, a broad spectrum of peripherals\, hundreds of thousands of gates of programmable logic and high-speed multi-gigabit transceivers. As the complexity of the underlying hardware has grown\, so has the value of the applications built in them and the data handled by them. Traditional FPGA bitstream security has been enhanced to address these greater security requirements. This talk presents an overview of hardware security issues and the security features of the Zynq All- Programmable SoC. The secure boot process includes asymmetric and symmetric authentication as well as symmetric encryption to protect software and programmable hardware during programming.During operation the hardware can disable test ports\, monitor on-chip power and temperature and detect tampering with configuration data. ARM Trust Zone is integrated through the AXI busses into both the processor and the programmable logic subsystems. \nBio: Dr. Stephen Trimberger holds a M.S. degree in ICS from UCI and a Ph.D. degree from California Institute of Technology. Since 1988\, he has been employed at Xilinx\, where he is currently Xilinx Fellow heading the Circuits and Architectures Group in Xilinx Research Labs in San Jose\, California. He was the technical leader for the XC4000 design automation software\, developed a dynamically -reconfigurable multi-context FPGA\, led the architecture definition group for the Xilinx XC4000X device families and designed the Xilinx bitstream security functions in the Virtex families of FPGAs. He led the group that developed the first die- stacked 3D FPGA prototype at Xilinx. He has served as Design Methods Chair for the Design Automation Conference\, Program Chair and General Chair for the ACM/SIGDA FPGA Symposium and on the technical programs of numerous Workshops and Symposia. He has authored five books and dozens of papers on design automation\, FPGA architectures and hardware security. He has more than 220 patents in IC design\, FPGA and ASIC architecture\, CAE\, hardware security and cryptography. His innovations appear today in nearly all commercial FPGA devices. He is a Fellow of the ACM and a Fellow of the IEEE. \nView Details Here \n 
URL:https://www.cecs.uci.edu/event/hardware-security-in-the-zynq-all-programmable-soc/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190611Z
CREATED:20231011T190611Z
LAST-MODIFIED:20231011T190611Z
UID:14464-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:CMOS Process Variations: A “Critical Operation Point” Hypothesis
DESCRIPTION:Title: CMOS Process Variations: A “Critical Operation Point” Hypothesis\nSpeaker: Dr. Janak H. Patel \nDate: May 2\, 2012 \nTime: 3:30-4:30 P.M. \nLocation: DBH 3011 \nHost: Professor Nikil Dutt \n 
URL:https://www.cecs.uci.edu/event/cmos-process-variations-a-critical-operation-point-hypothesis/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190611Z
CREATED:20231011T190611Z
LAST-MODIFIED:20231011T190611Z
UID:14465-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:IEEE Solid-State Circuits Society Webinar
DESCRIPTION:“Fundamentals of Millimeter-Wave Frequency Generation and Synthesis in Silicon”\, Presented by Payam Heydari \nThis webinar is free and open to all SSCS members. \nTue\, May 31\, 2016 9:00 AM – 10:30 AM PDT \n 
URL:https://www.cecs.uci.edu/event/ieee-solid-state-circuits-society-webinar/
LOCATION:CA
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14461-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Addressing Supply Chain Security with Split Manufacturing
DESCRIPTION:Speaker: Dr. Ted Huffmire\, Naval Postgraduate School\, Monterey\, CATitle: Addressing Supply Chain Security with Split Manufacturing\nDate: July 27\, 2012\nTime:11:00am\nLocation: Donald Bren Hall 3011\nCECS Host: Prof. Nikil Dutt \nAbstract: Security is an essential design goal in computer architecture\, and security is a concern throughout the entire lifecycle of a system. The process of designing hardware requires trusting intellectual property (IP) cores and computer-aided design (CAD) tools developed by third parties\, as well as the fabrication\, packaging\, assembly\, and delivery of the final system. Valuable IP is vulnerable to theft and modification during tape-out\, even if a perfect design free of security flaws is sent to the foundry. Of course\, no design is ever perfect\, and having a trusted foundry does not solve the problem of flawed designs. Furthermore\, the trusted foundry may not have the capability to deliver the most aggressive technology node\, volume\, yield\, or cost. Even the extraordinary step of building everything from scratch in-house\, including all of the tool chains\, both digital and analog\, is not guaranteed to result in a trustworthy design. \nBio: Ted Huffmire is an Assistant Professor of Computer Science at the Naval Postgraduate School in Monterey\, California. His research spans both computer security and computer architecture\, focusing on hardware-oriented security and the development of policy enforcement mechanisms for application-specific devices. He has a Ph.D. in computer science from the University of California\, Santa Barbara. He is a member of the IEEE and the ACM. The views presented in this talk are those of the speaker and do not necessarily reflect the views of the United States Department of Defense. \nView Details Here
URL:https://www.cecs.uci.edu/event/addressing-supply-chain-security-with-split-manufacturing-2/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14462-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:The Confluence of Communications\, Sensing and Control in Large Scale Wireless Networks
DESCRIPTION:Speaker:  Prof. Urbashi Mitra\, Electrical Engineering\, University of Southern California\nTitle:  The Confluence of Communications\, Sensing and Control in Large Scale Wireless Networks \nDate:  Friday\, November 8\, 2013 \nTime:  11:00am – 12:00pm\n \nLocation:  Donald Bren Hall 6011 \nAbstract: Modern wireless technology enables the vision of future large scale systems such as the SmartGrid\, a network of ubiquitous and heterogeneous devices wirelessly connected to the Internet\, and wireless health monitoring and health modifying sensor networks over communities and not just individuals.  All of these applications necessitate methods that simultaneously consider scale\, communication\, sensing and control. In this talk\, key elements of realizing this vision are examined.  We shall focus on novel active control methods for networks described by partially observable Markov decision processes.  Such models are very general and can encompass sensing networks\, as well as communication networks.  Following an innovations approach\, a Kalman-like filter is derived to estimate the underlying system state.  As a case-study\, numerical results are provided for physical activity detection in a heterogeneous wireless body area network.  We further examine distributed estimation in large scale networks with time-correlated behavior and explore how modern statistical methods such as compressed sensing can be applied to both the distributed estimation problem as well as the network control problem. \nBio: Urbashi Mitra received the B.S. and the M.S. degrees from the University of California at Berkeley and her Ph.D. from Princeton University.   She is currently a Professor in the Ming Hsieh Department of Electrical Engineering at the University of Southern California.  She is a member of the IEEE Information Theory Society’s Board of Governors (2002-2007\, 2012-2014) and the IEEE Signal Processing Society’s Technical Committee on Signal Processing for Communications and Networks (2012-2014). She is the recipient of:  2012 Globecom Signal Processing for Communications Symposium Best Paper Award\, 2012 NAE Lillian Gilbreth Lectureship\, USC Center for Excellence in Research Fellowship (2010-2013)\, the 2009 DCOSS Applications & Systems Best Paper Award\, IEEE Fellow (2007)\, Texas Instruments Visiting Professor (Fall 2002\, Rice University)\, 2001 Okawa Foundation Award\, 2000 OSU College of Engineering Lumley Award for Research\, and a 1996 NSF CAREER Award.  Dr. Mitra has been/is an Associate Editor for the following IEEE publications: Transactions on Signal Processing (2012–)\, Transactions on Information Theory (2007-2011)\, Journal of Oceanic Engineering (2006-2011)\, and Transactions on Communications (1996-2001).  Dr. Mitra has held visiting appointments at: the Delft University of Technology\, Stanford University\, Rice University\, and the Eurecom Institute. She served as co-Director of the Communication Sciences Institute at the University of Southern California from 2004-2007.  Her research interests are in: wireless communications\, communication and sensor networks\, detection and estimation and the interface of communication\, sensing and control.
URL:https://www.cecs.uci.edu/event/the-confluence-of-communications-sensing-and-control-in-large-scale-wireless-networks/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14463-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:A Client-centric Approach to Interoperable Clouds
DESCRIPTION:Speaker: Mukesh Singhal\, Department of Computer Science\, University of California\, Merced\nTitle: A Client-centric Approach to Interoperable Clouds \nDate: Friday\, December 6\, 2013 \nTime: 11:00am – 12:00pm \nLocation: Donald Bren Hall 6011 \nAbstract: Cloud computing offers several benefits in terms of scalability\, cost and performance. These benefits have contributed to the wide-scale acceptance of the cloud computing paradigm and growing adoption by the industry. With this growth\, limitations of this paradigm are beginning to surface. One such limitation is that contemporary clouds are not interoperable. This limitation arises due to proprietary technologies\, heterogeneous interfaces and the tight tethering of service offerings to the host cloud. Current research solutions for enabling cloud interoperability are predominantly provider-centric\, requiring cloud providers to adopt and implement the changes that facilitate interoperation. This approach faces several hurdles and can take a long time to hit the market. In the meantime\, a client-centric approach to interoperation is necessary for providing its benefits to consumers in the current cloud ecosystem. To this end\, a novel framework for cloud interoperation called collaborative cloud computing is proposed. The proposed framework provides dynamic\, on-the-fly collaborations and resource sharing among cloud-based services\, without pre-established collaboration agreements or standardized interfaces\, through use of client-controlled mediating agents called proxies. \nBio: Mukesh Singhal is a Chancellor’s Professor in the Computer Science and Engineering program at the University of California\, Merced. He received a PhD degree in Computer Science from the University of Maryland\, College Park\, in May 1986. From 1986 to 2001\, he was a faculty in the department of Computer and Information Science at The Ohio State University. From 1998 to 2001\, he served as the program director of the Operating Systems and Compilers program at the National Science Foundation. From 2001 to 2012\, he was a Professor and Gartner Group endowed chair in Network Engineering in the Department of Computer Science at The University of Kentucky. His current research interests include distributed and cloud computing\, cyber-security\, and computer networks. He has published over 240 refereed articles in these areas. He is a Fellow of IEEE and he was a recipient of 2003 IEEE Technical Achievement Award. He has coauthored four books titled “Advanced Concepts in Operating Systems”\, McGraw-Hill\, New York\, 1994\, “Distributed Computing Systems”\, Cambridge University Press 2007\, “Data and Computer Communications: Networking and Internetworking”\, CRC Press\, 2001\, and “Readings in Distributed Computing Systems”\, IEEE Computer Society Press\, 1993. He has served in the editorial board of “IEEE Trans. on Dependable and Secure Computing”\, “IEEE Trans. on Parallel and Distributed Systems”\, “IEEE Trans. on Data and Knowledge Engineering”\, and “”IEEE Trans. on Computers”. \n 
URL:https://www.cecs.uci.edu/event/a-client-centric-approach-to-interoperable-clouds/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190554Z
LAST-MODIFIED:20231011T190555Z
UID:14451-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Circuits and Systems Seminar Series
DESCRIPTION:Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”\nSpeaker: Prof Mingoo Seok\, Columbia University\, New York\, NY \nDate and Time: Friday\, April 22\, 2016 at 3:00 P.M. – 4:00 P.M. \nLocation: Engineering Hall 2430 \nHosts: Professor Payam Heydari \nAbstract: In this talk\, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage\, chip temperature\, manufacturing process\, and transistor aging have imposed a large amount of pessimistic margins in clock frequency\, voltage\, and device size\, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead\, in-sit\, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage\, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing\, (3) self-testing circuits and frameworks for in-field & in-sit aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented. \nBio: Mingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University\, South Korea\, in 2005\, and the MS and PhD degree from University of Michigan in 2007 and 2011\, respectively\, all in electrical engineering. He was a member of technical staff in Texas Instruments\, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems\, including ultra-low-power computing systems\, computing systems for machine learning\, adaptive circuits and architecture\, and non-conventional computing systems. He received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies\, 2005 Doctoral Fellowship from the same organization\, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013\, and IEEE Transactions on VLSI Systems since 2015. \nView Details Here
URL:https://www.cecs.uci.edu/event/circuits-and-systems-seminar-series/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190553Z
LAST-MODIFIED:20231011T190555Z
UID:14450-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:CECS Hosts IWCR 2016
DESCRIPTION:View details here
URL:https://www.cecs.uci.edu/event/cecs-hosts-iwcr-2016/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14391-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Building Fake Body Parts: Real-Time Digital Mockups of Physiological Systems
DESCRIPTION:Title:  Building Fake Body Parts: Real-Time Digital Mockups of Physiological SystemsSpeaker: Prof. Frank Vahid\, University of California\, Riverside\nLocation: 6011 Donald Bren Hall\nDate/Time: Friday\, October 26\, 2012\, 11:00am – 12:00pm\nHost: Prof. Eli Bozorgzadeh \nAbstract: Designing computer-based medical devices like pacemakers or ventilators is hard\, in part because testing can’t be done on real humans. PC-based simulations are slow and inaccurate. Using physical mockups\, like connecting a ventilator device to a balloon acting as a lung\, can’t support sufficiently diverse scenarios\, like fluid in the lungs. This talk describes joint UCR/UCI work on developing “digital mockups” — models of physiological systems that execute in real-time\, supporting thorough testing of device software. We show that FPGAs (field-programmable gate arrays) — widely-available programmable chips having a unique execution approach that we’ll describe — are an excellent match for executing physiological models\, yielding order-of-magnitude speedups over PCs\, GPUs\, and other computing approaches. The talk describes the synthesis approach to automatically converting models\, consisting of thousands of differential equations\, into networks of processing elements on FPGAs. Real-time execution of physiological models can also be useful in building complete human simulators\, used today medical and nursing schools. More broadly\, real-time execution of physical systems (chemical\, biological\, mechanical\, physiological\, etc.) can be useful in the design of a wide variety of what today are called cyber-physical systems– systems where computers interact closely with the physical world – including automobiles\, aircraft\, medical equipment\, military equipment\, manufacturing systems\, and much more. \nBio: Frank Vahid is a Professor of Computer Science and Engineering at the University of California\, Riverside (B.S. 1988 Univ. of Illinois in 1988\, M.S./Ph.D. 1990/1994 Univ.of California\, Irvine. He is author of several textbooks on embedded systems and digital design. His current research interests include creating technologies for cyber-physical systems (http://www.cs.ucr.edu/~vahid/digitalmockups/)\, developing customizable assistive monitoring systems for home-alone aging/disabled persons and their caretakers http://www.cs.ucr.edu/~vahid/assistivemonitoring/\, and creating the next generation of online interactive animated learning material (http://pcpp.zyante.com).\nView Details Here
URL:https://www.cecs.uci.edu/event/building-fake-body-parts-real-time-digital-mockups-of-physiological-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160928T150000
DTEND;TZID=America/Los_Angeles:20160928T160000
DTSTAMP:20231011T190616Z
CREATED:20231011T190616Z
LAST-MODIFIED:20231011T190616Z
UID:14471-1475074800-1475078400@www.cecs.uci.edu
SUMMARY:Distinguished Lecture at CECS
DESCRIPTION:Speaker: Prof. Massimo Poncino\, Polytechnic University of Turin\, Italy\nTitle: Towards Computer-Aided Design of Electrical Energy Systems:Challenges and Solutions\nDate: Friday\, April 22\, 2016\nTime: 11:00am – 12:00pm\nLocation: Engineering Hall 2430 \nHost: Prof. Mohammad Al Faruque \n\nView Details Here
URL:https://www.cecs.uci.edu/event/distinguished-lecture-at-cecs-2/
LOCATION:CA
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160818T150000
DTEND;TZID=America/Los_Angeles:20160818T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190553Z
LAST-MODIFIED:20231011T190555Z
UID:14449-1471532400-1471536000@www.cecs.uci.edu
SUMMARY:PhD Defense:
DESCRIPTION:Name:  Aras Pirbadian\nDate: August 29\, 2016 \nTime: 3:30pm \nLocation:  EH 3403 \nCommittee: Ahmed Eltawil (Chair)\, Fadi Kurdahi\, Rainer Doemer \nWith the continued scaling of chip manufacturing technologies\, the significance of process variation in performance of the systems is increasing. Specifically\, process variation results in growing voltage and frequency overhead margins required to ensure error free operation of circuits. However\, the traditional practice of overdesigning the systems to cover process variation is no longer an efficient design methodology in an age with high demands for processing power and limited energy supplies. In this dissertation\, a novel analytical model is proposed to predict the required margin accurately in the early stages of design space exploration. The model can be used to optimize the system overhead in error free calculations or to release the bound by full correctness in error tolerant parts of systems and optimize the energy vs. performance trade-off. Additionally\, this model also considers the statistics of the inputs of the circuit as compared to other existing efforts enabling it to achieve close predictions of full circuit simulation results in a short time. This model is finally used in an adaptive carry select/ripple carry adder configuration to demonstrate the potential achievable power savings. \nGrowing variation in newer technology nodes is not always a negative side effect. The increased inherent randomness in the process manufacturing technology can be utilized to develop unique physically unclonable functions (PUFs). These functions are irreproducible hardware-based authenticating systems\, which do not require memory-based storage. A low overhead delay-based PUF using the variation of the silicon manufacturing is also proposed in the second part of this work. The proposed PUF uses a simple and efficient structure to convert the randomness of the manufacturing process into random responses to fixed challenges in identically designed circuits.
URL:https://www.cecs.uci.edu/event/phd-defense/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160804T150000
DTEND;TZID=America/Los_Angeles:20160804T160000
DTSTAMP:20231011T190537Z
CREATED:20231011T190537Z
LAST-MODIFIED:20231011T190537Z
UID:14448-1470322800-1470326400@www.cecs.uci.edu
SUMMARY:Progression and Edge Intelligence Framework for IoT Systems
DESCRIPTION:Name:  Zhenqiu Huang\nDate: July 29\, 2016 \nTime: 10:00am \nLocation:  EH 4106 \nCommittee: Kwei-Jay Lin (Chair)\, Fadi Kurdahi\, Mohammad Al Faruque \nAbstract: This thesis studies the issues on building and managing future Internet of Things (IoT)\nsystems. IoT systems consist of distributed components with services for sensing\, processing\,\nand controlling through devices deployed in our living environment as part of the global\ncyber-physical ecosystem. \nSystems with perpetually running IoT devices may use a lot of energy. One challenge is to\nimplement good management policies for energy saving. In addition\, a large scale of devices\nmay be deployed in wide geographical areas through low bandwidth wireless communication\nnetworks. This brings the challenge of con
URL:https://www.cecs.uci.edu/event/progression-and-edge-intelligence-framework-for-iot-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160715T150000
DTEND;TZID=America/Los_Angeles:20160715T160000
DTSTAMP:20231011T190537Z
CREATED:20231011T190537Z
LAST-MODIFIED:20231011T190537Z
UID:14447-1468594800-1468598400@www.cecs.uci.edu
SUMMARY:Area/speed tradeoffs in a retargetable FPGA-optimized processor core
DESCRIPTION:Speaker:  Marco Zec\, University of Zagreb \nTitle:  “Area/speed tradeoffs in a retargetable FPGA-optimized processor core” \nDate:  Friday\, July 15\, 2016 \nTime:  11:00 AM \nLocation:  CECS Conference Room (Engineering Hall 3206) \nHost:  Prof. Daniel Gajski \nAbstract: Can portable yet efficient\, FPGA-optimized processor cores be constructed using generic HDL\, without depending on any vendor-specific primitives?  In this talk we will discuss the techniques applied for achieving a balance between instruction throughput and FPGA resource utilization in a synthesizable scalar core which outperforms its proprietary counterparts (MicroBlaze\, Nios\, Cortex-M3) by 20% to 40% in industry-standard integer benchmarks (CoreMark\, Dhrystone per MHz) while\noccupying less than 1000 6-input LUTs\, and less than 650 LUTs in an area-optimized configuration.  The core can be retargeted to execute subsets of either the emerging RISC-V or the traditional MIPS instruction sets\, and is supported by contemporary GNU-based software toolchains.\n \nBio: Marko Zec received a BSc in electrical engineering from the University of Zagreb\, where since 2005. he has been working as a project scientist on various computer networks projects with funding from ICSI Berkeley\, the FreeBSD foundation\, Boeing Integrated Defense Systems\, and Ericsson. His research interests include operating systems\, computer networks\, software-based packet processing datapaths\, and programmable logic. \nView Details
URL:https://www.cecs.uci.edu/event/area-speed-tradeoffs-in-a-retargetable-fpga-optimized-processor-core/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160422T150000
DTEND;TZID=America/Los_Angeles:20160422T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190554Z
LAST-MODIFIED:20231011T190555Z
UID:14452-1461337200-1461340800@www.cecs.uci.edu
SUMMARY:"Towards Computer-Aided Design of Electrical Energy Systems: Challenges and Solutions"
DESCRIPTION:Title: “Towards Computer-Aided Design of Electrical Energy Systems: Challenges and Solutions”\nSpeaker: Professor Massimo Poncino\, Polytechnic University of Turin\, Italy \nDate and Time: Friday\, April 22\, 2016 at 11:00 A.M. – 12:00 P.M. \nLocation: Engineering Hall 2430 \nHosts: Professor Mohammad Al Faruque \nAbstract: Electrical energy systems (EESs) include energy generation\, distribution\, storage\, and consumption\, and involve many diverse components and sub-systems to implement these tasks. In this talk we discuss fundamental concepts towards a first attempt in applying EDA design methodologies that are widely used for electronics systems design to the case of the design of EESs. CAD for EESs encompasses modeling\, simulation\, design and optimization and is a challenging task that mandates a multidisciplinary and heterogeneous approach. We identify similarities and differences between electrical energy systems and electronics systems in order to inherit as much as possible the profound legacy resources of EDA. The talk analyzes in deeper details the issue of representation\, modeling\, and simulation of EESs\, tasks that naturally precede synthesis and optimization in a typical design flow.\n\n\n\n\n\nBio: Massimo Poncino is Full Professor of Computing Systems at Politecnico di Torino. Prior to that\,\nhe was an Associate Professor (from 2004 to 2006) at Politecnico di Torino\, Associate Professor (from 2001 to 2004) at Università di Verona\, and Assistant Professor (from 1995 to 2001) at Politecnico di Torino. From 1993 to 1994 he was a Visiting Scientist at the Department of Electrical and Computer Engineering of the University of Colorado\, Boulder\, USA. He holds a Dr. Eng. degree in Electrical Engineering (1989) and a PhD degree in Computer Engineering\, both from Politecnico di Torino (1993).His research interests include the design automation of digital systems\, with emphasis on low\n-power embedded systems\, modeling and the simulation of systems -on- chip\, and automatic synthesis of digital systems. He has coauthored more than 300 publications in the above areas\, including one book on energy -efficient memory design. Massimo Poncino has served as member of Technical Program Committee of more than 50 IEEE and ACM conferences. He was the Technical Program Chair of the 2011 IEEE/ACM Symposium on Low-Power Electronics and Design and General co-Chair for the same conference in 2012. He has served in the Editorial Board of the IEEE Transactions on CAD from 2006 to 2011\, and is currently serving in the Editorial Board of IEEE Design & Test and ACM Transactions on Design Automation of Electronic Systems (TODAES). Prof. Poncino is a Senior Member of IEEE\, member of the ACM SIGDA Low -Power Technical Committee\, and a Member the Circuit and Systems Society.\n\nView Details Here
URL:https://www.cecs.uci.edu/event/towards-computer-aided-design-of-electrical-energy-systems-challenges-and-solutions/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160404T150000
DTEND;TZID=America/Los_Angeles:20160404T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14445-1459782000-1459785600@www.cecs.uci.edu
SUMMARY:Power Optimization for Medical Sensing Systems
DESCRIPTION:Name:  Jun Luan\nLocation:  EH 4106 \nDate: February 24\, 2016 \nTime: 1:00pm \nCommittee: Pai Chou (Chair)\, Mohammad Al Faruque\, Fadi Kurdahi \nAbstract:  \nMedical sensing systems collect and analyze the patients’ physiological data for monitoring\, aid or diagnostic purposes. System designers are faced with stringent requirements on not only correctness and safety but also power. Reference designs and multi-purpose platforms help to significantly shorten the development cycle. \nThis work takes a cross-layer\, system-level\, platform-based approach to addressing the problem of saving power in a class of portable medical system. We propose a low-power medical sensing system that can be used to monitor Electrocardiography (ECG)\, Photo- plethysmogram (PPG)\, and muscle tension. It also includes a hand gesture recognition system to aid mobility-impaired patients. \nWe explore the theory and application of a compressive sensing framework to medical signal processing. A novel compressive sensing-based ECG compression algorithm and a dominant frequency extraction-based PPG heart-rate calculation algorithm are proposed to reduce the system power. The unique combination of hardware structure and software signal-processing algorithms makes low-power design possible. The system test results show that the proposed system is superior to existing works in terms of power consumption and system size.
URL:https://www.cecs.uci.edu/event/power-optimization-for-medical-sensing-systems/
LOCATION:CA
CATEGORIES:PhD Defenses
END:VEVENT
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