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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040127T150000
DTEND;TZID=America/Los_Angeles:20040127T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14348-1075215600-1075219200@www.cecs.uci.edu
SUMMARY:System-Level Design Methodology
DESCRIPTION:Presented by Professor Daniel Gajski\, University of California\, Irvine\nASP-DAC 2004\nPacifico Yokohama\, Yokohama\, Japan\nJanuary 27\, 2004\ndownload pdf
URL:https://www.cecs.uci.edu/event/system-level-design-methodology/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040116T150000
DTEND;TZID=America/Los_Angeles:20040116T160000
DTSTAMP:20231011T183337Z
CREATED:20231011T183337Z
LAST-MODIFIED:20231011T183337Z
UID:14302-1074265200-1074268800@www.cecs.uci.edu
SUMMARY:System-Level Design: Only the Radical Will Survive
DESCRIPTION:  \nLecture Slides \nSystem-Level Design: Only the Radical Will Survive\n\n\n\n\nSpeaker\n\n\nDr. Reinaldo Bergamaschi\nIBM T. J. Watson Research Center\, Yorktown Heights \, NY\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, January 16\, 2004\nRefreshments served at 10:00 a.m.\, lecture begins at 10:30 a.m.\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe term “system-level design” has been defined\, used and abused countless times by designers\, cad developers and most of all\, tools sales people. By now we all know what is supposed to be\, and it ‘ain’t pretty` (despite the claims by cad vendors). In this talk\, I will argue that for the past 5 years (at least) we have tried to develop system-level tools by fattening the already beaten up ASIC design methodology\, by exaggerating the advantages of high-level languages\, by overblowing the benefits of software-related methodologies for designing hardware\, among other very incremental approaches. The design methodologies and tools currently used for system-on-chip design are an evolution of ASIC and board-level design tools. Such an incremental approach has been ineffective in closing the productivity design gap. I will analyze the current push to use high-level languages and software approaches for hardware design\, and try to convince the audience that such attempts\, while in the right direction\, are far from sufficient. I will argue that radical new approaches for system design are needed if we want to be able to design new products in shorter time-to-market. I will discuss some of the approaches we are developing at IBM Research and speculate on possible new research avenues.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nReinaldo Bergamaschi graduated in Electronics Engineering from the Aeronautics Institute of Technology\, Sao Jose dos Campos\, Brazil \, in 1982\, and in 1984 he received the M.E.E degree from the Philips International Institute\, Eindhoven\, The Netherlands. In 1989 he obtained the Ph.D. degree in Electronics and Computer Science from the University of Southampton\, Southampton\, England\, and joined the IBM T. J. Watson Research Center\, Yorktown Heights \, USA. He has worked extensively on RTL\, behavioral and system-level design tools and methodologies. He was the main architect of IBM’s high-level synthesis system and he is currently developing system-level modeling and synthesis tools for core-based\, platform-based designs. He has participated in numerous conference committees and given several tutorials and lectures on high-level and system-level design issues and tools.\n\n\n\nSystem-Level Design: Only the Radical Will Survive\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/system-level-design-only-the-radical-will-survive/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040113T150000
DTEND;TZID=America/Los_Angeles:20040113T160000
DTSTAMP:20231011T193551Z
CREATED:20231011T185036Z
LAST-MODIFIED:20231011T193551Z
UID:14355-1074006000-1074009600@www.cecs.uci.edu
SUMMARY:The Nicholas Endowment Presents CECS a $100\,000 Gift
DESCRIPTION:The Nicholas Endowment Presents CECS a $100\,000 Gift\nJanuary 13 \, 2004 \nThe Center for Embedded Computer Systems at the University of California\, Irvine recently received a $100\,000 gift from The Nicholas Endowment. Craig S. Gunther\, Chairmen of Board of Trustees\, The Nicholas Foundation\, presented the gift to Daniel D. Gajski\, The Henry Samueli “Turing” Endowed Chair and Director\, Center for Embedded Computer Systems. The gift will support two UCI graduate students performing interdisciplinary research in embedded systems for the 2005-2006 academic year. The selected students will be designated Henry T. Nicholas\, III Research Fellows. The fellowships will provide a stipend plus the payment of tuition and fees for one academic year. The candidates will be selected by an independent committee composed of CECS faculty and representatives from The Nicholas Endowment. \nNicolaos G. Alexopoulos\, Dean of the Henry Samueli School of Engineering at UCI stated: “This gift by Dr. and Mrs. Henry T. Nicholas\, III will strengthen our efforts to create a cluster of outstanding graduate students in Embedded Systems Design. This is a pervasive and expanding field in all sectors of technology and therefore it impacts our economy to a significant degree.”
URL:https://www.cecs.uci.edu/event/the-nicholas-endowment-presents-cecs-a-100000-gift/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031219T150000
DTEND;TZID=America/Los_Angeles:20031219T160000
DTSTAMP:20231011T184638Z
CREATED:20231011T184638Z
LAST-MODIFIED:20231011T184638Z
UID:14345-1071846000-1071849600@www.cecs.uci.edu
SUMMARY:Estimation and Exploration Automation of System Level Design
DESCRIPTION:Estimation and Exploration Automation of System Level Design\nby Lukai Cai\nRecently\, as system design is becoming more and more challenging due to decreasing timeto-\nmarket and increasing system complexities\, trends are emerging to move the design process to\nhigher levels of abstraction. System-level design demands corresponding approaches that efficiently explore the complete system design space and rapidly evaluate a large number of design alternatives in a short amount of time. \nThis work proposes fast estimation and efficient exploration approaches for system synthesis\ndesign flow. It starts with the system behavior which represents the design functionality\, generates\nthe system architecture from the system behavior\, and finally maps the system behavior to the\nsystem architecture. \nIn this work\, we target at complex system design: the system behavior is modeled concurrently\nand hierarchically\, the system architecture is assembled by processing elements with\ndifferent attributes and incompatible communication protocols. Because our approaches are all\nimplemented at high abstraction levels and have relatively low time complexities\, we meet the\nrequirement for fast estimation and exploration of the system level design.
URL:https://www.cecs.uci.edu/event/estimation-and-exploration-automation-of-system-level-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031209T150000
DTEND;TZID=America/Los_Angeles:20031209T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14303-1070982000-1070985600@www.cecs.uci.edu
SUMMARY:The Fundamentals: Moore's Law\, Microarchitecture\, and the Microprocessor of the Year 2014
DESCRIPTION:The Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\nSpeaker\n\n\nProfessor Yale Patt\nThe University of Texas at Austin\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Jean-Luc Gaudiot\ngaudiot@uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 9\, 2003\nRefreshments at 1:15pm\, Lecture begins at 1:30pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nMoore’s Law promises very soon more than a billion transistors on a chip processing at more than 10 GHz. But\, what else does Moore ‘s Law tell us about the future of high performance microprocessors. Is there anything left to do in the microarchitecture to make use of all this capability\, or should we fold our tents and go home? Many claim we have reached the end of our rope. In this talk\, I hope to spend a little time discussing the rationale of the naysayer and then move on to what we can do. Per usual\, I plan to tie my comments to the fundamentals\, because I believe it is always the fundamentals that provide the insights to new knowledge. Finally\, I will discuss what I think we will see in the microprocessor of the year 2014\, including the block-structured ISA\, stronger use of SSMT\, greater use of microcode\, dedicated infrequently used functional units\, and most importantly\, a stronger coupling with the compiler\, language\, and algorithm technologies. If time permits\, I will discuss some things I do not think we will see on the chip\, like qbits and machines that think.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nYale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell\, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He directs the Ph.D. research of 12 graduate students in computer architecture and teaches both the freshman introduction to computing and his graduate course in Microarchitecture. He has received the highest honors in his field for his research and teaching\, including the 1996 IEEE/ACM Eckert-Mauchly Award for his contributions to high performance microprocessor design and the 2000 ACM Karl V. Karlstrom Outstanding Educator Award for his contributions to education. He has had\, for the past 35 years\, an active consulting practice\, including long term associations with Intel\, Digital\, NCR\, Motorola\, and others. His freshman textbook “Introduction to Computing Systems: from bits and gates to C and beyond\,” has been adopted by more than 100 universities world-wide. It is co-authored with Professor Sanjay Patel of the University of Illinois . McGraw-Hill just released the second edition this fall. Yale Patt is a Fellow of both the IEEE and the ACM.\n\n\n\nThe Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\n\n\n\nMcDonnell Douglas Auditorium at Engineering Gateway.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nLecture began at 1:30pm at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nProfessor Yale Patt talking about microarchitecture.\nview larger image
URL:https://www.cecs.uci.edu/event/the-fundamentals-moores-law-microarchitecture-and-the-microprocessor-of-the-year-2014/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031120T150000
DTEND;TZID=America/Los_Angeles:20031120T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14349-1069340400-1069344000@www.cecs.uci.edu
SUMMARY:System Debugging and Verification: A New Challenge
DESCRIPTION:Presented by Professor Daniel Gajski and Samar Abdi\, University of California\, Irvine\nVerify 2003\nNovember 20\, 2003\ndownload pdf
URL:https://www.cecs.uci.edu/event/system-debugging-and-verification-a-new-challenge/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031107T150000
DTEND;TZID=America/Los_Angeles:20031107T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14350-1068217200-1068220800@www.cecs.uci.edu
SUMMARY:Covalidation of Hardware/Software Systems
DESCRIPTION:Presented by Professor Ian G. Harris\, University of California\, Irvine\nIntel Test Research Symposium\nSanta Clara\, CA\nNovember 7\, 2003\ndownload pdf
URL:https://www.cecs.uci.edu/event/covalidation-of-hardware-software-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030930T110000
DTEND;TZID=America/Los_Angeles:20030930T120000
DTSTAMP:20231011T180215Z
CREATED:20231011T180215Z
LAST-MODIFIED:20231011T180215Z
UID:14208-1064919600-1064923200@www.cecs.uci.edu
SUMMARY:SCESS 2003 Award
DESCRIPTION:Marshall Lee presenting 2nd place award citation to Sudeep Pasricha\, graduate student\, UCI\n  \n 
URL:https://www.cecs.uci.edu/event/scess-2003-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030919T150000
DTEND;TZID=America/Los_Angeles:20030919T160000
DTSTAMP:20231205T135318Z
CREATED:20231011T185235Z
LAST-MODIFIED:20231205T135318Z
UID:14362-1063983600-1063987200@www.cecs.uci.edu
SUMMARY:SPARK
DESCRIPTION:Release Date: September 19\, 2003Web Site: https://www.cecs.uci.edu/~spark/ \nSPARK is a C-to-VHDL high-level synthesis framework that employs a set of innovative compiler\, parallelizing compiler\, and synthesis transformations to improve the quality of high-level synthesis results. The compiler transformations have been re-instrumented for synthesis by incorporating ideas of mutual exclusivity of operations\, resource sharing and hardware cost models. The SPARK methodology is particularly targeted to control-intensive microprocessor functional blocks and multimedia and image processing applications. We have validated the effectiveness of our approach and evaluated the various optimizations for large real-life applications such as the Instruction Length Decoder from the Intel Pentium and multimedia applications such as MPEG-1\, MPEG-2 and the GIMP image processing tool. \nReference:\nR. Goering\, “Tool promises parallelizing synthesis\,” EE Times\, December 19\, 2003\nview full article
URL:https://www.cecs.uci.edu/event/spark/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030722T150000
DTEND;TZID=America/Los_Angeles:20030722T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14304-1058886000-1058889600@www.cecs.uci.edu
SUMMARY:Smart Cameras as High Performance Embedded Systems
DESCRIPTION:by Professor Wayne Wolf\, Princeton University\,McDonnell Douglas Auditorium\, University of California\, Irvine\, CA\nDistinguished Lecture\, July 22\, 2003\nAbstract :: Lecture Slides :: Pictures 
URL:https://www.cecs.uci.edu/event/smart-cameras-as-high-performance-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030606T150000
DTEND;TZID=America/Los_Angeles:20030606T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14388-1054911600-1054915200@www.cecs.uci.edu
SUMMARY:CECS DAC Open House
DESCRIPTION:
URL:https://www.cecs.uci.edu/event/cecs-dac-open-house-2/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030513T150000
DTEND;TZID=America/Los_Angeles:20030513T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14305-1052838000-1052841600@www.cecs.uci.edu
SUMMARY:Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems
DESCRIPTION:by Professor Kang Shin\, University of Michigan\,McDonnell Douglas Auditorium\, University of California\, Irvine\, CA\nDistinguished Lecture\, May 13\, 2003\nAbstract :: Lecture Slides :: Pictures
URL:https://www.cecs.uci.edu/event/real-time-dynamic-voltage-scaling-for-low-power-embedded-operating-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030509T100000
DTEND;TZID=America/Los_Angeles:20030509T120000
DTSTAMP:20231011T192949Z
CREATED:20231011T180419Z
LAST-MODIFIED:20231011T192949Z
UID:14228-1052474400-1052481600@www.cecs.uci.edu
SUMMARY:Statistical Tools and Methodologies for Delay Test and Timing Validation
DESCRIPTION:by Li-C. Wang\, UCSB\, ECE DepartmentMay 9\, 2003
URL:https://www.cecs.uci.edu/event/statistical-tools-and-methodologies-for-delay-test-and-timing-validation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030301T100000
DTEND;TZID=America/Los_Angeles:20030301T120000
DTSTAMP:20231011T180215Z
CREATED:20231011T180215Z
LAST-MODIFIED:20231011T180215Z
UID:14209-1046512800-1046520000@www.cecs.uci.edu
SUMMARY:IEEE Computer Society Certificate of Appreciation 2003
DESCRIPTION:A certificate presented for creditable service to any Computer Society activity or program was presented to Professor Ian G. Harris.
URL:https://www.cecs.uci.edu/event/ieee-computer-society-certificate-of-appreciation-2003/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020919T010000
DTEND;TZID=America/Los_Angeles:20020919T120000
DTSTAMP:20231011T192748Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T192748Z
UID:14219-1032397200-1032436800@www.cecs.uci.edu
SUMMARY:Reconfigurable Systems
DESCRIPTION:by Majid Sarrafzadeh\, UCLA\, Computer Science DepartmentSeptember 19\, 2002
URL:https://www.cecs.uci.edu/event/reconfigurable-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020910T060000
DTEND;TZID=America/Los_Angeles:20020910T120000
DTSTAMP:20231011T180215Z
CREATED:20231011T180215Z
LAST-MODIFIED:20231011T180215Z
UID:14212-1031637600-1031659200@www.cecs.uci.edu
SUMMARY:2002 Southern California Embedded Systems Symposium
DESCRIPTION:Center for Embedded Computer Systems\nUniversity of California\, Irvine \nSeptember 10\, 2002\nJazz Semiconductor Auditorium\n4311 Jamboree Road\nNewport Beach\, CA \n\n\n\n\n\n\n\n8:30 am\n\n\n8:45 am\n\n\n9:00 am\n\n\n10:00 am\n\n\n11:00 am\n\n\n12:00 nn\n\n\n1:15 pm\n\n\n2:30 pm\n\n\n3:00 pm\n\n\n\n\n\n\n\n\n\n\n\n\nContinental Breakfast\n\n\n\nWelcome: Chancellor\, Professor Ralph J. Cicerone\, UCI\n\n\nSession 1: System Design \n\n\n\n\n“Optimal Indexing for Cache Miss Reduction in Embedded Systems”\, Professor Tony Givargis\, ICS\, UCI\n\n\n\n“System-on-a-Chip Platform Tuning for Embedded Systems”\, Professor Frank Vahid\, CS\, UCR\n\n\n\n\n\n\nSession 2: Novel Architectures \n\n\n\n\n“Area and System Clock Effects on Simultaneous MultiThreading and Chip MultiProcessing Processors”\, Professor Jean-Luc Gaudiot\, ECE\, UCI\n\n\n\n“Architectural Exploration of Programmable Core Based Designs”\, Professor Nikil Dutt\, ICS\, UCI\n\n\n\n\n\n\nSession 3: Embedded Software \n\n\n\n\n“Embedded Instrumentation Co-Design”\, Professor Pai Chou\, ECE\, UCI\n\n\n\n“Power Management in Embedded Applications and Systems Software”\, Professor Rajesh Gupta\, CSE\, UCSD\n\n\n\n\n\n\nLunch: Speaker \n\n\n\n\n“SRC Programs and Plans in Circuits and Systems Design”\, Dr. Justin Harlow\, Semiconductor Research Corporation\n\n\n\n\n\n\nPanel: Future Engineering Challenges in Embedded Systems \n\n\n\n\nModerator:\nProfessor Daniel D. Gajski\, ICS\, UCI\n\n\n\nPanelists:\nMohamed S. Ben Romdhane\, Conexant Systems\n\n\n\n\nVolkan Ozguz\, Chief Scientist\, Irvine Sensors Corp.\n\n\n\n\nRonald P.Quagliara\, Group President\, Emulex Corp.\n\n\n\n\nDr. Edward L. Staton\, CTO\, MSC Software\n\n\n\n\nJohn S. Walley\, Technical Director\, Skyworks Inc.\n\n\n\n\n\n\nSession 4: System Testing \n\n\n\n\n“Novel Test Approaches for Aggressive SoC Designs”\, “Test Volume and Application Time Reduction Through Scan Chain Concealmen\,'” Professor Alex Orailoglu\, CS\, UCSD\n\n\n\n\n\n\nSession 5: Low Power \n\n\n\n\n“Customizable Embedded Processor Architectures for Low Power and High Performance”\, Professor Alex Orailoglu\, CS\, UCSD\n\n\n\n“SoC Power Estimation and Optimization”\, Professor Wolfgang Nebel\, University of Oldenburg\, Germany\n\n\n\n“Design Methodologies and Tools for Battery-Aware Mobile Embedded Systems”\, Professor Sujit Dey\, ECE\, UCSD
URL:https://www.cecs.uci.edu/event/2002-southern-california-embedded-systems-symposium/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020826T150000
DTEND;TZID=America/Los_Angeles:20020826T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14351-1030374000-1030377600@www.cecs.uci.edu
SUMMARY:Design Methodology for Systems-On-Chip
DESCRIPTION:Presented by Professor Daniel Gajski\, University of California\, Irvine\nIEEE Orange County Computer Society\nWyndham Gardens Hotel\, Costa Mesa\, CA\nAugust 26\, 2002\ndownload pdf
URL:https://www.cecs.uci.edu/event/design-methodology-for-systems-on-chip/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020823T020000
DTEND;TZID=America/Los_Angeles:20020823T120000
DTSTAMP:20231011T193148Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T193148Z
UID:14220-1030068000-1030104000@www.cecs.uci.edu
SUMMARY:Worst-Case Performance Analysis of Parallel Communicating Processors
DESCRIPTION:by Wolfgang Rosensteil\, University of Tuebingen\, GermanyAugust 23\, 2002
URL:https://www.cecs.uci.edu/event/worst-case-performance-analysis-of-parallel-communicating-processors/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020806T030000
DTEND;TZID=America/Los_Angeles:20020806T120000
DTSTAMP:20231011T192457Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T192457Z
UID:14221-1028602800-1028635200@www.cecs.uci.edu
SUMMARY:Low-Power Liquid Crystal Display Systems
DESCRIPTION:by Naehyuck Chang\, Seoul National UniversityAugust 6\, 2002
URL:https://www.cecs.uci.edu/event/low-power-liquid-crystal-display-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020802T050000
DTEND;TZID=America/Los_Angeles:20020802T120000
DTSTAMP:20231011T192041Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192041Z
UID:14223-1028264400-1028289600@www.cecs.uci.edu
SUMMARY:Design of a Hardware/Software RTOS for SoC
DESCRIPTION:by Vincent John Mooney III\, Gerogia Institute of TechnologyAugust 2\, 2002
URL:https://www.cecs.uci.edu/event/design-of-a-hardware-software-rtos-for-soc/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020802T040000
DTEND;TZID=America/Los_Angeles:20020802T120000
DTSTAMP:20231011T192054Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T192054Z
UID:14222-1028260800-1028289600@www.cecs.uci.edu
SUMMARY:Embedded Systems Research at IIT Delhi
DESCRIPTION:by M. Balahrishnan\, IIT Delhi\, IndiaAugust 2\, 2002
URL:https://www.cecs.uci.edu/event/embedded-systems-research-at-iit-delhi/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020724T060000
DTEND;TZID=America/Los_Angeles:20020724T120000
DTSTAMP:20231011T192654Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192654Z
UID:14224-1027490400-1027512000@www.cecs.uci.edu
SUMMARY:Polychrony for System Design
DESCRIPTION:by Dr. Jean-Pierre Talpin\, INRIA project ESPRESSO\, FranceJuly 24\, 2002
URL:https://www.cecs.uci.edu/event/polychrony-for-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020325T070000
DTEND;TZID=America/Los_Angeles:20020325T120000
DTSTAMP:20231011T192748Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192748Z
UID:14225-1017039600-1017057600@www.cecs.uci.edu
SUMMARY:Power Estimation and Optimization on Architectural Level
DESCRIPTION:by Achim Rettberg\, C-Lab\, Paderborn\, GermanyMarch 25\, 2002
URL:https://www.cecs.uci.edu/event/power-estimation-and-optimization-on-architectural-level/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020315T080000
DTEND;TZID=America/Los_Angeles:20020315T120000
DTSTAMP:20231011T192041Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192041Z
UID:14226-1016179200-1016193600@www.cecs.uci.edu
SUMMARY:Compiling with Code-Size Constraints
DESCRIPTION:by Jens Palsberg\, Purdue UniversityMarch 15\, 2002
URL:https://www.cecs.uci.edu/event/compiling-with-code-size-constraints/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020221T090000
DTEND;TZID=America/Los_Angeles:20020221T120000
DTSTAMP:20231011T192254Z
CREATED:20231011T180348Z
LAST-MODIFIED:20231011T192254Z
UID:14227-1014282000-1014292800@www.cecs.uci.edu
SUMMARY:Heterogeneous Actor-oriented Modeling in Ptolemy II
DESCRIPTION:by Steven Neuendorffer\, University of California\, BerkeleyFebruary 21\, 2002
URL:https://www.cecs.uci.edu/event/heterogeneous-actor-oriented-modeling-in-ptolemy-ii/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20011028T090000
DTEND;TZID=America/Los_Angeles:20011028T120000
DTSTAMP:20231011T180215Z
CREATED:20231011T180215Z
LAST-MODIFIED:20231011T180215Z
UID:14210-1004259600-1004270400@www.cecs.uci.edu
SUMMARY:SRC Awards
DESCRIPTION:The Semiconductor Research Corporation (SRC) recently named one CECS graduate student as an SRC Fellow and one CECS graduate student as an SRC Master’s Scholar. These awards will commence with the fall 2001 semester.\nGraduate student Frederic Doucet\, studying under Professor Rajesh K. Gupta\, was named an SRC Fellow in the SRC Graduate Fellowship Program. This fellowship award is for up to three years of study and provides tuition and fees\, a generous monthly stipend\, and an annual unrestricted gift of $2\,000 to the ICS department. \nGraduate student Shannon Tauro\, studying under Professor Nikil D. Dutt\, was named an SRC Master’s Scholar in the SRC Master’s Scholarship Program. This scholarship award is for up to two years of study and provides tuition and fees\, a generous monthly stipend\, and an annual unrestricted gift of $2\,000 to the ICS department. \nCECS is honored and privileged to have these two outstanding graduate students and congratulates Shannon and Frederic on receiving these prestigious SRC research awards.
URL:https://www.cecs.uci.edu/event/src-awards/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010831T050000
DTEND;TZID=America/Los_Angeles:20010831T120000
DTSTAMP:20231011T192054Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192054Z
UID:14213-999234000-999259200@www.cecs.uci.edu
SUMMARY:Evaluation of VLSI Architectures
DESCRIPTION:by Dr. Walter Stechele\, Director of Research\, Institute for Integrated Circuits\,Munich University of Technology\, Munich\, Germany\nAugust 31\, 2001
URL:https://www.cecs.uci.edu/event/evaluation-of-vlsi-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010808T040000
DTEND;TZID=America/Los_Angeles:20010808T120000
DTSTAMP:20231011T192457Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192457Z
UID:14214-997243200-997272000@www.cecs.uci.edu
SUMMARY:Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis
DESCRIPTION:by Prof. Jihong Kim\, School of Computer Science & Engineering\,Seoul National University\, Korea\nAugust 8\, 2001
URL:https://www.cecs.uci.edu/event/low-energy-intra-task-voltage-scheduling-using-static-timing-analysis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010808T030000
DTEND;TZID=America/Los_Angeles:20010808T120000
DTSTAMP:20231011T192053Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192053Z
UID:14215-997239600-997272000@www.cecs.uci.edu
SUMMARY:Embedded System Design and Energy Optimization
DESCRIPTION:by Prof. Naehyuck Chang\, School of Computer Science & Engineering\,Seoul National University\, Korea\nAugust 8\, 2001
URL:https://www.cecs.uci.edu/event/embedded-system-design-and-energy-optimization/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010802T020000
DTEND;TZID=America/Los_Angeles:20010802T120000
DTSTAMP:20231011T192054Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192054Z
UID:14216-996717600-996753600@www.cecs.uci.edu
SUMMARY:FLYSIG - A Fast Re-Configurable Asynchronous Architecture  for Multimedia Applications
DESCRIPTION:by Achim Rettberg\, Cooperative Computing & Communication Laboratory (C-LAB)\, Paderborn\, GermanyAugust 2\, 2001
URL:https://www.cecs.uci.edu/event/flysig-a-fast-re-configurable-asynchronous-architecture-for-multimedia-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR