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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090618T150000
DTEND;TZID=America/Los_Angeles:20090618T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14320-1245337200-1245340800@www.cecs.uci.edu
SUMMARY:Automatic Generation and Verification of Transaction Level Models
DESCRIPTION:Automatic Generation and Verification of Transaction Level Models\nby Lochi Yu \nLocation: ET 331 \nDate and Time: June 18\, 2009 10:00am \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nThe rising complexity in system designs over the past decades poses great challenges to current designers. One way to cope with this challenge has been to raise the level of abstraction of design\, reducing the number of elements and speeding up design decisions. Transaction Level Models (TLM) have emerged as a new alternative to design Multi-Processor System-on-Chips (MPSoC). TLMs express communication among modules at the transaction level\, without simulating the dozens of individual signals in communication elements such as busses. Nevertheless\, several drawbacks exist: TLMs are fast\, but their accuracy is low\, TLMs are being coded manually\, often by the use of a System Level Design Language (SLDL)\, there is no widely-adopted and tool-supported TLM style\, and there has been little work on verifi cation at the System Level. In this dissertation\, we aimed to contribute in different aspects: We defined a modeling style for SystemC TLMs whose modules have a one-to-one relationship with actual synthesized modules in a FPGA. Then\, we defined a data structure\, complete and flexible enough to describe a complete embedded system\, its hardware platform and application\, and developed generation algorithms that would use it to automatically produce an executable TLM in SystemC. Fourth\, we designed new transformation rules for models in Model Algebra (MA) that allows veri cation on pipelined models in MA. With our approach\, we can have automatic generation and verification of Transaction Level Models\, freeing the designer from error-prone manual coding\, and allows him to focus on higher level design decisions\, speeding up the overall design phase.
URL:https://www.cecs.uci.edu/event/automatic-generation-and-verification-of-transaction-level-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090603T150000
DTEND;TZID=America/Los_Angeles:20090603T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14321-1244041200-1244044800@www.cecs.uci.edu
SUMMARY:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors
DESCRIPTION:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors\nby Ashok Halambi \nLocation: DBH 4013 \nDate and Time: June 3\, 2009 2:00pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Alex Nicolau\nProfessor Alex Viedenbaum \nAbstract:\nEmbedded systems continue to increase in functionality\, complexity and connectivity. Programmable platforms\, consisting of processors programmable in software\, are a popular solution to satisfy the design constraints (such as cost\, performance\, flexibility\, reliability etc.) of such systems. Key challenges in the design of programmable platforms include compiler-in-loop design space exploration (DSE)\, and automatic generation of software toolkit for hardware/software co-design. \nA language-based model of the processor-memory subsystem has several benefits: it serves as a golden reference model for all principals involved in the design; it can be used to drive DSE and automatic software toolkit generation; it can be used to perform top-down (formal) verification and validation; and\, it can be refined down to implementation (register-transfer level). In this dissertation\, we present EXPRESSION\, an architecture description language (ADL) that is designed for DSE of processor-memory sub-system and automatic generation of software toolkit including compiler and cycle-accurate simulator. EXPRESSION has been used to describe various processors from RISC (DLX\, MIPS R4000\, ARM 9)\, VLIW (TI C6x)\, DSP (ST100)\, etc. Our EXPRESSION based DSE methodology permits exploration of a wide range of processor architectures\, and includes compiler-in-loop for accurate analysis of each design configuration. \nTo aid compiler-in-loop DSE\, we developed EXPRESS\, a retargetable\, instruction level parallelizing compiler that accepts programs in “C” and produces assembly code for the target processor described in EXPRESSION. The EXPRESS compiler is capable of handling irregular architectures\, and can adapt to changes in the processor’s instruction-set or micro-architecture. EXPRESS also includes a framework for dynamic customization of the compiler based on the target application and architecture characteristics. These capabilities of EXPRESS make it ideal for use in the DSE of processor-memory subsystems. \nRetargetable compilers suffer from the drawback of poor output code quality as compared to a compiler that is “hand-crafted” for the target processor. Key differences between the two compilers include the presence of target specific optimizations and custom phase ordering of optimization passes in the target specific compiler. In this dissertation\, we propose a framework\, called TransMutations\, that enables dynamic\, run-time customization of a retargetable compiler. It allows for easy integration of optimizations (called mutations) into the compiler and solves the phase ordering problem by applying optimizations in a context-sensitive manner for each region of the application code. The TransMutations framework has been implemented in the EXPRESS compiler and we present results demonstrating the effectiveness of the technique. This framework improves the quality of code generated by retargetable compilers and enables them to be used in accurate compiler-in-loop DSE of programmable embedded systems.
URL:https://www.cecs.uci.edu/event/transmutations-a-framework-for-dynamic-customization-of-retargetable-compilers-for-embedded-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090529T150000
DTEND;TZID=America/Los_Angeles:20090529T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14322-1243609200-1243612800@www.cecs.uci.edu
SUMMARY:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement
DESCRIPTION:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement\nby Aseem Gupta \nLocation: DBH 3011 \nDate and Time: May 29\, 2009 1:30pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Fadi Kurdahi\nProfessor Tony Givargis \nAbstract:\nProcess scaling and shrinking device geometries have resulted in chips with greater performance and complexity levels. However\, these advancements have come at the cost of higher power densities and increased operating temperatures. The inability to control the operating temperatures by existing cooling techniques is the principal reason for discontinuation of an increase in frequencies and introduction of multi-core architectures. Apart from operability\, high temperatures have unfavorable consequences such as: increased leakage power\, reduced interconnect life time\, slowing of interconnects and transistors\, need for expensive package and cooling mechanisms\, and increased manufacturing cost and design effort. Traditionally\, thermal issues have been examined only at the post-synthesis stages of the design flow. This thesis attempts to migrate the “thermal awareness” from the physical level design phase to early stages of the VLSI design flow and utilize it to target various design metrics such as power\, performance\, reliability\, and operability. This thesis advances the procedure of leakage power estimation by coupling it with thermal profile estimation and capturing the positive interdependence between temperature and leakage power. It also advances the traditional role of communication architecture to that of an active thermal manager. The proposed communication architecture based thermal manager delays the execution of chosen components by regulating the flow of data over the on-chip communication fabric. This dissertation demonstrates the need of examining the effects of frequency\, supply voltage\, power dissipation\, and temperature on SRAM reliability in a mutually interrelated manner. Our observation contradicts the conventional belief that increasing supply voltage always reduces the failure rate in SRAMs. Because of thermal effects\, an increase in the supply voltage can also lead to increase in the SRAM failure rate. This thesis also extends the procedure of system level floorplanning to manage the leakage power and reliability of the design. The fundamental contribution of this thesis is that it advances the traditional design flow in the direction of incorporating thermal awareness during various stages of the flow.
URL:https://www.cecs.uci.edu/event/temperature-aware-vlsi-design-for-reduced-power-and-reliability-enhancement/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090527T150000
DTEND;TZID=America/Los_Angeles:20090527T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14323-1243436400-1243440000@www.cecs.uci.edu
SUMMARY:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems
DESCRIPTION:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems\nby Gabor Madl \nLocation: DBH 3011 \nDate and Time: May 27\, 2009 10:00am \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Tony Givargis\nProfessor Ian Harris \nAbstract:\nAs embedded systems become increasingly networked\, and interact with the physical world\, Distributed Real-time Embedded (DRE) systems emerge. DRE systems range from small-scale Multi-processor Systems-on-Chip (MPSoCs) operating in resource constrained environments such as cell phone platforms\, medical devices and sensor networks all the way to large-scale software-intensive systems of systems used in avionics\, ship computing environments\, and in supervisory control and data acquisition systems managing regional power grids. \nThis dissertation focuses on the model-based analysis of event-driven DRE systems. Event-driven DRE systems are based on a reactive communication paradigm\, where the execution of tasks is triggered asynchronously\, invoked by external events\, interrupts\, or by other tasks. Events can also express time\, providing a common semantic domain for the compositional analysis of time- and event-driven DRE systems. \nThe key technical contributions of this dissertation are (1) the specification of a formal semantic domain for DRE systems\, (2) a model checking method for the real-time verification of non-preemptive DRE systems using timed automata\, (3) a performance estimation method for DRE systems by discrete event simulations\, (4) a conservative approximation method for the verification of preemptive event-driven asynchronous DRE systems by timed automata\, (5) a method for the functional verification and performance estimation of MPSoCs built on an industry standard interconnect\, and (6) a cross-abstraction real-time analysis method for MPSoC designs utilizing bus matrix interconnects. \nThe novelty of our approach lies in combining formal methods and symbolic simulations for the system-level evaluation of DRE designs early in the design flow\, and utilizing multiple abstractions to trade off analysis accuracy in scalability. \nWe implemented the proposed analysis methods in the open-source Distributed Real-time Embedded Analysis Method (DREAM) framework for the model-based real-time verification and performance estimation of DRE systems. DREAM focuses on the practical application of formal analysis methods to automate the verification\, development\, configuration\, and integration of event-driven DRE systems. DREAM is available for download at http://dre.sourceforge.net. We applied the proposed design flow to the domain of software-intensive mission-critical avionics DRE applications\, and the domain of multimedia MPSoCs.
URL:https://www.cecs.uci.edu/event/model-based-analysis-of-event-driven-distributed-real-time-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090504T150000
DTEND;TZID=America/Los_Angeles:20090504T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14251-1241449200-1241452800@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n  \n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 4\, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm (Lecture Cancelled)\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090309T150000
DTEND;TZID=America/Los_Angeles:20090309T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T181037Z
LAST-MODIFIED:20231011T192457Z
UID:14252-1236610800-1236614400@www.cecs.uci.edu
SUMMARY:Nonlinear Symbolic Program Analysis for Increased Parallelization
DESCRIPTION:Nonlinear Symbolic Program Analysis for Increased Parallelization\n\n\n\n\nSpeaker\n\n\nProfessor Kleanthis Psarris \nDepartment of Computer Science\nThe University of Texas at San Antonio\, TX\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Nicolau\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 9\, 2009\nRefreshments at 2:30 pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHigh end parallel and multi-core processors rely on compilers to perform the necessary optimizations and exploit concurrency in order to achieve higher performance. However\, source code for high performance computers is extremely complex to analyze and optimize. In particular\, program analysis techniques often do not take into account complex expressions during the data dependence analysis phase. Most data dependence tests are only able to analyze linear expressions\, even though non-linear expressions occur very often in practice. Therefore\, considerable amounts of potential parallelism remain unexploited. In this talk we propose new data dependence analysis techniques to handle such complex instances of the dependence problem and increase program parallelization. Our method is based on a set of polynomial time techniques that can prove or disprove dependences in source codes with non-linear and symbolic expressions\, complex loop bounds\, arrays with coupled subscripts\, and if-statement constraints. In addition our algorithm can produce accurate and complete direction vector information\, enabling the compiler to apply further transformations. To validate our method we performed an experimental evaluation and comparison against the I-Test\, the Omega test and the Range test in the Perfect and SPEC benchmarks. The experimental results indicate that our dependence analysis tool is accurate\, efficient and more effective in program parallelization than the other dependence tests. The improved parallelization results into higher speedups and better program execution performance in several benchmarks.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nKleanthis Psarris is Professor and Chair of the Department of Computer Science at the University of Texas at San Antonio. His research interests are in the areas of Parallel and Distributed Systems\, Compilers and Programming Languages. He received his B.S. degree in Mathematics from the National University of Athens\, Greece in 1984. He received his M.S. degree in Computer Science in 1987\, his M.Eng. degree in Electrical Engineering in 1989 and his Ph.D. degree in Computer Science in 1991\, all from Stevens Institute of Technology in Hoboken\, New Jersey. He has published extensively in top journals and conferences in the field and his research has been funded by the National Science Foundation and Department of Defense agencies. He is an Editor of the Parallel Computing journal. He has served on the Program Committees of several international conferences including the ACM International Conference on Supercomputing (ICS) in 1995\, 2000\, 2006 and 2008\, the IEEE International Conference on High Performance Computing and Communications (HPCC) in 2008 and 2009\, and the ACM Symposium on Applied Computing (SAC) in 2003\, 2004\, 2005 and 2006.
URL:https://www.cecs.uci.edu/event/nonlinear-symbolic-program-analysis-for-increased-parallelization/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090227T150000
DTEND;TZID=America/Los_Angeles:20090227T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14324-1235746800-1235750400@www.cecs.uci.edu
SUMMARY:Automatic Design and Optimization of Application Specific Processors
DESCRIPTION:Automatic Design and Optimization of Application Specific Processors\nby Jelena Trajkovic \nThe stringent performance and power requirements of modern applications have fueled the need for application specific computing platforms. Conventional general purpose embedded processor do not provide the necessary throughput for meeting the applications’ performance and power needs. On the other hand\, manual hardware design is too expensive and results in inflexible implementation. The short time to market demands also make hardware design prohibitive. Therefore\, there exists a need for automatic design methods and tools that provide a high performance\, programmable and energy-efficient implementation starting from standard application descriptions such as C reference code. High level synthesis and application specific processor tools are a step in this direction\, but suffer from scalability\, quality and controllability issues. In this dissertation\, we present techniques for automatic processor design from C code that are scalable to thousands of lines of C code\, are controllable at each step of the design process and provide quality of results comparable to manual design. \nOur contributions enable a system level design methodology for application specific processors that starts with a reference C code of the application. An initial processor data path is constructed from a database of available components such as function units\, register files and buses. The initial data path is based on the types of operations and available concurrency in the application. The data path is then iteratively refined until an efficient architecture is derived. The key optimization goal is to keep performance within given boundaries while maximizing resource utilization. We further optimize the processor design using a novel algorithm for automatic custom pipelining based on the C code. The pipelining optimization also targets both resource utilization and performance. Our experimental results with large applications such as DCT and MP3 decoder show that automatically generated architectures are comparable to manual designs\, but can be obtained in a matter of few seconds\, leading to significant productivity gains. \nOur final contribution to design methods for embedded systems deals with low power memory design. Typically\, DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high\, exceeding that of the data cache or even that of the processor. We present and evaluate a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small\, cache-like structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption\, 23%\, on average\, and reduction in the energy-delay product\, 44%\, on average. The approach also improves performance: the CPI is reduced by 26%\, on average.
URL:https://www.cecs.uci.edu/event/automatic-design-and-optimization-of-application-specific-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081119T150000
DTEND;TZID=America/Los_Angeles:20081119T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14282-1227106800-1227110400@www.cecs.uci.edu
SUMMARY:My Work and My Life
DESCRIPTION:by Prof. Leonard KleinrockDepartment of Computer Science\nUniversity of California\, Los Angeles\nMcDonnell Douglas Auditorium\nDistinguished Lecture\, November 19\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/my-work-and-my-life/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081104T150000
DTEND;TZID=America/Los_Angeles:20081104T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192254Z
UID:14243-1225810800-1225814400@www.cecs.uci.edu
SUMMARY:Geppeto*: Consumer’s Approach to Programming
DESCRIPTION:Prof. Sinisa Srbljic\, School of Electrical Engineering and Computing\, University of Zagreb\, CroatiaNovember 4\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/geppeto-consumers-approach-to-programming/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080709T150000
DTEND;TZID=America/Los_Angeles:20080709T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14325-1215615600-1215619200@www.cecs.uci.edu
SUMMARY:Improving Packet Latencies of Live Streams in Wired Networks
DESCRIPTION:Improving Packet Latencies of Live Streams in Wired Networks\nby Arijit Ghosh (Advisor: Prof. Tony Givargis)\nDate: July 9\, 2008 \nLive streaming is becoming increasingly popular. In a study published in January 2008\, Cisco predicted that Internet-to-TV video will account for 30% of all Internet traffic. If all kinds of video traffic are considered\, then it will be 90% of consumer traffic by 2012. We distinguish live streams from on demand streams. Live streams are sent as the data is being generated\, is typically of long duration\, requires high bandwidth and associated with flash crowd behavior. As such\, live streams place tremendous demand on network resources. \nIn this thesis\, we proposed network techniques to improve packet latencies of live streams in wired networks. In particular\, we made the following contributions. First\, we proposed a technique that allows multicasting at the access network\, the proverbial last mile which presents tremendous bandwidth limitations. Second\, we reduced nodal processing by a tunelling scheme based on source routing. Essentially\, using routing computed at source and a novel network encoding scheme\, we eliminated intermediate processing. Third\, we presented a queueing algorithm that schedules packets based on application deadlines\, reduces the number of sorting iterations\, thereby improving performance\, has low complexity\, exhibits good fairness and provides a bounded delay for a single packet that is independent of the number of flows. Finally\, we proposed a variation of QoS routing that works with only partial network state information.
URL:https://www.cecs.uci.edu/event/improving-packet-latencies-of-live-streams-in-wired-networks/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080708T150000
DTEND;TZID=America/Los_Angeles:20080708T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14326-1215529200-1215532800@www.cecs.uci.edu
SUMMARY:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems
DESCRIPTION:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems\nby Minyoung Kim (Advisor: Prof. Nikil Dutt)\nDate: July 8\, 2008 \nResource limited mobile real-time embedded systems can benefit greatly from  dynamic adaptation of system parameters. This thesis proposes a novel framework  xTune that employs iterative tuning using light-weight formal verification at runtime with feedback for dynamic adaptation. One objective of this approach is to enable tradeoff analysis across multiple layers (for example\, application\, middleware\, operating system) and predict the possible property violations as the system evolves dynamically over time. Specifically\, an executable formal specification is developed for each layer of the mobile real-time system under consideration. The formal specification is then analyzed using statistical model checking and statistical quantitative analysis\, to determine the impact of various resource management policies for achieving desired a variety of end-to-end properties in a quantifiable manner. The integration of formal analysis with dynamic behavior from system execution results in a feedback loop that enables model refinement and further optimization of policies and parameters. Finally\, we propose a composition method for coordinated interaction of optimizers at different layers. The core idea of our approach is that each participating optimizer can restrict its own parameters and exchange refined parameters with its associated layers. We demonstrate the applicability of the proposed methodology to the adaptive provisioning of mobile real-time embedded systems by treating a multimedia case study on resource-limited devices.
URL:https://www.cecs.uci.edu/event/xtune-a-formal-methodology-for-cross-layer-tuning-of-mobile-real-time-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080616T150000
DTEND;TZID=America/Los_Angeles:20080616T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14327-1213628400-1213632000@www.cecs.uci.edu
SUMMARY:A Runtime System for Memory-Constrained Distributed Embedded Systems
DESCRIPTION:A Runtime System for Memory-Constrained Distributed Embedded Systems\nby Jiwon Hahn (Advisor: Prof. Pai Chou)\nDate: June 16\, 2008 \nWearable and embedded wireless sensor platforms are often highly constrained in size and power consumption in order to operate in unintrusive ways. To meet these constraints\, the memory is kept as small as possible to reduce area and power\, but at the same time it poses new challenges on programming. To address these problems\, this dissertation proposes \n(1) a framework for synthesis of host-assisted scripting engines\, \n(2) a minimum-overhead yet powerful runtime system based on recursive threaded code\, and \n(3) a host-assisted memory optimization technique that exploits high-level knowledge in models of computation. The benefits are three-fold: first\, the interactive access between programmer and embedded system improve productivity of programmers. Second\, the low runtime overhead and memory requirements enable this runtime system to run on compact platforms while providing high flexibility and composability. Third\, a new memory optimization scheme combined with the dispatching structure expose regularity of dataflow models to enable memory and scheduling optimizations\, sometimes in ways better than manual coding. \nExperimental results show that systems developed using these techniques have unleashed the power of these resource-constrained distributed embedded systems. As memory is currently the limiting factor\, the lightweight runtime system and systematic memory optimization technique presented in this dissertation are enabling technology for a new class of real-world\, ultra-compact distributed embedded systems.
URL:https://www.cecs.uci.edu/event/a-runtime-system-for-memory-constrained-distributed-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14375-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:CECS DAC Open House
DESCRIPTION:The 45th Design Automation Conference (DAC) is being held in Anaheim\, CA on June 8-13\, 2008. CECS cordially invites DAC attendees to an Open House on Friday afternoon\, June 13\, 2008 from 2:00PM to 4:00PM in our CECS office on the 2rd floor of the Anteater Instruction & Research Building (AIRB). We are planning a buffet of sandwiches\, cookies\, and soft drinks for a relaxed atmosphere. Many of our research affiliates and graduate students will be available to informally discuss new directions in technology and research.\nFor those attending DAC\, kindly consider attending this open house to see first hand our research programs and visit with our professors and graduate students. We are planning an informal environment and hope you will attend and enjoy the CECS hospitality.\nView Flyer with Directions
URL:https://www.cecs.uci.edu/event/cecs-dac-open-house/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14244-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models
DESCRIPTION:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models\n\n\n\n\nSpeaker\n\n\nDr. Christian Haubelt\nUniversity of Erlangen-Nuremberg\, Germany\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Tower\, Room 331\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 13 \, 2008\nTalk begins 11:00am\nRefreshments at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n80% of all design decisions are made in the first 20% of the design time. Thus\, a substantiated knowledge about possible solutions is mandatory in early design phases in order to design high quality products. SystemCoDesigner is a software tool for automatic design space exploration at the electronic system level and for platform-based prototyping of hardware/software systems. By exploring the design space\, a designer becomes more confident in decisions to be done. Starting from a behavioral SystemC description different solutions are generated automatically by using software synthesis techniques and Forte Design Systems’ Cynthesizer for behavioral hardware synthesis. In order to allow such a degree of automation\, SystemCoDesigner requires the behavioral SystemC model to be representable in a well-defined Model of Computation\, called FunState. As a case study\, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput\, ranging from software only solutions up to pure hardware implementations which reach real-time performance for QCIF streams on a 50MHz FPGA. In this talk\, the SystemCoDesigner overall design flow\, the FunState Model of Computation\, and some automatic transformation are presented using the Motion-JPEG case study.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nChristian Haubelt received his diploma degree in Electrical Engineering from the University of Paderborn\, Germany\, in 2001. He received his Ph.D. in Computer Science from the University of Erlangen-Nuremberg\, Germany\, in 2005. Since 2004\, he is head of the System-Level Design Automation Group at the Chair of Hardware/Software Co-Design\, University of Erlangen-Nuremberg\, Germany. Dr. Haubelt’s research interests include electronic system level design\, system level design automation\, and multi-objective optimization.\n\n\n\n\n\n\n\n\n\n\nWeb Site\n\n\nhttp://www12.informatik.uni-erlangen.de/people/haubelt/
URL:https://www.cecs.uci.edu/event/systemcodesigner-automatic-design-space-exploration-and-rapid-prototyping-from-behavioral-models/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080604T150000
DTEND;TZID=America/Los_Angeles:20080604T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14328-1212591600-1212595200@www.cecs.uci.edu
SUMMARY:Source Re-coding to Create Parallel and Flexible MPSoC Models for Embedded System Design and Exploration
DESCRIPTION:by Pramod Chandraiah\, University of California\, Irvine\nJune 4\, 2008\nview details
URL:https://www.cecs.uci.edu/event/source-re-coding-to-create-parallel-and-flexible-mpsoc-models-for-embedded-system-design-and-exploration/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080512T150000
DTEND;TZID=America/Los_Angeles:20080512T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14329-1210604400-1210608000@www.cecs.uci.edu
SUMMARY:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip
DESCRIPTION:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip\nby Sudeep Pasricha (advisor: Prof. Nikil Dutt)\nDate: May 12\, 2008 \nWith the increasing performance demands of emerging convergence applications and advances in process technology\, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance\, power\, cost and reliability. Consequently\, the design\, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today. \nIn this dissertation\, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis\, comprehensively and automatically generating both the topology and protocol parameters\, while trading off multiple design constraints such as power\, performance\, area and cost.Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality\, better complexity management\, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs.
URL:https://www.cecs.uci.edu/event/commsyn-on-chip-communication-architecture-synthesis-for-multi-processor-systems-on-chip/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080510T150000
DTEND;TZID=America/Los_Angeles:20080510T160000
DTSTAMP:20231205T135317Z
CREATED:20231011T185235Z
LAST-MODIFIED:20231205T135317Z
UID:14359-1210431600-1210435200@www.cecs.uci.edu
SUMMARY:NISC: No-Instruction-Set-Computer
DESCRIPTION:Release Date: May 2008 (NISC Toolset 2008.05)NISC Demo: https://www.cecs.uci.edu/~nisc/  \nNo-Instruction-Set-Computer (NISC) Technology is the next generation of tools for Design Synthesis.\nWith NISC Technology\, you can simultaneously gain higher productivity and better quality of results. Other techniques only offer one of these benefits. \nTwo popular approaches for designing digital systems: \n\nLow-level design at Register Transfer Level (RTL).\n\nCan lead to efficient IPs but the development time and cost is very high.\nHigh-Level-Synthesis (HLS) goal: improve productivity\n\nAutomatically converts high-level description of the IP (e.g. written in C language) to RTL\nDesigner has little control over the quality of the generated RTL in terms of clock frequency\, area\, manufacturability\, power\, etc\n\nResult quality typically bad.\n\n\n\n\n\n\nHigh-level design using general-purpose or custom processors.\n\nDevelopment time and cost is much lower\, but the efficiency and implementation quality is also much lower.\nApplication-Specific-Instruction-Processors (ASIP) goal: improve quality\n\nAdds application-specific instructions to the processor\n\nFinding suitable custom instructions and adding them to the toolset (compiler\, simulator\, etc.) is a very challenging task.\nBecause of their instruction-set\, processors (including ASIPs) impose a minimum overhead in terms of area\, power\, and performance.\n\n\nThe processor-based implementation may become more appealing only when the IP design complexity is above a certain level (relatively very high).\n\nNot suitable if you want to run a few algorithms or design a hardware block\n\n\n\n\n\n\n\nReferences:\nD. Gajski\, “NISC: The Ultimate Reconfigurable Component\,” TR 03-28\, October 1\, 2003.\ndownload pdf
URL:https://www.cecs.uci.edu/event/nisc-no-instruction-set-computer/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080429T150000
DTEND;TZID=America/Los_Angeles:20080429T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14283-1209481200-1209484800@www.cecs.uci.edu
SUMMARY:Hardware-Accelerated Formal Verification
DESCRIPTION:by Prof. Masahiro FujitaVLSI Design and Education Center\nUniversity of Tokyo\, Tokyo\, Japan\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, April 29\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/hardware-accelerated-formal-verification/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080328T150000
DTEND;TZID=America/Los_Angeles:20080328T160000
DTSTAMP:20231205T135316Z
CREATED:20231011T185234Z
LAST-MODIFIED:20231205T135316Z
UID:14358-1206716400-1206720000@www.cecs.uci.edu
SUMMARY:ESE: Embedded System Environment
DESCRIPTION:Release Date: March 28\, 2008Web Site: https://www.cecs.uci.edu/~ese/ \nESE is a toolset for modeling\, synthesis and validation of multi-processor embedded system designs. It builds on over 15 years of research in system level design at CECS under Prof. Daniel Gajski. It consists of two parts: ESE Front End and ESE Back End. \nESE Front End provides automatic generation of SystemC transaction level models (TLMs) from graphical capture of system platform and application C/C++ code. ESE generated TLMs can be used either as virtual platforms for SW development or for fast and early timing estimation of system performance. The retargetable performance estimation utilizes the LLVM infrastructure. \nESE Back End provides automatic synthesis from TLM to Pin-Cycle Accurate Model (PCAM) consisting of RTL interfaces\, system SW and prototype ready FPGA project files. ESE generated RTL can be synthesized using standard logic synthesis tools and system SW can be compiled along with application code for a given processor. ESE automatically creates Xilinx EDK projects for download to Xilinx boards. \nThe key advantages of ESE are huge productivity gain (provided by model automation and higher design abstraction) and ease of use for non-experts (provided by C-based and graphical design input). To learn more about ESE or to download ESE Front End\, please visit the ESE Web Site. \nReference:\nD. Gajski\, A. Gerstlauer\, and S. Abdi\, “Embedded System Design: Concepts and Tools\,” ASP-DAC 2007 Pacifico Yokohama\, Yokohama\, Japan\, January 23\, 2007.\ndownload pdf
URL:https://www.cecs.uci.edu/event/ese-embedded-system-environment/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080324T150000
DTEND;TZID=America/Los_Angeles:20080324T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14284-1206370800-1206374400@www.cecs.uci.edu
SUMMARY:On Numerical Modeling of Large Strain Elastoplastic Structural Responses
DESCRIPTION:By Jurica Sori?Institute of Applied Mechanics\nFaculty of Mechanical Engineering and Naval Architecture\, University of Zagreb\, Croatia\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, Mar 24\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/on-numerical-modeling-of-large-strain-elastoplastic-structural-responses/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080306T150000
DTEND;TZID=America/Los_Angeles:20080306T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14245-1204815600-1204819200@www.cecs.uci.edu
SUMMARY:Tiptoe: A Compositional Real-Time Operating System
DESCRIPTION:Prof. Christoph Kirsch\, Dept. of Computer Sciences\, University of SalzburgDonald Bren Hall (DBH) 3011\, University of California\, Irvine\nMarch 06\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/tiptoe-a-compositional-real-time-operating-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080303T150000
DTEND;TZID=America/Los_Angeles:20080303T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14330-1204556400-1204560000@www.cecs.uci.edu
SUMMARY:Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design
DESCRIPTION:by Gunar Schirner\, University of California\, Irvine\nMarch 3\, 2008\nview details
URL:https://www.cecs.uci.edu/event/analysis-and-optimization-of-transaction-level-models-for-multi-processor-system-on-chip-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080110T150000
DTEND;TZID=America/Los_Angeles:20080110T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14285-1199977200-1199980800@www.cecs.uci.edu
SUMMARY:Opportunities for Power and Performance Optimization in Digital Feedback-Controllers
DESCRIPTION:By Prof. Forrest Brewer\, Deptment of Electrical & Computer EngineeringUniversity of California\, Santa Barbara\nEngineering Gateway\, Room 3161\, University of California\, Irvine\nLecture\, Jan 10\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/opportunities-for-power-and-performance-optimization-in-digital-feedback-controllers/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071229T150000
DTEND;TZID=America/Los_Angeles:20071229T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14286-1198940400-1198944000@www.cecs.uci.edu
SUMMARY:Passive Supply Voltage And Frequencey Scaling (PVS)
DESCRIPTION:By Prof. Naehyuck Chang\, EECS Department\, Seoul National UniversityBren Hall Room. 3011\, Unversity of California\, Irvine\nLecture\, Dec 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/passive-supply-voltage-and-frequencey-scaling-pvs/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071206T150000
DTEND;TZID=America/Los_Angeles:20071206T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14331-1196953200-1196956800@www.cecs.uci.edu
SUMMARY:Synthesis and Optimization of Low-Power Custom NISC Processors
DESCRIPTION:by Bita Gorjiara\, University of California\, Irvine\nDecember 6\, 2007\nview details
URL:https://www.cecs.uci.edu/event/synthesis-and-optimization-of-low-power-custom-nisc-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071026T150000
DTEND;TZID=America/Los_Angeles:20071026T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14376-1193410800-1193414400@www.cecs.uci.edu
SUMMARY:CECS Faculty-Students Gathering 2007
DESCRIPTION:Faculty and students mingle at the 2007 CECS Student-Faculty Gathering\, held in our new office at 2010 Anteater Instruction Research Building (AIRB). We would like to welcome all the new faces and welcome back returning faculty and students.\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/cecs-faculty-students-gathering-2007/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071003T000000
DTEND;TZID=America/Los_Angeles:20071003T000000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14195-1191369600-1191369600@www.cecs.uci.edu
SUMMARY:Gabor Madl wins prestigious ACM Award
DESCRIPTION:Gabor Madl\, a CECS graduate student pursuing a PhD in Computer Science\, received the 2008 ACM SIGBED/SIGSOFT Frank Anger Memorial Award at the 2007 Embedded Systems Week Conference held in Salzburg\, Austria. This award recognizes one student researcher from each of the professional societies (ACM SIGBED and ACM SIGSOFT)\, promoting the crossover of ideas between the embedded software and software engineering research communities. Gabor’s research focuses on applying formal methods to enable analysis and evaluation of embedded computer systems\, and is a member of Professor Nikil Dutt’s research group.\nA photograph of Gabor receiving his award can be viewed at: http://cs.uni-salzburg.at/ 
URL:https://www.cecs.uci.edu/event/gabor-madl-wins-prestigious-acm-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070920T150000
DTEND;TZID=America/Los_Angeles:20070920T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14332-1190300400-1190304000@www.cecs.uci.edu
SUMMARY:Software Architecture for High Data Rate Wireless Body Sensor Applications
DESCRIPTION:Software Architecture for High Data Rate Wireless Body Sensor Applications\nby Seung-Mok Yoo \nFor wireless body area sensor networks\, the wearable nodes are highly constrained by low power\, low cost\, and small size while deliverly high throughput and low latency in a multiple access environment. To accomplish these goals\, the hardware must be kept simple\, and as a result\, the traditional abstractions with separate layers of the protocol stack and application must be merged and made as streamlined as possible. This dissertation identifies and removes two bottlenecks with data transfers: one is between the base station and its sensor nodes\, and the other is within the sensor node. \nFirst\, we propose a thin-server\, fat-client architecture. It supports a pulling protocol that achieves intra-network collision-free multiple access as in TDMA but without the time synchronization overhead. It also achieves high data throughput of air bandwidth and adaptivity of CSMA protocols but without collision or complexity on the node side. \nSecond\, for intra-node transfers\, another known bottleneck is the system bus. We identify the double-transaction problem\, which is common to SPI\, DMA\, and other interfaces. We propose the Master-Handoff Protocol to eliminate the redundant transaction and improve latency significantly\, and it is compatible with existing controllers. It not only halves the data transfer time but also achieves energy reduction. Together\, these techniques enable highly constrained hardware to meet strict size and power constraints for high wearability without sacrificing performance.
URL:https://www.cecs.uci.edu/event/software-architecture-for-high-data-rate-wireless-body-sensor-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070918T150000
DTEND;TZID=America/Los_Angeles:20070918T160000
DTSTAMP:20231011T184245Z
CREATED:20231011T184245Z
LAST-MODIFIED:20231011T184245Z
UID:14333-1190127600-1190131200@www.cecs.uci.edu
SUMMARY:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract
DESCRIPTION:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract\nby Mehrdad Reshadi \nToday\, depending on the size and complexity of a program\, there are two options for synthesizing a program to hardware: (1) using High Level Synthesis (HLS)\, and (2) using Application-Specific-Instruction-Processor (ASIP). \nTraditional HLS techniques can only support relatively small applications and do not give enough control to the designer over the quality of results. Poor quality of results and limited application domain has prevented the HLS from wide spread usage. \nEmbedded processors often run only one or a few applications in the life-time of the system. Therefore\, they can be customized for the target applications and significantly improve the quality of the embedded system in terms of cost\, performance\, power consumption\, etc. This is the goal in ASIP approaches. Instruction-based architectures limit the customizations because: (a) hardware designer is limited by instruction coding\, size and complexity of the decoder; (b) compilers can support certain class of instructions and hence instructions cannot be very complex; and (c) manually updating compilers to incorporate the custom instructions is not practical and developing compilers that automatically utilize hardware customizations through new custom instructions is very complex. \nIn this talk I present a new design approach called NISC (No-Instruction-Set-Computer) Technology. In NISC\, the datapath and controller are generated in two different phases. First the datapath is generated or selected from a database based on the application behavior. At the core of NISC technology\, there is a cycle-accurate compiler that maps a given application directly on a given datapath and generates the control words (CWs) that control the datapath resources in every clock cycle. The NISC architecture style is similar to the old nanocode machines. However\, instead of using nanocodes inside the process for implementing the microcodes and in turn instructions\, in NISC the nanocode (CWs) are directly used to program the datapath. \nNISC simplifies customization and allows designer to fully control design quality. NISC simplifies ASIP (Application-Specific-Instruction-Processor) approach by removing the complex task of finding and designing “most profitable” custom instructions. In NISC only the datapath needs to be specified and NISC compiler generates code “as if” each basic block of the program is executed with one custom instruction. On the other hand\, NISC improves resource constrained HLS techniques by adding the connectivity constraints\, on top of the traditional resource constraints\, into synthesis process. This enables the designer to control every thing in datapath including wires\, which are becoming increasingly more critical in newer technologies. In fact NISC combines the ASIP and HLS techniques. \nTo realize the NISC Technology design flow\, several challenging categories of problems must be solved. Mainly we need: \n1. Techniques for efficiently designing and customizing a datapath for an application\n2. Techniques for efficiently compiling any application on any given datapath\n3. Techniques for efficiently synthesizing a controller from the output of compiler and then generating synthesizable code for different target implementations. \nIn my thesis\, I focus on the compilation problems to enable practical use of NISC IPs in a system. A working compiler and other NISC tools are available for public use from NISC websitehttps://www.cecs.uci.edu/~nisc/. An online version of the tools can be also directly accessed at this website.
URL:https://www.cecs.uci.edu/event/no-instruction-set-computer-nisc-modeling-and-compilation-abstract/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070615T150000
DTEND;TZID=America/Los_Angeles:20070615T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192949Z
UID:14236-1181919600-1181923200@www.cecs.uci.edu
SUMMARY:The ADRES & DRESC dynamically reconfigurable architecture and ANSI C compiler
DESCRIPTION:Dr. Bjorn De Sutter\, IMEC Research Labs\, Belgium Calit2 Room 3008\, University of California\, Irvine\nJune 15\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/the-adres-dresc-dynamically-reconfigurable-architecture-and-ansi-c-compiler/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR