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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070615T150000
DTEND;TZID=America/Los_Angeles:20070615T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192949Z
UID:14236-1181919600-1181923200@www.cecs.uci.edu
SUMMARY:The ADRES & DRESC dynamically reconfigurable architecture and ANSI C compiler
DESCRIPTION:Dr. Bjorn De Sutter\, IMEC Research Labs\, Belgium Calit2 Room 3008\, University of California\, Irvine\nJune 15\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/the-adres-dresc-dynamically-reconfigurable-architecture-and-ansi-c-compiler/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070608T150000
DTEND;TZID=America/Los_Angeles:20070608T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192031Z
UID:14237-1181314800-1181318400@www.cecs.uci.edu
SUMMARY:A Methodology for Creating Application Specific Processor Architectures
DESCRIPTION:Prof. Anshul Kumar\, Indian Institute of Technology\, Delhi Calit2 Room 3008\, University of Califonria\, Irvine\nJune 08\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/a-methodology-for-creating-application-specific-processor-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070601T230000
DTEND;TZID=America/Los_Angeles:20070601T230000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14196-1180738800-1180738800@www.cecs.uci.edu
SUMMARY:Jelena and Gajski Receive IESS Best Paper Award
DESCRIPTION:Jelena Trajkovic\, a PhD candidate in computer science\, and Professor Daniel D Gajski\, received best paper award at the second International Embedded System Symposium that took place in Irvine\, California from May 30th to June 1st 2007. Their paper is titled “Automatic Data Path Generation from C Code for Custom Processors.” The paper was selected from over 60 submissions on the basis of technical quality and presentation. The authors of the best paper received an Altera Nios II Embedded Development Kit.\nAutomatic generation of architectures from C code is a fundamentally novel way of addressing the problem of system design. In traditional design methods\, architecture is assumed as fixed for implementing an application. Compilers must then figure out the best mapping of the application on the given architecture. This method may result in poor performance because the given architecture may not carry the best features to execute the application code. Moreover\, the architecture may carry features that are never used by the application\, resulting in wasted power and area. Architecture generation from C code attempts to solve this problem by automatically creating an architecture that “matches” the C code. \nIn their paper\, Jelena and Prof. Gajski present first results for the generation of matching architecture from C code. They address the selection of function units to meet performance goals while maximizing architecture utilization. Their experimental results demonstrate that the architecture could be generated for large C code\, including an MP3 decoder with over 14K lines of code\, under an hour. The optimizations improved architecture utilization by 30 to 60 percent while meeting performance constraints. \nCECS congratulates the researchers on their achievement and wishes them success in their future endeavors.
URL:https://www.cecs.uci.edu/event/jelena-and-gajski-receive-iess-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T192031Z
UID:14239-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Adaptive Mechanisms for Meeting Energy and Real-Time Constraints in MPSoC Platforms
DESCRIPTION:Prof. Flavio R. Wagner\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/adaptive-mechanisms-for-meeting-energy-and-real-time-constraints-in-mpsoc-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T193148Z
UID:14238-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Transparent Acceleration of Data Dependent Instructions for General Purpose Processors
DESCRIPTION:Prof. Luigi Carro\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract 
URL:https://www.cecs.uci.edu/event/transparent-acceleration-of-data-dependent-instructions-for-general-purpose-processors/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070528T210000
DTEND;TZID=America/Los_Angeles:20070528T210000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14198-1180386000-1180386000@www.cecs.uci.edu
SUMMARY:Payam Heydari Wins Guillemin-Cauer
DESCRIPTION:Payam Heydari\, associate professor of electrical engineering and computer science\, and a Calit2 academic affiliate at UC Irvine\, has won this year’s prestigious Guillemin- Cauer Award from the IEEE Circuits and Systems Society. Heydari is also the recipient of the 2005 IEEE Circuits and Systems Society Darlington Award\, which puts him in an elite group of only seven researchers who\, in the 40-year history of the awards\, have received both.\nHeydari was recognized for his paper “Model-Order Reduction Using Variational Balanced Truncation with Spectral Shaping\,” which was published in the IEEE Transactions on Circuits and Systems\, Vol. 53\, April 2006. \nThe latest integrated circuit technology – geared to the nanoscale – continues to create new possibilities for designers to substantially reduce chip size and increase speed. The technology\, however\, also presents challenges\, most notably to the yield and reliability of the circuits and on-chip wires. \nIt is essential to capture statistical fluctuations caused by process variations\, but testing such complicated systems can require days of computer simulation. Heydari’s approach dramatically reduces the time needed for this statistical modeling from days to just minutes. It significantly reduces the order of the original system while retaining important circuit characteristics\, such as frequency and timedomain. Most notably\, this technique accounts for statistical variation due to changes in process. \nIn addition\, Heydari’s approach provides a proven boundary for error between the reduced order model and the original system. The work has since been the foundation for several key papers published by other researchers on the same topic. \nThe Guillemin-Cauer Award recognizes the best journal paper published in IEEE Transactions on Circuits and Systems during the two calendar years preceding the award. The award is based on general quality\, originality\, contributions\, subject matter and timeliness.
URL:https://www.cecs.uci.edu/event/payam-heydari-wins-guillemin-cauer/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070501T220000
DTEND;TZID=America/Los_Angeles:20070501T220000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14197-1178056800-1178056800@www.cecs.uci.edu
SUMMARY:Bita Gorjiara Takes Hami and Best Paper Award
DESCRIPTION:Bita Gorjiara has won the prestigious Hami Award of Excellence in Engineering Education for the year 2007. Sponsored by the Fanni Reunion Foundation\, the Hami award recognizes outstanding M.Sc. and Ph.D. graduates with a previous degree from University of Tehran. Each year\, Hami award is given to one or two students with excellent academic record in terms of GPA\, number of publications\, and overall contribution in their field of study. Bita has also received the Best Student Paper Award for her journal paper\, “Ultra-Fast and Efficient Algorithm for Energy Optimization by Gradient-based Stochastic Voltage and Task Scheduling\,” which has also been accepted for publication in ACM Transactions on Design Automation of Electronic Systems (TODAES).\nThis paper award is an honor given by the EECS department for first-time authors. In her paper\, co-authored by Professor Bagherzadeh and Professor Chou\, Bita proposes an ultra-fast and voltage scheduling algorithm called Adaptive Stocahstic Gradient Voltage-and-Task Scheduling (ASG-VTS) that is used for power optimization of designs with voltage islands. This unique technique was shows to surpass the energy savings of previously published results while reducing number of voltage transitions. Compared to an optimal ILP algorithm\, her technique converges 1000 times faster while generating results as good as the optimal solution. She has also developed a web-based tool for her algorithm that allows researchers to capture the model of their system and run ASG-VTS. Research groups use Bita’s tool for evaluating new algorithms\, and some universities have used as part of their course curriculum. \nCurrently\, and for the past three years\, Bita has been working on No-Instruction-Set Computer (NISC) project under supervision of Prof. Gajski. She has developed an Architecture Description Language (ADL) for NISC called GNR that is used for automatic generation of RTL code. She has also proposed techniques to reduce power consumption and code size of NISCs while improving their performance via architecture customization.
URL:https://www.cecs.uci.edu/event/bita-gorjiara-takes-hami-and-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070426T150000
DTEND;TZID=America/Los_Angeles:20070426T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192254Z
UID:14240-1177599600-1177603200@www.cecs.uci.edu
SUMMARY:High Level Systems Validation Using Hierarchical Message Sequence Charts
DESCRIPTION:Dr. Praveen Murthy\, Fujitsu Labs of AmericaCalit2 Auditorium\, University of California\, Irvine\nApril 26\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/high-level-systems-validation-using-hierarchical-message-sequence-charts/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070423T150000
DTEND;TZID=America/Los_Angeles:20070423T160000
DTSTAMP:20231011T184245Z
CREATED:20231011T184245Z
LAST-MODIFIED:20231011T184245Z
UID:14334-1177340400-1177344000@www.cecs.uci.edu
SUMMARY:Software for Embedded Systems: Serializing Compilers and Its Applications
DESCRIPTION:Software for Embedded Systems: Serializing Compilers and Its  Applications\nby Andre Costi Nacul \nIn order to cope with the complexity of systems\, engineers are  turning to software. In part\, well established programming models\,  highly evolved tool chains\, ease of software reuse\, availability of  open-source software\, and expeditious nature of the design-compile- execute paradigm make developing a new feature in software more  favorable. It is assumed that\, in coming years\, more than 70% of  product features are going to be supported by software.\nIn particular\, the concurrent programming paradigm is an ideal model  of computation for design of embedded systems\, which often encompass  inherent concurrency. The support for concurrent programming is  usually provided by a real-time operating system (RTOS). Usually\, an  RTOS is a generic framework which can be used across a large number  of processors and applications. An RTOS provides coarse grained  timing support\, and is loosely coupled to the running tasks. As a  result\, an RTOS is seldom optimized for any particular application. \nDespite of all the recent enhancements to compiler technology\,  current compilers have a limited understanding of tasks. Generally\,  the compiler is tightly integrated with the platform. Traditional  compilers are efficient in using platform specific resources\, and in  generating an optimized instruction sequence. Current compiler  technology is capable of extracting instruction-level parallelism  (ILP)\, to varying degrees. Traditionally\, ILP comes from optimizing  loops\, and most likely analyzes code at the basic block level. Today\,  there is no compiler that can detect parallelism at the task level.  Parallelism detection is usually restricted to basic block  structures\, or higher level constructs such as loops. Moreover\,  compilers also lack support for timing constraints of real-time  applications. \nIn this thesis\, we propose an alternative to an RTOS based on the  idea of serializing compilers. A serializing compiler is an automated  software synthesis methodology that can transform a multitasking  application into an equivalent and optimized monolithic sequential  code\, to be compiled with the embedded processor’s native optimizing  compiler. The serializing compiler can analyze the tasks at compile  time and generate a fine-tuned\, application specific infrastructure  to support multitasking\, resulting in a more efficient executable  than one that is intended to run on top of a generic RTOS. By having  control over the application execution and context switches\, the  serializing compiler enables the fine grain control of task timing  while enhancing overall performance. Our serializing compiler  technology strengthens existing compilers\, making them timing and  task-aware. \nThe Phantom Compiler\, our implementation of a serializing compiler\,  provides a fully automated mechanism to synthesize a single threaded\,  ANSI C/C++ program from a multithreaded C/C++ (extended with POSIX)  program. The Phantom generated code is highly tuned for the input  application. With a serializing compiler such as the Phantom  Compiler\, it is possible to generate a multitasking infrastructure  that is small in size\, very efficient when context-switching\, and  customized for each specific application.
URL:https://www.cecs.uci.edu/event/software-for-embedded-systems-serializing-compilers-and-its-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070411T150000
DTEND;TZID=America/Los_Angeles:20070411T160000
DTSTAMP:20231011T184638Z
CREATED:20231011T184638Z
LAST-MODIFIED:20231011T184638Z
UID:14346-1176303600-1176307200@www.cecs.uci.edu
SUMMARY:New Strategies for System-Level Design
DESCRIPTION:New Strategies for System-Level Design: Where to Go?\nKeynote Talk \n\n\n\n\nSpeaker\n\n\nProfessor Gajski \nElectrical Engineering and Computer Science\nUniversity of California at Irvine\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nThe 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems\, Kraków\, Poland\n\n\n\n \n\n\n \n\n\n\nDate\n\n\nApril 11\, 2007\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nWith complexities of Systems-on-Chip rising almost daily\, the design community has been searching for new vision that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution\, such as increasing levels of abstraction\, introducing variety of IPs or offering new design languages will not solve the problem but only prolong the present status of inefficiency and confusion. What is needed is a drastic change in design automation for complex systems that consist of software and hardware. In order to design such systems efficiently\, we need a new approach with a new design flow\, with new models with well defined semantics and a new formalism that will support system synthesis and verification of software and hardware. \nIn order to find the solution\, we will look first at the system gap between SW and HW designs and derive requirements for the design flow that includes software as well as hardware. In order to enable new EDA tools for model generation\, simulation\, synthesis and verification\, the design flow has to be well defined with unique abstraction levels\, model semantics and model transformations corresponding to design decisions made by the designers. We will introduce the concept of model algebra that supports this approach and can serve as an enabler for the extreme makeover of EDA. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of complex systems to the basic principles of design science only.\n\n\n\n\n\n\n\n\n\n\nSlides\n\n\nDownload slides\n\n\n\n \n\n\n \n\n\n\nBiography\n\n\n  \n\n \n\nDaniel Gajski\, a leader in the areas of embedded systems\, design methodologies and languages\, headed the research teams that created new design concepts\, methodologies\, tools and languages. He was instrumental in developing formalisms such as Y-chart\, and numerous algorithms for high-level synthesis\, the definition of the control-data-flow-graph (CDFG) and finite-state-machine with data (FSMD)\, system level languages such as SpecCharts and SpecC\, and design tools such as SpecSyn and Embedded-System Environment. Many of these concepts have been adapted by academia and industry in the last 25 years. \nGajski directs the UCI Center for Embedded Computer Systems\, with a research mission to incorporate embedded systems into automotive\, communications\, and medical applications. He has authored over 300 papers and numerous textbooks\, including Principles of Digital Design (Englewood Cliffs\, NJ: Prentice Hall\, 1997) that has been translated into several languages. \nHe holds Dipl. Ing. and M.S. degrees in electrical engineering from the University of Zagreb\, Croatia\, and a doctoral degree in computer and information sciences from the University of Pennsylvania\, Philadelphia. After 10 years as Professor at University of Illinois he has joined UCI\, where he presently holds The Henry Samueli Endowed Chair in Computer System Design.
URL:https://www.cecs.uci.edu/event/new-strategies-for-system-level-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070325T150000
DTEND;TZID=America/Los_Angeles:20070325T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14287-1174834800-1174838400@www.cecs.uci.edu
SUMMARY:Operating system kernel as a building block for scalable and fast network topology emulation
DESCRIPTION:Marko Zec\, University of Zagreb\, Croatia5251 California Ave.\, Suite 210 ( CECS Research Park Office)\, Unversity of California\, Irvine\nLecture\, May 25\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/operating-system-kernel-as-a-building-block-for-scalable-and-fast-network-topology-emulation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070316T150000
DTEND;TZID=America/Los_Angeles:20070316T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14241-1174057200-1174060800@www.cecs.uci.edu
SUMMARY:Embedded Control Software Engineering Methods and Tools Research at ISL\, Bangalore
DESCRIPTION:Dr. S. Ramesh\, Technical Fellow\, India Science Lab\, GM R&D Labs\, Bangalore\, IndiaCalit2 Auditorium\, University of California\, Irvine\nMarch 16\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/embedded-control-software-engineering-methods-and-tools-research-at-isl-bangalore/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070309T150000
DTEND;TZID=America/Los_Angeles:20070309T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14242-1173452400-1173456000@www.cecs.uci.edu
SUMMARY:Arithmetic Optimizations for System Design
DESCRIPTION:Dr. Farzan Fallah\, Fujitsu LaboratoriesCalit2 Auditorium\, University of Califonia\, Irvine\, CA\nLecture\, March 09\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/arithmetic-optimizations-for-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070305T150000
DTEND;TZID=America/Los_Angeles:20070305T160000
DTSTAMP:20231011T184246Z
CREATED:20231011T184246Z
LAST-MODIFIED:20231011T184246Z
UID:14335-1173106800-1173110400@www.cecs.uci.edu
SUMMARY:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems
DESCRIPTION:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems\nby Radu Cornea \nRecent advances in processor\, wireless and graphics technology have fueled a convergence of traditional PDA and cellphone functionality into complex\, media-centric mobile devices. A popular class of applications emerging on these platforms is represented by multimedia\, in particular content streaming (video\, audio). However\, all this added functionality has not come without an expense in one of the most important area for a mobile device: battery life. Multimedia streaming in particular\, with its stringent compu tation\, communication and quality of service requirements further aggravates battery life on these already constrained devices. \nOn the other hand\, multimedia applications have very regular execution patterns\, the only changes being introduced by variations in the data stream itself. This thesis presents a new way to optimize power consumption for multimedia applications\, based on content analysis and annotations. Specifically\, we pre-process the multimedia streams and utilize annotations to capture and carry content-related information to the client device at the receiving end. Annotations allow us to perform more accurate and aggressive optimizations\, with knowledge of the actual content and without relying to less accurate prediction models. \nWe investigate the use of annotation for content-aware optimizations at all level of abstraction (hardware/OS\, network\, application) for the most important system components in a mobile device: CPU/memory\, network interface\, display. Our experimental results show that important energy savings can be achieved for all these components through annotations. Finally\, we integrate the techniques at all levels of abstraction for an increased user experience and battery functionality. We also show how cross-layer trade-offs between power and quality can lead to even higher energy savings with minimal quality degradation.
URL:https://www.cecs.uci.edu/event/content-annotation-for-power-and-quality-trade-offs-in-mobile-multimedia-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070222T150000
DTEND;TZID=America/Los_Angeles:20070222T160000
DTSTAMP:20231011T183308Z
CREATED:20231011T183308Z
LAST-MODIFIED:20231011T183308Z
UID:14288-1172156400-1172160000@www.cecs.uci.edu
SUMMARY:Automatic Parallelization with Hybrid Analysis
DESCRIPTION:Dr. Lawrence Rauchwerger\,Texas A&M UniversityCalit2\, Room 3008\, University of Califonia\, Irvine\, CA\nLecture\, February 22\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/automatic-parallelization-with-hybrid-analysis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070220T150000
DTEND;TZID=America/Los_Angeles:20070220T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14289-1171983600-1171987200@www.cecs.uci.edu
SUMMARY:Research Challenges in High Performance VLSI/SoC Circuits and Systems
DESCRIPTION:Professor. Eby G. Friedman\, University of RochesterMcDonnell Douglas Auditorium\, University of Califonia\, Irvine\, CA\nDistinguished Lecture\, February 20\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/research-challenges-in-high-performance-vlsi-soc-circuits-and-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070205T150000
DTEND;TZID=America/Los_Angeles:20070205T160000
DTSTAMP:20231011T184246Z
CREATED:20231011T184246Z
LAST-MODIFIED:20231011T184246Z
UID:14336-1170687600-1170691200@www.cecs.uci.edu
SUMMARY:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications
DESCRIPTION:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications\nby Ilya Michailovich Issenin \nWith increasing processing power demands of embedded applications and technology advances\, Multiprocessor Systems-on-Chip (MPSoCs) become prevalent in embedded systems. The memory subsystem is a large and critical contributor to both energy and performance of such systems\, requiring system designers to perform exploration of low power memory organizations. In this dissertation we present an automated approach for data memory subsystem customization for streaming applications. Our approach allows modification of the program to use custom scratch pad memory configurations comprising a hierarchical set of buffers for local storage of frequently reused data. Our data reuse analysis technique provides the system designer with a wide range of customized memory hierarchy organizations with different size and energy profiles and enables the system designer to explore feasible memory subsystem solutions that satisfy power and area constraints while still meeting task deadlines\, both for uniprocessor and multiprocessor systems. \nIn modern multiprocessor embedded systems the communication subsystem also plays an important role in determining overall system power consumption and performance. We propose novel approaches that enables energy-aware co-synthesis of both memory and communication architectures for streaming applications targeting hierarchical bus-based and Network-on-Chip communication architectures. Our techniques achieve significant reduction in memory and communication subsystems energy consumption for data dominant applications\, and allow system designers to explore custom scratch pad memory configuration for a range of power and area constraints. \nThesis\nSlides
URL:https://www.cecs.uci.edu/event/multiprocessor-system-on-chip-data-memory-customization-for-embedded-array-intensive-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070119T150000
DTEND;TZID=America/Los_Angeles:20070119T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14290-1169218800-1169222400@www.cecs.uci.edu
SUMMARY:From Service Composition to Gadget Composition: Enabling Process-Oriented Web
DESCRIPTION:Dr. Sinisa Srbljic\, University of Zagreb\, CroatiaMcDonnell Douglas Auditorium\, University of Califonia\, Irvine\, CA\nDistinguished Lecture\, January 19\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/from-service-composition-to-gadget-composition-enabling-process-oriented-web/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20061128T150000
DTEND;TZID=America/Los_Angeles:20061128T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14377-1164726000-1164729600@www.cecs.uci.edu
SUMMARY:Farewell to IERF Building
DESCRIPTION:Professor Givargis hosted the lunch to say farwell to the IERF building.
URL:https://www.cecs.uci.edu/event/farewell-to-ierf-building/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20061031T150000
DTEND;TZID=America/Los_Angeles:20061031T160000
DTSTAMP:20231011T190252Z
CREATED:20231011T190252Z
LAST-MODIFIED:20231011T190252Z
UID:14378-1162306800-1162310400@www.cecs.uci.edu
SUMMARY:CECS Faculty-Students Gathering 2006
DESCRIPTION:
URL:https://www.cecs.uci.edu/event/cecs-faculty-students-gathering-2006/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060928T150000
DTEND;TZID=America/Los_Angeles:20060928T160000
DTSTAMP:20231205T135319Z
CREATED:20231011T185235Z
LAST-MODIFIED:20231205T135319Z
UID:14360-1159455600-1159459200@www.cecs.uci.edu
SUMMARY:SpecC Reference Compiler
DESCRIPTION:Release Date: September 28\, 2006 (version 2.1)Web Site: https://www.cecs.uci.edu/~specc/ \nThe SpecC Reference Compiler (SCRC) is an Open Source implementation of a compiler and simulator for the SpecC language. \nThe goal of the SpecC Reference Compiler is to: \n\npromote SpecC standardization\nprovide a reference implementation\, that is\n\ncompliant with the SpecC Language Reference Manual (LRM V2.0)\nfreely available\n\n\nprovide a basis for SpecC tool development\n\nThe SCRC distribution consists of: \n\na SpecC compiler (parser\, internal representation\, code generator)\na SpecC simulator (run-time libraries for SpecC execution)\na SpecC standard channel library (channels for synchronization\, etc.)\na test suite (SpecC LRM compliance test cases)\n\nReference:\nR. Doemer\, A. Gerstlauer\, and D. Gajski\, “SpecC Language Reference Manual\, Version 2.0\,” December 12\, 2002 .\ndownload pdf
URL:https://www.cecs.uci.edu/event/specc-reference-compiler/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060803T180000
DTEND;TZID=America/Los_Angeles:20060803T180000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14201-1154628000-1154628000@www.cecs.uci.edu
SUMMARY:Love and Eli Take FPL’06 Best Paper Award
DESCRIPTION:Love Singhal\, a Ph.D. candidate in computer science\, and professor of computer science Eli Bozorgzadeh received the Best Paper Award at the 2006 IEEE International Conference on Field Programmable Logic and Applications (FPL’06) that took place in Madrid\, Spain\, August 28-30 2006. The awarded paper is titled “Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.”\nThe dynamic partial reconfigurability of programmable devices such as FPGAs is characterized by their ability to reconfigure subsets of their logic and routing resources at runtime. This intrinsic dynamic reconfiguration results in accommodation of complex and dense designs\, on-fly adaptivity\, and design modification. Reconfigurable module can be a new coprocessor implemented on a FPGA device\, an upgraded implementation of the existing module\, or a reconfigured memory block. However\, partial reconfiguration comes with the cost of reconfiguration overhead delays. In order to reduce the reconfiguration overhead\, two consecutive similar sub-designs should be placed in the same locations to get the maximum reuse of common components. \nIn this paper\, a new multi-layer sequencepair- based floorplanner is proposed for a given sequence of reconfigurable designs. In the experiments\, compared to a traditional sequential floorplanner\, the new floorplanner removes infeasibility in many designs\, and provides faster timing closure. \nFPL is the first and largest conference on programmable logic which encompasses a wide range of research area on FPGAs\, including applications\, novel system architectures and CAD tools\, embedded processors\, dynamic recon figuration\, etc. The acceptance rate in FPL 2006 was 28 percent\, out of 307 submissions.
URL:https://www.cecs.uci.edu/event/love-and-eli-take-fpl06-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060714T150000
DTEND;TZID=America/Los_Angeles:20060714T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14291-1152889200-1152892800@www.cecs.uci.edu
SUMMARY:Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform
DESCRIPTION:Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform\n\n\n\n\nSpeaker\n\n\nDr. Youn-Long Steve Lin\nDepartment of Computer Science\nNational Tsing-Hua University\, Taiwan\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDouglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 14 \, 2006\nRefreshments at 10:30 am\, followed by Lecture at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHere in Tsing Hua\, we have developed a pure hardwired AMBA-compliant accelerator for H.264/AVC main profile. Integrated into the FPGA module of a multimedia SOC platform\, it can real-time decode CIF video running at just 10MHz. I will give a brief introduction to H.264/AVC\, the next generation video coding standard. Then I will describe the SOC platform and system design flow jointly developed by Tsing Hua and Global UniChip Corp. Finally\, I will present several architectural innovations in the decoder core that lead to high performance.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nYoun-Long Steve Lin received his B.S. degree in Electronics Engineering from National Taiwan University of Science and Technology\, Taipei\, Taiwan in 1982\, and Ph.D degree in Computer Science from the University of Illinois\, Urbana-Champaign\, IL.\, in 1987. Upon his graduation\, he joined National Tsing Hua University\, Hsin-Chu\, Taiwan\, where he established the THEDA Group (Tsing Hua EDA)\, served as Director of the University Computer and Communication Center\, Chairman of the Department of Computer Science\, Secretariat General of the University and Director of the University Library. Youn-Long Steve Lin is currently a Professor of Computer Science at the National Tsing Hua University\, Hsin-Chu\, Taiwan. He is also an Adjunct Professor at Peking University\, Beijing\, China. He is elected the president of Taiwan Integrated Circuit Design Society (TICD) for 2005-2006. \nProfessor Lin’s primary research interest is in computer-aided design (CAD) of very large-scale integrated circuits (VLSI) with emphasis on physical design automation and high-level synthesis. He co-authored the book “High Level Synthesis—Introduction to Chip and System Design.” He also spends great effort in promoting the VLSI design and CAD education in Taiwan. His current research focus is on design technology for System-on-a-Chips (SOC) employing reusable silicon intellectual properties (IPs). He is a senior member of the IEEE\, the IEEE Computer Society\, the IEEE Circuit and System Society\, the IEEE Solid State Circuit Society\, and the Association for Computer Machinery. He is a board member of the Taiwan IC Design Society. He is a nation-certified electrical engineer.
URL:https://www.cecs.uci.edu/event/development-of-an-h-264-avc-decoder-prototype-on-a-multimedia-soc-platform/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060501T150000
DTEND;TZID=America/Los_Angeles:20060501T160000
DTSTAMP:20231011T185642Z
CREATED:20231011T185642Z
LAST-MODIFIED:20231011T185642Z
UID:14371-1146495600-1146499200@www.cecs.uci.edu
SUMMARY:Emerging Challenges in Assuring Functional Correctness of VLSI Devices for Mobile Applications
DESCRIPTION:Scott RunnerDirector of the Design Verification Team\, Qualcomm CDMA Technologies\nSan Diego\, CA\nMay 1\, 2006\nMcDonnell Douglas Auditorium\nAbstract
URL:https://www.cecs.uci.edu/event/emerging-challenges-in-assuring-functional-correctness-of-vlsi-devices-for-mobile-applications-2/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060501T150000
DTEND;TZID=America/Los_Angeles:20060501T160000
DTSTAMP:20231011T192054Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192054Z
UID:14235-1146495600-1146499200@www.cecs.uci.edu
SUMMARY:Emerging Challenges in Assuring Functional Correctness of VLSI Devices  for Mobile Applications
DESCRIPTION:Scott Runner\, Qualcomm CDMA TechnologiesMcDonnel Douglas Auditorium\, University of California\, Irvine\nMay 1\, 2006\nAbstract
URL:https://www.cecs.uci.edu/event/emerging-challenges-in-assuring-functional-correctness-of-vlsi-devices-for-mobile-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060427T150000
DTEND;TZID=America/Los_Angeles:20060427T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T190240Z
UID:14293-1146150000-1146153600@www.cecs.uci.edu
SUMMARY:How Many Cores is too Many Cores?
DESCRIPTION:Dr. Avi MendelsonIntel Israel\nApril 27\, 2006\nIERF 144/148\nAbstract
URL:https://www.cecs.uci.edu/event/how-many-cores-is-too-many-cores/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060427T150000
DTEND;TZID=America/Los_Angeles:20060427T160000
DTSTAMP:20231011T185642Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T185642Z
UID:14292-1146150000-1146153600@www.cecs.uci.edu
SUMMARY:Challenges in Compiling for Modern Architectures
DESCRIPTION:Dr. Bilha MendelsonIBM Haifa Research Lab\, Israel\nApril 27\, 2006\nIERF 144/148\nAbstract
URL:https://www.cecs.uci.edu/event/challenges-in-compiling-for-modern-architectures/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060328T200000
DTEND;TZID=America/Los_Angeles:20060328T200000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14199-1143576000-1143576000@www.cecs.uci.edu
SUMMARY:Sudeep Pasricha recieves Center for Pervasive Communications and Computing (CPCC) Fellowship Award
DESCRIPTION:Graduate Student  Sudeep Pasricha has been selected for the Center for Pervasive Communications and Computing (CPCC) fellowship award for 2005/2006. He was also a previous recipient of this award for the term of 2004/2005.
URL:https://www.cecs.uci.edu/event/sudeep-pasricha-recieves-center-for-pervasive-communications-and-computing-cpcc-fellowship-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060317T150000
DTEND;TZID=America/Los_Angeles:20060317T160000
DTSTAMP:20231011T190252Z
CREATED:20231011T190252Z
LAST-MODIFIED:20231011T190252Z
UID:14379-1142607600-1142611200@www.cecs.uci.edu
SUMMARY:Dr. Gajski's Honorary Doctrine Celebration
DESCRIPTION:Professor Alex Veidenbaum hosted the reception for Dr. Gajski’s honorary doctrine celebration.
URL:https://www.cecs.uci.edu/event/dr-gajskis-honorary-doctrine-celebration/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060302T150000
DTEND;TZID=America/Los_Angeles:20060302T160000
DTSTAMP:20231011T184246Z
CREATED:20231011T184246Z
LAST-MODIFIED:20231011T184246Z
UID:14337-1141311600-1141315200@www.cecs.uci.edu
SUMMARY:Acceleration beyond Memory Barriers in IS-extensible Processors
DESCRIPTION:Acceleration beyond Memory Barriers in IS-extensible Processors\nby Partha Biswas \nExtensible processors refer to a class of processors that can be customized for a given application with new designer-defined functional units. One popular feature to extend is the Instruction Set (IS) of the processor—we call such a processor an IS-extensible processor. In an IS-extensible processor\, applications can be accelerated by extending the processor architecture with Application-specific Functional Units (AFUs)\, which execute Instruction Set Extensions (ISEs) in the critical segments of the applications. Automatic identification of such ISEs is the key step in automating the process of processor customization. \nA high-quality ISE identification approach needs to obtain results close to those achieved by experienced designers\, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. This thesis develops an ISE identification algorithm (ISEGEN)\, which identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Traditionally\, synchronization issues have discouraged the inclusion of memory operations in ISEs during the ISE identification step\, causing a “memory barrier”. We show in this thesis that it is possible to go beyond these memory barriers and accelerate the application even more than the traditional ISE identification approaches by eliminating costly memory operations. We present the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively. Finally\, we develop an interface-aware processor customization methodology and use the methodology to realize an IS-extensible-processor-based system on a real platform. \nExperimental results on a number of MediaBench\, EEMBC and cryptographic applications demonstrate that our ISEGEN approach matches the quality of the optimal solution obtained by exhaustive search. We show that our ISEGEN technique is on average 20X faster than a genetic formulation that generates equivalent solutions. We also demonstrate the effectiveness of our approach by incorporating the generated ISEs in the cycle-accurate SimpleScalar simulator. The average speedup on the selected benchmarks increases from 1.4X to 2.8X when the ISE identification process goes beyond memory barriers. Furthermore\, we show a concomitant reduction in energy consumption as a result of reduced cache pollution. In addition to analytical and simulation-based evaluation of the identified ISEs\, we implement our approach in a realistic hardware-software system that allows us to comprehensively study the effect of ISEs on performance\, energy\, power\, and code size using our interface-aware processor customization methodology. Our experiments on a Xilinx Virtex II board—employing the Microblaze soft-core as an extensible processor—show a simultaneous increase in performance\, and reduction in code size\, energy and power consumption with the incorporation of the AFU in the Microblaze soft-core processor.
URL:https://www.cecs.uci.edu/event/acceleration-beyond-memory-barriers-in-is-extensible-processors/
CATEGORIES:PhD Defenses
END:VEVENT
END:VCALENDAR