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X-ORIGINAL-URL:https://www.cecs.uci.edu
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070309T150000
DTEND;TZID=America/Los_Angeles:20070309T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14242-1173452400-1173456000@www.cecs.uci.edu
SUMMARY:Arithmetic Optimizations for System Design
DESCRIPTION:Dr. Farzan Fallah\, Fujitsu LaboratoriesCalit2 Auditorium\, University of Califonia\, Irvine\, CA\nLecture\, March 09\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/arithmetic-optimizations-for-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070305T150000
DTEND;TZID=America/Los_Angeles:20070305T160000
DTSTAMP:20231011T184246Z
CREATED:20231011T184246Z
LAST-MODIFIED:20231011T184246Z
UID:14335-1173106800-1173110400@www.cecs.uci.edu
SUMMARY:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems
DESCRIPTION:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems\nby Radu Cornea \nRecent advances in processor\, wireless and graphics technology have fueled a convergence of traditional PDA and cellphone functionality into complex\, media-centric mobile devices. A popular class of applications emerging on these platforms is represented by multimedia\, in particular content streaming (video\, audio). However\, all this added functionality has not come without an expense in one of the most important area for a mobile device: battery life. Multimedia streaming in particular\, with its stringent compu tation\, communication and quality of service requirements further aggravates battery life on these already constrained devices. \nOn the other hand\, multimedia applications have very regular execution patterns\, the only changes being introduced by variations in the data stream itself. This thesis presents a new way to optimize power consumption for multimedia applications\, based on content analysis and annotations. Specifically\, we pre-process the multimedia streams and utilize annotations to capture and carry content-related information to the client device at the receiving end. Annotations allow us to perform more accurate and aggressive optimizations\, with knowledge of the actual content and without relying to less accurate prediction models. \nWe investigate the use of annotation for content-aware optimizations at all level of abstraction (hardware/OS\, network\, application) for the most important system components in a mobile device: CPU/memory\, network interface\, display. Our experimental results show that important energy savings can be achieved for all these components through annotations. Finally\, we integrate the techniques at all levels of abstraction for an increased user experience and battery functionality. We also show how cross-layer trade-offs between power and quality can lead to even higher energy savings with minimal quality degradation.
URL:https://www.cecs.uci.edu/event/content-annotation-for-power-and-quality-trade-offs-in-mobile-multimedia-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070222T150000
DTEND;TZID=America/Los_Angeles:20070222T160000
DTSTAMP:20231011T183308Z
CREATED:20231011T183308Z
LAST-MODIFIED:20231011T183308Z
UID:14288-1172156400-1172160000@www.cecs.uci.edu
SUMMARY:Automatic Parallelization with Hybrid Analysis
DESCRIPTION:Dr. Lawrence Rauchwerger\,Texas A&M UniversityCalit2\, Room 3008\, University of Califonia\, Irvine\, CA\nLecture\, February 22\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/automatic-parallelization-with-hybrid-analysis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070220T150000
DTEND;TZID=America/Los_Angeles:20070220T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14289-1171983600-1171987200@www.cecs.uci.edu
SUMMARY:Research Challenges in High Performance VLSI/SoC Circuits and Systems
DESCRIPTION:Professor. Eby G. Friedman\, University of RochesterMcDonnell Douglas Auditorium\, University of Califonia\, Irvine\, CA\nDistinguished Lecture\, February 20\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/research-challenges-in-high-performance-vlsi-soc-circuits-and-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070205T150000
DTEND;TZID=America/Los_Angeles:20070205T160000
DTSTAMP:20231011T184246Z
CREATED:20231011T184246Z
LAST-MODIFIED:20231011T184246Z
UID:14336-1170687600-1170691200@www.cecs.uci.edu
SUMMARY:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications
DESCRIPTION:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications\nby Ilya Michailovich Issenin \nWith increasing processing power demands of embedded applications and technology advances\, Multiprocessor Systems-on-Chip (MPSoCs) become prevalent in embedded systems. The memory subsystem is a large and critical contributor to both energy and performance of such systems\, requiring system designers to perform exploration of low power memory organizations. In this dissertation we present an automated approach for data memory subsystem customization for streaming applications. Our approach allows modification of the program to use custom scratch pad memory configurations comprising a hierarchical set of buffers for local storage of frequently reused data. Our data reuse analysis technique provides the system designer with a wide range of customized memory hierarchy organizations with different size and energy profiles and enables the system designer to explore feasible memory subsystem solutions that satisfy power and area constraints while still meeting task deadlines\, both for uniprocessor and multiprocessor systems. \nIn modern multiprocessor embedded systems the communication subsystem also plays an important role in determining overall system power consumption and performance. We propose novel approaches that enables energy-aware co-synthesis of both memory and communication architectures for streaming applications targeting hierarchical bus-based and Network-on-Chip communication architectures. Our techniques achieve significant reduction in memory and communication subsystems energy consumption for data dominant applications\, and allow system designers to explore custom scratch pad memory configuration for a range of power and area constraints. \nThesis\nSlides
URL:https://www.cecs.uci.edu/event/multiprocessor-system-on-chip-data-memory-customization-for-embedded-array-intensive-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070119T150000
DTEND;TZID=America/Los_Angeles:20070119T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14290-1169218800-1169222400@www.cecs.uci.edu
SUMMARY:From Service Composition to Gadget Composition: Enabling Process-Oriented Web
DESCRIPTION:Dr. Sinisa Srbljic\, University of Zagreb\, CroatiaMcDonnell Douglas Auditorium\, University of Califonia\, Irvine\, CA\nDistinguished Lecture\, January 19\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/from-service-composition-to-gadget-composition-enabling-process-oriented-web/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20061128T150000
DTEND;TZID=America/Los_Angeles:20061128T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14377-1164726000-1164729600@www.cecs.uci.edu
SUMMARY:Farewell to IERF Building
DESCRIPTION:Professor Givargis hosted the lunch to say farwell to the IERF building.
URL:https://www.cecs.uci.edu/event/farewell-to-ierf-building/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20061031T150000
DTEND;TZID=America/Los_Angeles:20061031T160000
DTSTAMP:20231011T190252Z
CREATED:20231011T190252Z
LAST-MODIFIED:20231011T190252Z
UID:14378-1162306800-1162310400@www.cecs.uci.edu
SUMMARY:CECS Faculty-Students Gathering 2006
DESCRIPTION:
URL:https://www.cecs.uci.edu/event/cecs-faculty-students-gathering-2006/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060928T150000
DTEND;TZID=America/Los_Angeles:20060928T160000
DTSTAMP:20231205T135319Z
CREATED:20231011T185235Z
LAST-MODIFIED:20231205T135319Z
UID:14360-1159455600-1159459200@www.cecs.uci.edu
SUMMARY:SpecC Reference Compiler
DESCRIPTION:Release Date: September 28\, 2006 (version 2.1)Web Site: https://www.cecs.uci.edu/~specc/ \nThe SpecC Reference Compiler (SCRC) is an Open Source implementation of a compiler and simulator for the SpecC language. \nThe goal of the SpecC Reference Compiler is to: \n\npromote SpecC standardization\nprovide a reference implementation\, that is\n\ncompliant with the SpecC Language Reference Manual (LRM V2.0)\nfreely available\n\n\nprovide a basis for SpecC tool development\n\nThe SCRC distribution consists of: \n\na SpecC compiler (parser\, internal representation\, code generator)\na SpecC simulator (run-time libraries for SpecC execution)\na SpecC standard channel library (channels for synchronization\, etc.)\na test suite (SpecC LRM compliance test cases)\n\nReference:\nR. Doemer\, A. Gerstlauer\, and D. Gajski\, “SpecC Language Reference Manual\, Version 2.0\,” December 12\, 2002 .\ndownload pdf
URL:https://www.cecs.uci.edu/event/specc-reference-compiler/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060803T180000
DTEND;TZID=America/Los_Angeles:20060803T180000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14201-1154628000-1154628000@www.cecs.uci.edu
SUMMARY:Love and Eli Take FPL’06 Best Paper Award
DESCRIPTION:Love Singhal\, a Ph.D. candidate in computer science\, and professor of computer science Eli Bozorgzadeh received the Best Paper Award at the 2006 IEEE International Conference on Field Programmable Logic and Applications (FPL’06) that took place in Madrid\, Spain\, August 28-30 2006. The awarded paper is titled “Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.”\nThe dynamic partial reconfigurability of programmable devices such as FPGAs is characterized by their ability to reconfigure subsets of their logic and routing resources at runtime. This intrinsic dynamic reconfiguration results in accommodation of complex and dense designs\, on-fly adaptivity\, and design modification. Reconfigurable module can be a new coprocessor implemented on a FPGA device\, an upgraded implementation of the existing module\, or a reconfigured memory block. However\, partial reconfiguration comes with the cost of reconfiguration overhead delays. In order to reduce the reconfiguration overhead\, two consecutive similar sub-designs should be placed in the same locations to get the maximum reuse of common components. \nIn this paper\, a new multi-layer sequencepair- based floorplanner is proposed for a given sequence of reconfigurable designs. In the experiments\, compared to a traditional sequential floorplanner\, the new floorplanner removes infeasibility in many designs\, and provides faster timing closure. \nFPL is the first and largest conference on programmable logic which encompasses a wide range of research area on FPGAs\, including applications\, novel system architectures and CAD tools\, embedded processors\, dynamic recon figuration\, etc. The acceptance rate in FPL 2006 was 28 percent\, out of 307 submissions.
URL:https://www.cecs.uci.edu/event/love-and-eli-take-fpl06-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060714T150000
DTEND;TZID=America/Los_Angeles:20060714T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14291-1152889200-1152892800@www.cecs.uci.edu
SUMMARY:Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform
DESCRIPTION:Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform\n\n\n\n\nSpeaker\n\n\nDr. Youn-Long Steve Lin\nDepartment of Computer Science\nNational Tsing-Hua University\, Taiwan\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDouglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 14 \, 2006\nRefreshments at 10:30 am\, followed by Lecture at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHere in Tsing Hua\, we have developed a pure hardwired AMBA-compliant accelerator for H.264/AVC main profile. Integrated into the FPGA module of a multimedia SOC platform\, it can real-time decode CIF video running at just 10MHz. I will give a brief introduction to H.264/AVC\, the next generation video coding standard. Then I will describe the SOC platform and system design flow jointly developed by Tsing Hua and Global UniChip Corp. Finally\, I will present several architectural innovations in the decoder core that lead to high performance.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nYoun-Long Steve Lin received his B.S. degree in Electronics Engineering from National Taiwan University of Science and Technology\, Taipei\, Taiwan in 1982\, and Ph.D degree in Computer Science from the University of Illinois\, Urbana-Champaign\, IL.\, in 1987. Upon his graduation\, he joined National Tsing Hua University\, Hsin-Chu\, Taiwan\, where he established the THEDA Group (Tsing Hua EDA)\, served as Director of the University Computer and Communication Center\, Chairman of the Department of Computer Science\, Secretariat General of the University and Director of the University Library. Youn-Long Steve Lin is currently a Professor of Computer Science at the National Tsing Hua University\, Hsin-Chu\, Taiwan. He is also an Adjunct Professor at Peking University\, Beijing\, China. He is elected the president of Taiwan Integrated Circuit Design Society (TICD) for 2005-2006. \nProfessor Lin’s primary research interest is in computer-aided design (CAD) of very large-scale integrated circuits (VLSI) with emphasis on physical design automation and high-level synthesis. He co-authored the book “High Level Synthesis—Introduction to Chip and System Design.” He also spends great effort in promoting the VLSI design and CAD education in Taiwan. His current research focus is on design technology for System-on-a-Chips (SOC) employing reusable silicon intellectual properties (IPs). He is a senior member of the IEEE\, the IEEE Computer Society\, the IEEE Circuit and System Society\, the IEEE Solid State Circuit Society\, and the Association for Computer Machinery. He is a board member of the Taiwan IC Design Society. He is a nation-certified electrical engineer.
URL:https://www.cecs.uci.edu/event/development-of-an-h-264-avc-decoder-prototype-on-a-multimedia-soc-platform/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060501T150000
DTEND;TZID=America/Los_Angeles:20060501T160000
DTSTAMP:20231011T185642Z
CREATED:20231011T185642Z
LAST-MODIFIED:20231011T185642Z
UID:14371-1146495600-1146499200@www.cecs.uci.edu
SUMMARY:Emerging Challenges in Assuring Functional Correctness of VLSI Devices for Mobile Applications
DESCRIPTION:Scott RunnerDirector of the Design Verification Team\, Qualcomm CDMA Technologies\nSan Diego\, CA\nMay 1\, 2006\nMcDonnell Douglas Auditorium\nAbstract
URL:https://www.cecs.uci.edu/event/emerging-challenges-in-assuring-functional-correctness-of-vlsi-devices-for-mobile-applications-2/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060501T150000
DTEND;TZID=America/Los_Angeles:20060501T160000
DTSTAMP:20231011T192054Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192054Z
UID:14235-1146495600-1146499200@www.cecs.uci.edu
SUMMARY:Emerging Challenges in Assuring Functional Correctness of VLSI Devices  for Mobile Applications
DESCRIPTION:Scott Runner\, Qualcomm CDMA TechnologiesMcDonnel Douglas Auditorium\, University of California\, Irvine\nMay 1\, 2006\nAbstract
URL:https://www.cecs.uci.edu/event/emerging-challenges-in-assuring-functional-correctness-of-vlsi-devices-for-mobile-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060427T150000
DTEND;TZID=America/Los_Angeles:20060427T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T190240Z
UID:14293-1146150000-1146153600@www.cecs.uci.edu
SUMMARY:How Many Cores is too Many Cores?
DESCRIPTION:Dr. Avi MendelsonIntel Israel\nApril 27\, 2006\nIERF 144/148\nAbstract
URL:https://www.cecs.uci.edu/event/how-many-cores-is-too-many-cores/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060427T150000
DTEND;TZID=America/Los_Angeles:20060427T160000
DTSTAMP:20231011T185642Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T185642Z
UID:14292-1146150000-1146153600@www.cecs.uci.edu
SUMMARY:Challenges in Compiling for Modern Architectures
DESCRIPTION:Dr. Bilha MendelsonIBM Haifa Research Lab\, Israel\nApril 27\, 2006\nIERF 144/148\nAbstract
URL:https://www.cecs.uci.edu/event/challenges-in-compiling-for-modern-architectures/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060328T200000
DTEND;TZID=America/Los_Angeles:20060328T200000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14199-1143576000-1143576000@www.cecs.uci.edu
SUMMARY:Sudeep Pasricha recieves Center for Pervasive Communications and Computing (CPCC) Fellowship Award
DESCRIPTION:Graduate Student  Sudeep Pasricha has been selected for the Center for Pervasive Communications and Computing (CPCC) fellowship award for 2005/2006. He was also a previous recipient of this award for the term of 2004/2005.
URL:https://www.cecs.uci.edu/event/sudeep-pasricha-recieves-center-for-pervasive-communications-and-computing-cpcc-fellowship-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060317T150000
DTEND;TZID=America/Los_Angeles:20060317T160000
DTSTAMP:20231011T190252Z
CREATED:20231011T190252Z
LAST-MODIFIED:20231011T190252Z
UID:14379-1142607600-1142611200@www.cecs.uci.edu
SUMMARY:Dr. Gajski's Honorary Doctrine Celebration
DESCRIPTION:Professor Alex Veidenbaum hosted the reception for Dr. Gajski’s honorary doctrine celebration.
URL:https://www.cecs.uci.edu/event/dr-gajskis-honorary-doctrine-celebration/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060302T150000
DTEND;TZID=America/Los_Angeles:20060302T160000
DTSTAMP:20231011T184246Z
CREATED:20231011T184246Z
LAST-MODIFIED:20231011T184246Z
UID:14337-1141311600-1141315200@www.cecs.uci.edu
SUMMARY:Acceleration beyond Memory Barriers in IS-extensible Processors
DESCRIPTION:Acceleration beyond Memory Barriers in IS-extensible Processors\nby Partha Biswas \nExtensible processors refer to a class of processors that can be customized for a given application with new designer-defined functional units. One popular feature to extend is the Instruction Set (IS) of the processor—we call such a processor an IS-extensible processor. In an IS-extensible processor\, applications can be accelerated by extending the processor architecture with Application-specific Functional Units (AFUs)\, which execute Instruction Set Extensions (ISEs) in the critical segments of the applications. Automatic identification of such ISEs is the key step in automating the process of processor customization. \nA high-quality ISE identification approach needs to obtain results close to those achieved by experienced designers\, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. This thesis develops an ISE identification algorithm (ISEGEN)\, which identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Traditionally\, synchronization issues have discouraged the inclusion of memory operations in ISEs during the ISE identification step\, causing a “memory barrier”. We show in this thesis that it is possible to go beyond these memory barriers and accelerate the application even more than the traditional ISE identification approaches by eliminating costly memory operations. We present the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively. Finally\, we develop an interface-aware processor customization methodology and use the methodology to realize an IS-extensible-processor-based system on a real platform. \nExperimental results on a number of MediaBench\, EEMBC and cryptographic applications demonstrate that our ISEGEN approach matches the quality of the optimal solution obtained by exhaustive search. We show that our ISEGEN technique is on average 20X faster than a genetic formulation that generates equivalent solutions. We also demonstrate the effectiveness of our approach by incorporating the generated ISEs in the cycle-accurate SimpleScalar simulator. The average speedup on the selected benchmarks increases from 1.4X to 2.8X when the ISE identification process goes beyond memory barriers. Furthermore\, we show a concomitant reduction in energy consumption as a result of reduced cache pollution. In addition to analytical and simulation-based evaluation of the identified ISEs\, we implement our approach in a realistic hardware-software system that allows us to comprehensively study the effect of ISEs on performance\, energy\, power\, and code size using our interface-aware processor customization methodology. Our experiments on a Xilinx Virtex II board—employing the Microblaze soft-core as an extensible processor—show a simultaneous increase in performance\, and reduction in code size\, energy and power consumption with the incorporation of the AFU in the Microblaze soft-core processor.
URL:https://www.cecs.uci.edu/event/acceleration-beyond-memory-barriers-in-is-extensible-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060216T150000
DTEND;TZID=America/Los_Angeles:20060216T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14294-1140102000-1140105600@www.cecs.uci.edu
SUMMARY:Kilo-Instruction Processors: Overcoming the Memory Wall
DESCRIPTION:Kilo-Instruction Processors: Overcoming the Memory Wall\n\n\n\n\nSpeaker\n\n\nProfessor Mateo Valero\nComputer Architecture Dep. of the Polytechnical University of Catalunia\nCatalunia\, Spain\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nComputer Science 432\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFebruary 16\, 2006\nRefreshments at 10:30am\, followed by Lecture\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nToday’s systems have a very large and growing gap between processor and (DRAM) memory speeds\, which results in very long memory latency and loss of performance. Many different techniques have been proposed to address this problem: cache memories\, prefetching and other latency hiding techniques\, and multithreading\, to name a few. We proposed a different approach to solving this problem: a new type of out-of-order superscalar processor called the Kilo-Instruction Processor. Our design can have thousands of in-flight instructions using a scalable multi-check pointing mechanism. This allows memory access to be overlapped with the execution of a large number of other instructions and significantly improves performance. Kilo-Instruction Processors also offer advantages in multiprocessor systems\, where the average memory latency is even longer. They enable implementation of other very desirable features via their check-pointing mechanism. For example\, we can implement a multiprocessor transactional memory in hardware using checkpoints\, which enables an effective implementation of sequential consistency. This talk will describe the main ideas of our work on Kilo-instruction processors\, efficient\nimplementation options for this type of processors\, and their use in the design of multiprocessor systems.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nMateo Valero obtained his PhD at UPC in 1980. He is a Professor in the Computer Architecture Department of the Polytechnical University of Catalunia (UPC) in Spain and the director of the Barcelona Supercomputing Center\, the National Supercomputing Center of Spain. His research interests are in the area of high performance computer architecture. He has published over 400 papers in this field. Dr. Valero is a Fellow of the IEEE\, an Intel Distinguished Research Fellow and a Fellow of the ACM. He is a Correspondent Academic Member of the Spanish Royal Academy of Sciences. He is a winner of the “King Jaime I” award by the Generalitat Valenciana and the Spanish national award “Julio Rey Pastor” for his research in IT technologies. He is very proud that his home town of Alfamen named its Public College after him.
URL:https://www.cecs.uci.edu/event/kilo-instruction-processors-overcoming-the-memory-wall/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060207T190000
DTEND;TZID=America/Los_Angeles:20060207T190000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14200-1139338800-1139338800@www.cecs.uci.edu
SUMMARY:Professor Daniel Gajski Receives Honorary Doctorate
DESCRIPTION:Professor Daniel Gajski has been presented with an Honorary Doctorate from the University of Oldenburg\, Germany in recognition of his contributions in the areas of Embedded Systems and Design Science. In the early 1980s\, Dr. Gajski invented key concepts for the design of custom processors which are now widely used in the EDA industry. Later\, he made seminal contributions for the synthesis and verification of multi-processor embedded systems. Dr. Gajski is currently the Henry Samueli “Turing” Endowed Chair and Director of the Center for Embedded Computer Systems at the University of California\, Irvine.
URL:https://www.cecs.uci.edu/event/professor-daniel-gajski-receives-honorary-doctorate/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060201T150000
DTEND;TZID=America/Los_Angeles:20060201T160000
DTSTAMP:20231011T184446Z
CREATED:20231011T184446Z
LAST-MODIFIED:20231011T184446Z
UID:14338-1138806000-1138809600@www.cecs.uci.edu
SUMMARY:Compiler-in-the-Loop Exploration of Programmable Embedded Systems
DESCRIPTION:Compiler-in-the-Loop Exploration of Programmable Embedded Systems\nby Aviral Shrivastava \nEmbedded Systems are characterized by strict\, multi-dimensional design constraints such as power\, performance\, and time-to-market. Increasingly\, embedded processors are being employed for the flexibility of programmable solutions for embedded systems. However\, in order to satisfy all the design constraints simultaneously\, such embedded processors use many idiosyncratic architectural features (e.g.\, partial register renaming and partial bypassing)\, which in turn complicates the task of efficient software generation for the embedded processors. \nThe challenge in developing compilers for embedded processors is not only in developing compiler technology to exploit the idiosyncratic design feature\, but also to perofrm the required analysis in the limited resources present in embedded systems. When the compiler is able to exploit the idiosyncratic design feature\, it often has significant impact on the overall system characteristics. In such cases\, the compiler effects cannot be ignored while searching for the optimal processor design. Traditionally exploration to find an optimal processor is performed by simulating the same application binary over different processor variations. The variation that faresbest on the cost metric is chosen. Compiler effects in such an exploration scheme are typically accounted for\, using ad-hoc methods\, like hand-tuning the application binary\, or scaling the simluation results. Such ad-hoc methods miss many interesting design options\, and may even result in incorrect decisions being made during architectural exploration. \nMy thesis proposes a Compiler-in-the-Loop (CIL) Design Space Exploration (DSE) methodology to systematically include compiler effects in the search for an optimal embedded processor. In this talk I will demonstrate the need and usefulness of CIL DSE at several levels of design abstractions: the micro-architectural level\, the architectural level\, memory level\, and at the processor-memory-interface level. The CIL DSE approach results in a more meaningful exploration of the design space\, and allows embedded system designers to efficiently evaluate architectural options with respect to system constraints quickly\, reliably and early in the design process.
URL:https://www.cecs.uci.edu/event/compiler-in-the-loop-exploration-of-programmable-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060124T170000
DTEND;TZID=America/Los_Angeles:20060124T170000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14202-1138122000-1138122000@www.cecs.uci.edu
SUMMARY:Sudeep Pasricha and Professor Nikil Dutt Receive Best Paper Award
DESCRIPTION:Graduate student Sudeep Pasricha and Professor Nikil Dutt\, proudly receive their Best Paper Award at the Asia and South Pacific Design Automation Conference 2006 (ASPDAC 2006) which took place in Yokohama\, Japan on January 24\, 2006. Their award winning technical paper is entitled “Constraint-driven Bus Matrix Synthesis for MPSoC.”download pdf
URL:https://www.cecs.uci.edu/event/sudeep-pasricha-and-professor-nikil-dutt-receive-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20051209T150000
DTEND;TZID=America/Los_Angeles:20051209T160000
DTSTAMP:20231011T190252Z
CREATED:20231011T190252Z
LAST-MODIFIED:20231011T190252Z
UID:14380-1134140400-1134144000@www.cecs.uci.edu
SUMMARY:CECS Holiday Gathering
DESCRIPTION:
URL:https://www.cecs.uci.edu/event/cecs-holiday-gathering/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20051202T150000
DTEND;TZID=America/Los_Angeles:20051202T160000
DTSTAMP:20231011T184446Z
CREATED:20231011T184446Z
LAST-MODIFIED:20231011T184446Z
UID:14339-1133535600-1133539200@www.cecs.uci.edu
SUMMARY:Functional Verification of System Level Model Refinements
DESCRIPTION:Functional Verification of System Level Model Refinements\nby Samar Abdi \nWith continuous improvement in process technology\, designers have more resources than ever available for implementing their systems. As applications become larger\, the modeling abstraction has to rise to keep the complexity manageable. This has given rise to modeling at abstractions above the register transfer and cycle accurate levels. Verification becomes an even greater challenge as designers try to develop more models to evaluate their implementation choices. In this dissertation we present our verification strategy to alleviate the problems resulting from the move to system level. We argue our case for a system level modeling and verification methodology where detailed models are refined from abstract models. The models are represented formally using Model Algebra and the refinements are proved to be functionality preserving\, using the rules of Model Algebra. We define the objects and composition rules of Model Algebra and show how system level models are represented as expressions in this formalism. The formal execution semantics of such models are discussed and a notion for functional equivalence of models is also presented. We then define transformation rules that syntactically modify a model algebraic expression\, while keeping its functionality intact. Then we present key refinements that are commonly encountered in system level design and prove the correctness of those refinements using the transformation rules of Model Algebra. As a proof of concept\, we implemented a tool that automatically checks if the refinements were performed correctly on SpecC models. As a result\, the designer needs to perform the costly and time consuming property verification on the first model only. All step wise refinements from the original model are proven to produce functionally equivalent models.
URL:https://www.cecs.uci.edu/event/functional-verification-of-system-level-model-refinements/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20051202T150000
DTEND;TZID=America/Los_Angeles:20051202T160000
DTSTAMP:20231011T184446Z
CREATED:20231011T184446Z
LAST-MODIFIED:20231011T184446Z
UID:14340-1133535600-1133539200@www.cecs.uci.edu
SUMMARY:Cache Power-Performance Optimization
DESCRIPTION:Cache Power-Performance Optimization\nby Dan Nicolaescu \nThe speed gap between the memory and processor continues to increase. As a consequence the cache system becomes more and more important for bridging this speed gap in order to obtain good performance. As the cache size and associativity increase\, its energy consumption becomes a higher part of the total processor energy budget. The high energy consumption is a major problem for current processors\, and given the predictions for the semiconductor industry\, it will further increase in the future. The traditional way of reducing energy consumption through decreasing the feature size is running out of steam. Therefore solutions need to be found at other levels in the design hierarchy. This dissertation studies the performance and energy consumption of the cache system and proposes and proves effective low complexity\, yet highly effective solutions for reducing the cache energy consumption and increasing the processor performance at the architectural level. \nThe cache energy consumption can be reduced by reducing the number of cache accesses. This can be achieved by using a new architectural component called Cached Load/Store Queue which also allows for a performance improvement by reducing average cache access latency. The energy consumption of highly associative CAM based caches can be improved by using a predictor and changing the way the access is performed. The Way Cache is a novel component that can be used to improve the dynamic and static energy consumption of associative caches by reducing the number of tag and data ways accessed for each cache access.
URL:https://www.cecs.uci.edu/event/cache-power-performance-optimization/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20051115T150000
DTEND;TZID=America/Los_Angeles:20051115T160000
DTSTAMP:20231011T192654Z
CREATED:20231011T180420Z
LAST-MODIFIED:20231011T192654Z
UID:14232-1132066800-1132070400@www.cecs.uci.edu
SUMMARY:PIE: Programmable Internet Environment
DESCRIPTION:Abstract \nPIE: Programmable Internet Environment\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/pie-programmable-internet-environment/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20051014T150000
DTEND;TZID=America/Los_Angeles:20051014T160000
DTSTAMP:20231011T190252Z
CREATED:20231011T190252Z
LAST-MODIFIED:20231011T190252Z
UID:14381-1129302000-1129305600@www.cecs.uci.edu
SUMMARY:CECS Potluck Party
DESCRIPTION:click on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/cecs-potluck-party/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050617T150000
DTEND;TZID=America/Los_Angeles:20050617T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180434Z
LAST-MODIFIED:20231011T192041Z
UID:14233-1119020400-1119024000@www.cecs.uci.edu
SUMMARY:Cutpoints for Formal Equivalence Verification of Embedded Software
DESCRIPTION:Cutpoints for Formal Equivalence Verification of Embedded Software\n\n\n\n\nSpeaker\n\n\nDr. Alan Hu\nDepartment of Computer Science\nUniversity of British Colombia\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 432\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 17 \, 2005\nTalk begins at 9:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nLike hardware\, embedded software faces stringent design constraints\, undergoes extremely aggressive optimization\, and therefore has a similar need for verifying the functional equivalence of two versions of a design\, e.g.\, before and after an optimization. The concept of cutpoints was a breakthrough in the formal equivalence verification of combinational circuits and is the key enabling technology behind its successful commercialization. We introduce an analogous idea for formally verifying the equivalence of structurally similar\, “combinational” software\, i.e.\, software routines that compute a result and return/terminate\, rather than executing indefinitely. We have implemented a proof-of-concept cutpoint approach in our prototype verification tool for the TI C6x family of VLIW DSPs\, and our experiments show large improvements in runtime and memory usage.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nAlan Hu received his BS and PhD degrees from Stanford University . He is an associate professor and associate head of the Department of Computer Science at the University of British Columbia . For the past15 years\, his main research focus has been automated\, practical techniques for formal verification. He has served on the program committees of most major CAD and formal verification conferences\, and chaired or co-chaired CAV (1998)\, HLDVT (2003)\, and FMCAD (2004). He was also a Technical Working Group Key Contributor on the 2001 International Technology Roadmap for Semiconductors.
URL:https://www.cecs.uci.edu/event/cutpoints-for-formal-equivalence-verification-of-embedded-software/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050614T160000
DTEND;TZID=America/Los_Angeles:20050614T160000
DTSTAMP:20231011T180133Z
CREATED:20231011T180133Z
LAST-MODIFIED:20231011T180133Z
UID:14203-1118764800-1118764800@www.cecs.uci.edu
SUMMARY:Payam Heydari Receives Best Paper Award
DESCRIPTION:Payam Heydari\, Assistant Professor ofthe Department of Electrical Engineering and Computer Science\, won the 2005 Darlington Best Paper Award from the IEEE Circuits and Systems Society for his journal paper entitled “Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise” published in the IEEE Transactions on Circuits and Systems \, vol. 51\, no. 12\, pages 2404-2416\, December 2004.\nThe Darlington Award is given in honor of Dr. Sidney Darlington\, a Bell Labs scientist who pioneered the design of electronic circuits and systems. The award is given in recognition of the best paper bridging the gap between theory and practice published in IEEE Transactions on Circuits and Systems \, which is published in two separate monthly volumes over the past 2 years. The award is based on the general quality\, originality\, contributions\, subject matter and timeliness. Over 900 papers\, all of which have been peer-reviewed and published during the last two years\, were eligible to receive the award. \nPayam Heydari is the sole author of this paper and the youngest faculty among past recipients of this award. He will receive the award and a cash prize at the opening session of the 2005 Design Automation Conference on June 14 th \, 2005 in Anaheim Convention Center \, California . \nThe Circuits and Systems Society is one of the largest societies within the Institute for Electronics and Electrical Engineers\, commonly referred to as IEEE.
URL:https://www.cecs.uci.edu/event/payam-heydari-receives-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050609T150000
DTEND;TZID=America/Los_Angeles:20050609T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14295-1118329200-1118332800@www.cecs.uci.edu
SUMMARY:VLSI Design Methodologies Considering Fabrication Variability
DESCRIPTION:VLSI Design Methodologies Considering Fabrication Variability\n\n\n\n\nSpeaker\n\n\nProfessor Shrivastava \nDepartment of Electrical and Computer Engineering\nUniversity of Maryland\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Elaheh Bozorgzadeh\neli@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 127\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 9\, 2005\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn the past few years\, it has become clear that fabrication variability is one of the most important challenge that needs to be addressed for keeping the semiconductor industry profitable. Fabrication variability imposes an underlying uncertainty on the design process of VLSI chips making several parameters random. Therefore\, the old way of doing design needs to be overhauled for considering this randomness. This implies that VLSI CAD needs to incorporate probabilistic models for capturing uncertainty and stochastic optimization for controlling the design decision variables. Several challenges need to be addressed before this is made possible…\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nAnkur Srivastava received the B.S. degree from the Indian Institute of Technology\, Delhi\, the M.S. degree from Northwestern University\, Evanston\, IL\, and the Ph.D. degree from the University of California Los Angeles (UCLA) in 1998\, 2000\, and 2002. Since fall 2002 he has been an Assistant Professor with the University of Maryland\, College Park. His research interests include all aspects of design automation including logic and high-level synthesis\, low-power issues and predictability\, and low-power issues pertaining to sensor networks. Dr. Srivastava received the outstanding Ph.D. Award from the Computer Science Department of UCLA in 2002. He is a member of ACM and IEEE.
URL:https://www.cecs.uci.edu/event/vlsi-design-methodologies-considering-fabrication-variability/
CATEGORIES:Seminars at CECS
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