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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050414T150000
DTEND;TZID=America/Los_Angeles:20050414T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14297-1113490800-1113494400@www.cecs.uci.edu
SUMMARY:Multiple Objective Behavioural Synthesis
DESCRIPTION:Multiple Objective Behavioural Synthesis\n\n\n\n\nSpeaker\n\n\nProfessor Zwolinski \nSchool of Electronics and Computer Science\nUniversity of Southampton\, UK\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Ian Harris\nharris@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nICS 432\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 14\, 2005\nRefreshments at 10:30am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nFor a number of years\, the Electronic Systems Design Group in the School of Electronics and Computer Science\, University of Southampton has been working on a behavioral synthesis tool – MOODS (Multiple Objective Optimization in control and Data path Synthesis). Unlike many other high-level synthesis tools\, MOODS optimizes designs by a series of small\, localized transforms to the data and control paths. This approach has some significant advantages over other techniques\, most notably that a number of different objectives can be specified\, without knowing the relationship between those objectives. Initially\, optimization was performed in terms of area and critical path delay\, but this has been extended (through a succession of PhD projects) to include power\, testability and reconfigurability. In this talk\, the techniques used and results achieved will be discussed\, together with future research directions.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nDr. Mark Zwolinski is a Reader (Associate Professor) in the School of\nElectronics and Computer Science at the University of Southampton UK. He\ncompleted his BS in Electronic Engineering and PhD in Electronics at\nthe University of Southampton\, too. He was appointed as a lecturer\n(Assistant Professor) in 1990. His PhD was on the topic of electronic\ncircuit simulation\, but he has since developed research interests in\nanalog and mixed-signal test\, high-level synthesis and verification. He\nhas published over 100 refereed conference and journal papers and is the\nauthor of two books.
URL:https://www.cecs.uci.edu/event/multiple-objective-behavioural-synthesis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050320T150000
DTEND;TZID=America/Los_Angeles:20050320T160000
DTSTAMP:20231011T193551Z
CREATED:20231011T185235Z
LAST-MODIFIED:20231011T193551Z
UID:14361-1111330800-1111334400@www.cecs.uci.edu
SUMMARY:B#: A Battery Emulator and Power-Profiling Instrument
DESCRIPTION:Release Date: March\, 2005Download pdf: http://www.ece.uci.edu/~chou/battDT-layout.pdf \nB# (B sharp) is a programmable power supply that emulates battery behavior. It measures current load\, calls a battery simulation program to compute voltage in real time\, and controls a linear regulator to mimic a battery’s voltage output. The instrument enables validation of battery-aware power optimization techniques with accurate\, controllable\, reproducible results.
URL:https://www.cecs.uci.edu/event/b-a-battery-emulator-and-power-profiling-instrument/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050315T150000
DTEND;TZID=America/Los_Angeles:20050315T150000
DTSTAMP:20231011T180133Z
CREATED:20231011T180133Z
LAST-MODIFIED:20231011T180133Z
UID:14204-1110898800-1110898800@www.cecs.uci.edu
SUMMARY:Henry T. Nicholas\, III Research Fellowships
DESCRIPTION:The Center for Embedded Computer Systems (CECS) at the University of California\, Irvine (UCI) announces that it is receiving graduate student applications for two Henry T. Nicholas\, III Research Fellowships for the 2005-2006 academic year. These research fellowships will provide a graduate student stipend plus the payment of tuition and fees for one academic year including summer support. Applicants must satisfy the following requirements: \n\nApplicant must have passed PhD examination at University of California\, Irvine\nApplicant’s thesis advisor must be a member of the Center for Embedded Computer Systems\nApplicant’s should submit a 2 page research description to include: succinct discussion of interdisciplinary research novelty\, proposed extensions of interdisciplinary research\, and be able to demonstrate prototype or proof of concept\nResearch projects described on the CECS web site will be given priority\n\nApplications must be submitted to the Selection Committee Chair by March 15\, 2005: \nRobert P. Larsen\, Chair\nAssociate Director\nCenter for Embedded Computer Systems\nUniversity of California\, Irvine \nThe two Henry T. Nicholas\, III Research Fellows will be announced May 15\, 2005.
URL:https://www.cecs.uci.edu/event/henry-t-nicholas-iii-research-fellowships/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050207T140000
DTEND;TZID=America/Los_Angeles:20050207T140000
DTSTAMP:20231011T180133Z
CREATED:20231011T180133Z
LAST-MODIFIED:20231011T180133Z
UID:14205-1107784800-1107784800@www.cecs.uci.edu
SUMMARY:Chou & Heydari Win NSF CAREER Awards
DESCRIPTION: \nProfessors Pai H. Chou and Payam Heydari\, Department of Electrical Engineering and Computer Science at the Henry Samueli School of Engineering\, have been named recipients of the National Science Foundation (NSF) Faculty Early Career Development (CAREER) Award. Professor Chou’s research proposal was titled Design Optimization and Quantitative Evaluation of Wireless Embedded Sensing Systems. Professor Heydari’s research proposal was titled Analysis and Design of Silicon-Based Performance-Optimized Integrated Circuits for High-Frequency Wideband Wireless Communication Systems. Each professor received an award of $400\,000 covering a 5 year duration. \nThe CAREER award is the NSF’s most prestigious award to new faculty members. The CAREER program recognizes and supports the early career-development of those teacher-scholars who are most likely to become academic leaders of the 21 st century. CAREER awardees are selected on the basis of creative\, career-development plans that effectively integrate research and education within the context of the mission of their institution. The CAREER award plans should build a firm foundation for a lifetime of integrated contributions to research and education. \nCECS extends congratulations to Professor Chou and Professor Heydari on receiving this prestigious NSF CAREER award and the accompanying recognition. \n  \n\nProfessor Payam Heydari at his reseach station.\nview larger image \n\nA screenshot of some of Professor Heydari’s research:\na novel broadband non-uniform distributed amplifier.\nview larger image \n\nProfessor Masanobu Shinozuka and Professor Pai H. Chou\npresenting a piece from their network vibration sensor network research.\nview larger image
URL:https://www.cecs.uci.edu/event/chou-heydari-win-nsf-career-awards/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050125T130000
DTEND;TZID=America/Los_Angeles:20050125T130000
DTSTAMP:20231011T180133Z
CREATED:20231011T180133Z
LAST-MODIFIED:20231011T180133Z
UID:14206-1106658000-1106658000@www.cecs.uci.edu
SUMMARY:Dr. Mishra wins 2004 EDAA Outstanding Dissertation Award
DESCRIPTION:Dr. Prabhat Mishra won the EDAA outstanding dissertation award for the topic “New Directions in Embedded System Design Automation.” His paper is titled\, “Specification-Driven Validation of Programmable Embedded Systems.”
URL:https://www.cecs.uci.edu/event/dr-mishra-wins-2004-edaa-outstanding-dissertation-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20041209T150000
DTEND;TZID=America/Los_Angeles:20041209T160000
DTSTAMP:20231011T183336Z
CREATED:20231011T183336Z
LAST-MODIFIED:20231011T183336Z
UID:14298-1102604400-1102608000@www.cecs.uci.edu
SUMMARY:Technological Challenges to Computer Architecture Innovation
DESCRIPTION:Video Introduction (Windows Media Player) \n  \nTechnological Challenges to Computer Architecture Innovation\n\n\n\n\nSpeaker\n\n\nDr. Faye Briggs\nIntel Corporation\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nAlex Veidenbaum\nalexv@cecs.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 9 \, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nComputer architecture has evolved significantly over the last 30 years. With a major dependence on technology\, we have been able to keep up with Moore’s law. We are beginning to face enormous constraints in technology\, and these create significant challenges for computer architecture advancement. The goal of this talk is to provide an overview of many of the variables and constraints that will challenge traditional computer architecture innovations. The intent is to highlight these challenges with the expectation of triggering more research and potential breadkthroughs to sustain innovation in computer architecture.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\n \nDr. Faye Briggs is Sr. Principal Engineer and Director of Platform Performance Architecture\, Enterprise Products Group at Intel Corporation. Dr. Briggs led the architecture & engineering teams that develop the Intel AE 870 for 2-16P Itanium AE servers. He was a co-founder and CTO of Axil Computers. While at Sun Microsystems\, he coarchitected the first SPARC-V8\, and led the architecture team to develop multiprocessor SPARCserver2000. Faye Briggs also served on the faculties of Purdue and Rice Universities. He has co-authored a popular textbook on Computer Architecture and Parallel Processing\, and published over 40 technical papers. He received his MSEE from Stanford\, and Ph.D. ECE from the University of Illinois. \n\n\n\n\n\nTechnological Challenges to Computer Architecture Innovation\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/technological-challenges-to-computer-architecture-innovation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20041025T150000
DTEND;TZID=America/Los_Angeles:20041025T160000
DTSTAMP:20231011T184638Z
CREATED:20231011T184638Z
LAST-MODIFIED:20231011T184638Z
UID:14347-1098716400-1098720000@www.cecs.uci.edu
SUMMARY:Extreme Makeover of Design Automation
DESCRIPTION:Extreme Makeover of Design Automation \n\n\n\n\nSpeaker\n\n\nProfessor Gajski \nElectrical Engineering and Computer Science\nUniversity of California at Irvine\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nUniversity Club\, UC Irvine\n\n\n\n \n\n\n \n\n\n\nDate & Time\n\n\nOctober 25\, 2004\nSocial Hour at 6:00pm\, Presentation begins at 7:00pm\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nWith complexities of Systems-on-Chip rising almost daily\, the design community has been searching for new vision that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution\, such as increasing levels of abstraction\, introducing variety of IPs or offering new design languages will not solve the problem but only prolong the present status of inefficiency and confusion. What is needed is a drastic change in design automation for complex systems that consist of software and hardware. In order to design such systems efficiently\, we need a new approach with a new design flow\, with new models with well defined semantics and a new formalism that will support system synthesis and verification of software and hardware. \nIn order to find the solution\, we will look first at the system gap between SW and HW designs and derive requirements for the design flow that includes software as well as hardware. In order to enable new EDA tools for model generation\, simulation\, synthesis and verification\, the design flow has to be well defined with unique abstraction levels\, model semantics and model transformations corresponding to design decisions made by the designers. We will introduce the concept of model algebra that supports this approach and can serve as an enabler for the extreme makeover of EDA. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of complex systems to the basic principles of design science only.\n\n\n\n \n\n\n \n\n\n\nBiography\n\n\n  \n\n \n\nProfessor Gajski directs the UCI Center for Embedded Computer Systems\, with a research mission to incorporate embedded systems into automotive\, communications\, and medical applications. He has authored over 300 papers and seven textbooks\, including Principles of Digital Design (Englewood Cliffs\, NJ: Prentice Hall\, 1997) that has been translated into several languages. \nHe holds Dipl. Ing. and M.S. degrees in electrical engineering from the University of Zagreb\, Croatia\, and a doctoral degree in computer and information sciences from the University of Pennsylvania\, Philadelphia. After 10 years as Professor at University of Illinois he has joined UCI\, where he presently holds The Henry Samueli Endowed Chair in Computer System Design.
URL:https://www.cecs.uci.edu/event/extreme-makeover-of-design-automation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20041004T120000
DTEND;TZID=America/Los_Angeles:20041004T120000
DTSTAMP:20231011T180133Z
CREATED:20231011T180133Z
LAST-MODIFIED:20231011T180133Z
UID:14207-1096891200-1096891200@www.cecs.uci.edu
SUMMARY:Dutt\, Reshadi\, Mishra and Bansal Receive Best Paper Award at CODES+ISSS 2003
DESCRIPTION:Professor Nikil Dutt and graduate students Mehrdad Reshadi\, Prabhat Mishra\, and Nikhil Bansal\, pictured below\, proudly display their Best Paper Awards received at the First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (Codes + ISSS 2003) held at the Marriott Hotel and Tennis Club\, Newport Beach\, CA on October 1-3\, 2003. Their award winning technical paper was titled An Efficient Retargetable Framework for Instruction-Set Simulation. They also received a $1\,000 award in addition to their plaques. \n\nview larger image
URL:https://www.cecs.uci.edu/event/dutt-reshadi-mishra-and-bansal-receive-best-paper-award-at-codesisss-2003/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040831T150000
DTEND;TZID=America/Los_Angeles:20040831T160000
DTSTAMP:20231011T190252Z
CREATED:20231011T190252Z
LAST-MODIFIED:20231011T190252Z
UID:14382-1093964400-1093968000@www.cecs.uci.edu
SUMMARY:Prof. Dutt Presents Keynote Speech
DESCRIPTION:Professor Nikil Dutt presented the Keynote Speech at the EUROMICRO Symposium on Digital System Design. The symposium was held at Rennes\, France.EUROMICRO Web Site
URL:https://www.cecs.uci.edu/event/prof-dutt-presents-keynote-speech/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040817T150000
DTEND;TZID=America/Los_Angeles:20040817T160000
DTSTAMP:20231011T183336Z
CREATED:20231011T183336Z
LAST-MODIFIED:20231011T183336Z
UID:14299-1092754800-1092758400@www.cecs.uci.edu
SUMMARY:Taming Pointers – A Symbolic Approach
DESCRIPTION:Taming Pointers – A Symbolic Approach\n\n\n\n\nSpeaker\n\n\nProfessor Jianwen Zhu \nDepartment of Electrical and Computer Engineering\nUniversity of Toronto\, Canada\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Daniel Gajski\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nTuesday\, August 17\, 2004\nRefreshments at 2:30pm\, Seminar begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe silicon real estate available in systems-on-chip (SOC) has given hope for the massive-parallel\, high-performance implementation of complex applications. However\, new efforts in silicon compilers that synthesize applications in C into SOC cannot dodge an old problem\, called pointer analysis\, which has been actively pursued in the programming language and compiler community for two decades. The challenges of precise pointer analysis stem from the need to explore an exponential number of program execution paths\, and the need to maintain program state for every program point under all such paths. In this talk\, I will introduce a new method for constructing scalable graph algorithms (ICCAD’02\, PLDI’04)\, called superposition\, which solves different problem instances in an aggregate fashion. Applying this method to pointer analysis\, different program states under different execution paths are combined into a single Boolean function\, and solved together using the efficient\, BDD-based image computation operator developed by the formal verification community. Experimental results show that context-sensitive\, flow-insensitive analysis on programs with billions of different calling paths can be performed\, and benchmarks as large as GCC (200KLOC) can be completed in seconds. The subject of this talk can be of interest to researchers in CAD\, compiler\, software engineering and security.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\n \nJianwen Zhu received the B.S degree in electrical engineering from the Tsinghua University\, Beijing\, China\, and the M.S. and Ph.D. degrees in computer science from the University of California\, Irvine\, in 1993\, 1996 and 1999 respectively. He is currently an assistant professor in the Department of Electrical and Computer Engineering\, University of Toronto\, Canada. He is the coauthor of the book SpecC: Specification Language and Methodology (Kluwer-Academic\, 2000). His research interest includes hardware/software codesign\, high-level synthesis for high-performance circuits and retargetable compilation. \n\n\n\n\n\nTaming Pointers – A Symbolic Approach\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/taming-pointers-a-symbolic-approach/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040808T150000
DTEND;TZID=America/Los_Angeles:20040808T160000
DTSTAMP:20231011T190302Z
CREATED:20231011T190302Z
LAST-MODIFIED:20231011T190302Z
UID:14383-1091977200-1091980800@www.cecs.uci.edu
SUMMARY:CECS ISLPED Open House
DESCRIPTION:
URL:https://www.cecs.uci.edu/event/cecs-islped-open-house/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040630T150000
DTEND;TZID=America/Los_Angeles:20040630T160000
DTSTAMP:20231011T190302Z
CREATED:20231011T190302Z
LAST-MODIFIED:20231011T190302Z
UID:14384-1088607600-1088611200@www.cecs.uci.edu
SUMMARY:CECS End of the Year BBQ
DESCRIPTION:click on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/cecs-end-of-the-year-bbq/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040604T110000
DTEND;TZID=America/Los_Angeles:20040604T120000
DTSTAMP:20231011T192748Z
CREATED:20231011T180419Z
LAST-MODIFIED:20231011T192748Z
UID:14229-1086346800-1086350400@www.cecs.uci.edu
SUMMARY:Practical Considerations for Power-Aware Real-Time Scheduling
DESCRIPTION:Lecture Slides \nPractical Considerations for Power-Aware Real-Time Scheduling\n\n\n\n\nSpeaker\n\n\nProfessor Sharon Hu\nDepartment of Computer Science and Engineering\nUniversity of Notre Dame\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 4 \, 2004\nRefreshments at 10:30am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nReal-time embedded systems are prevalent in many applications such as computing and communication appliances\, various transportation vehicles\, and medical instruments. A common feature of these systems is that their performance is largely dependent on how well the timing constraints are met. Besides timing requirements\, power consumption is becoming a major consideration in real-time embedded system design as VLSI technology continues its remarkable advances. Techniques to minimize power/energy consumption while satisfying the stringent timing constraints are critical to successful deployment of such systems.The focus of this talk is on the scheduling aspect of hard real-time systems implemented on processors with dynamic voltage scaling (DVS) capabilities. Scheduling to guarantee real-time demands can be a difficult problem. DVS processors introduce a new dimension to the problem. Including realistic considerations\, such as the overhead of transitioning from one voltage level\nto another\, brings yet more challenges. Research results in this area have largely ignored the limitations of practical DVS processors. This talk will discuss several recent results on dealing with non-ideal features of DVS processors for hard real-time systems.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nXiaobo Sharon Hu is an associate professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana. She also holds a joint appointment in the department of Electrical Engineering at the same university. Her research interests include hardware-software codesign\, real-time embedded systems\, low-power system design\, VLSI design algorithms\, and computer-aided radiation treatment planning. She has published more than 80 papers in these areas and obtained a number research grants from both government and private industry. She was the Technical Program Co-Chair of the 9th International Symposium on Hardware/Software Codesign (CODES’2001) and the General Co-Chair of the same conference in 2002. She has been invited to serve on the program committees of a number of conferences in the electronic design automation field such as DAC\, ICCAD\, DATE\, ICCD\, CODES\, CASES\, etc. In 1997\, she received the NSF’s Faculty Early Career Development (CAREER) Award. A paper co-authored by Sharon Hu and her student received the Best Paper Award from the 38th ACM/IEEE Design Automation Conference in 2001.\n\n\n\nPractical Considerations for Power-Aware Real-Time Scheduling\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/practical-considerations-for-power-aware-real-time-scheduling/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040601T150000
DTEND;TZID=America/Los_Angeles:20040601T160000
DTSTAMP:20231011T190302Z
CREATED:20231011T190302Z
LAST-MODIFIED:20231011T190302Z
UID:14385-1086102000-1086105600@www.cecs.uci.edu
SUMMARY:Prof. Gajski Receives Mentor Award
DESCRIPTION:Professor Daniel D. Gajski received the first ever 2004 Graduate Mentor of the Year Award from the Donald Bren School of Information and Computer Sciences. This award was given in recognition of his devotion to graduating 4 PhD students in 2004 and 4 PhD students in 2003.
URL:https://www.cecs.uci.edu/event/prof-gajski-receives-mentor-award/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040524T150000
DTEND;TZID=America/Los_Angeles:20040524T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T180420Z
LAST-MODIFIED:20231011T193148Z
UID:14230-1085410800-1085414400@www.cecs.uci.edu
SUMMARY:Towards Better Compilers & Bug Finding for Sensor Networks
DESCRIPTION:Lecture Slides \nTowards Better Compilers & Bug Finding for Sensor Networks\n\n\n\n\nSpeaker\n\n\nProfessor Jens Palsberg\nComputer Science Department\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 24\, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nSensor-network programmers face tough challenges. They must maximize the network life time while managing resource tradeoffs among energy consumption\, stack space\, code size\, response time\, and throughput. For example\, a programmer can choose to inline a call and thereby decrease the response time and decrease the stack space\, but also increase the code size. \nAdditionally\, a programmer can choose to do more computation locally\non a sensor node and thereby decrease communication and the energy consumption\, but also increase the code size. Such tradeoffs make programming difficult and error prone. Most current compilers don’t help with making resource tradeoffs and there are few tools for finding resource bugs such as stack overflow. Can we design better compilers and bug-finding tools that will help out sensor-network programmers? \nIn this talk Jens Palsberg will examine the state of the art (TinyOS\, NesC\, TOSSIM)\, survey recent results on stack analysis and deadline analysis\, and give an overview of the UCLA compiler group’s project on building compiler and bug-finding tools for NesC and the Berkeley Mote sensor node platform.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nJens Palsberg is a Professor of Computer Science at UCLA. His research interests span the areas of compilers\, embedded systems\, programming languages\, software engineering\, and information security. He has authored over 70 technical papers\, co-authored the book Object-Oriented Type Systems\, and co-authored the 2002 revision of Appel’s textbook on Modern Compiler Implementation in Java. He is the recipient of National Science Foundation CAREER and ITR awards\, a Purdue University Faculty Scholar award\, and an Okawa Foundation research award. His research has also been supported by DARPA\, IBM\, Intel\, and British Telecom. He is an associate editor of ACM Transactions of Programming Languages and Systems\, a member of the editorial board of Information and Computation\, and a former member of the editorial board of IEEE Transactions on Software Engineering. He is serving as the general chair of the ACM Symposium on Principles of Programming Languages in 2005.\n\n\n\nTowards Better Compilers & Bug Finding for Sensor Networks\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/towards-better-compilers-bug-finding-for-sensor-networks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040513T150000
DTEND;TZID=America/Los_Angeles:20040513T160000
DTSTAMP:20231011T192253Z
CREATED:20231011T180420Z
LAST-MODIFIED:20231011T192253Z
UID:14231-1084460400-1084464000@www.cecs.uci.edu
SUMMARY:Frequent Value Locality and its Applications
DESCRIPTION:Lecture Slides \nFrequent Value Locality and its Applications\n\n\n\n\nSpeaker\n\n\nProfessor Rajiv Gupta\nComputer Science Department\nUniversity of Arizona\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 13\, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nBy studying the behavior of programs in the SPEC95 benchmark suite we have observed the frequent value phenomenon according to which a few values appear very frequently in memory locations and are therefore involved in a large fraction of memory accesses. Moreover we have observed that the set of frequent values remains stable over the execution of the program and these values are distributed fairly uniformly across the memory. In addition to describing the frequent value phenomenon I will describe two applications of the phenomenon. In the first application\, by transmitting values belonging to a dynamically changing set of frequent values in encoded form\, we greatly reduce the switching activity on a CPU’s external data bus. In the second application\, by storing values belonging to a fixed set of frequent values in compressed encoded form\, we significantly reduce energy consumed by the data cache.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nRajiv Gupta is a Professor of Computer Science at The University of Arizona. His areas of research interest include profile guided code optimization and program analysis; software tools; and performance\, power\, and memory issues in superscalar and embedded processors. Rajiv has published over 170 articles in refereed conferences and journals\, he holds 7 US patents\, and has supervised 12 PhD dissertations. Papers coauthored by him have been selected for: inclusion in 20 Years of PLDI (1979-1999)\, distinguished paper award in ICSE 2003\, most original paper award in ICPP 2003\, and outstanding paper award in ICECCS 1996. Rajiv received the NSF’s Presidential Young Investigator Award in 1991. He served as the Program Chair for PLDI’03 and HPCA’03 conferences. He has also been appointed as the Co-General Chair for CGO’05 and the Program Chair for LCTES’05 conferences. He serves as an Associate Editor for ACM Transactions on Architecture and Code Optimization\, Parallel Computing journal\, and Journal of Embedded Computing.\n\n\n\nFrequent Value Locality and its Applications\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/frequent-value-locality-and-its-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040512T150000
DTEND;TZID=America/Los_Angeles:20040512T160000
DTSTAMP:20231011T190302Z
CREATED:20231011T190302Z
LAST-MODIFIED:20231011T190302Z
UID:14386-1084374000-1084377600@www.cecs.uci.edu
SUMMARY:Advancement to Candidacy
DESCRIPTION:Dr. Utpal Banerjee from Intel visited CECS for PhD student Arun Kejariwal’s Advancement to Candicacy event. Dr. Banerjee was on Arun’s advancement committee and will be on the thesis committee as well. \n\nkneeling: Arun Kejariwal  left to right: Professor Veidenbaum\, Dr. Banerjee\,\nProfessor Nicolau\, Professor Jenks\, Professor Gajski\, Professor Gaudiot\nview larger image
URL:https://www.cecs.uci.edu/event/advancement-to-candidacy/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040416T150000
DTEND;TZID=America/Los_Angeles:20040416T160000
DTSTAMP:20231011T184447Z
CREATED:20231011T184447Z
LAST-MODIFIED:20231011T184447Z
UID:14342-1082127600-1082131200@www.cecs.uci.edu
SUMMARY:Communication Synthesis for SoC
DESCRIPTION:Communication Synthesis for System on Chip\nby Dongwan Shin \nWith the ever increasing complexity of system level designs and the pressure of the time-to-market in the design of System-on-Chip (SoC)\, communication between components is becoming more and more important. Communication design for SoCs poses the unique challenges in order to cover a wide range of architectures while offering new opportunities for optimizations based on the application specific nature of system designs. In this thesis\, we propose a communication design methodology that enables rapid design space exploration in order to achieve the required productivity gains. We define communication abstraction layers\, corresponding design models and transformations which refine abstract message passing channels down to a cycle-accurate implementation. We also implemented automatic model generation tools which apply transformations to a model in order to represent and implement design decisions taken from the users or from automatic synthesis algorithms. The experimental results show the benefits of our methodology and demonstrate the effectiveness of our automatic model generation for communication synthesis.
URL:https://www.cecs.uci.edu/event/communication-synthesis-for-soc/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040416T150000
DTEND;TZID=America/Los_Angeles:20040416T160000
DTSTAMP:20231011T184446Z
CREATED:20231011T184446Z
LAST-MODIFIED:20231011T184446Z
UID:14341-1082127600-1082131200@www.cecs.uci.edu
SUMMARY:Modeling Flow for Automated System Design and Exploration
DESCRIPTION:Modeling Flow for Automated System Design and Exploration\nby Andreas Gerstlauer \nRaising the level of abstraction is widely seen as the solution for closing the productivity gap in the design of embedded computer systems and systems-on-chip (SoCs). However\, system design thus far suffers from a lack of rigorous\, structured\, and comprehensive design processes from abstract specification down to cycle-accurate implementation. \nIn order to provide an automated design process\, a well-defined design flow with clear and unambiguous abstraction levels\, models\, and transformations is required. The key to the success of this approach are properly defined design models. Arbitrary models without clear semantics do not enable synthesis and verification. In addition\, synthesis requires clear definitions of the target architecture and the set of synthesis steps to transform the input model into the target model. In this dissertation\, we define such input and target models\, a set of design steps\, design decisions\, model transformation\, and intermediate models that are necessary for an automated system design flow. \nThe design flow has been implemented in the form of an interactive system-on-chip design environment (SCE). Automating tedious and error-prone tasks while reaping human expertise and insight results in a flow with the necessary transparency\, controllability\, observability and productivity. As part of this work\, architecture\, organization\, tool flow\, design model management\, interfaces\, and databases of the design framework have been established. Models in the flow have been defined such that they can be automatically generated and model refinement tools have been integrated into the design environment. Finally\, a graphical user interface (GUI) has been developed that aids and steers the designer in the decision making process\, provides visualization of design models\, and supports interactive\, graphical decision entry for each design step. \nExperiments using the design environment prove the feasibility and effectiveness of a seamless\, comprehensive\, and automated design flow supporting rapid\, early design space exploration. Results obtained by applying the design flow to several industrial-strength examples show the tradeoffs and benefits of intermediate models at each step and demonstrate that required productivity gains can be achieved while supporting a wide range of realistic target implementations.
URL:https://www.cecs.uci.edu/event/modeling-flow-for-automated-system-design-and-exploration/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040402T150000
DTEND;TZID=America/Los_Angeles:20040402T160000
DTSTAMP:20231011T184637Z
CREATED:20231011T184637Z
LAST-MODIFIED:20231011T184637Z
UID:14343-1080918000-1080921600@www.cecs.uci.edu
SUMMARY:System-Level Automatic Model Refinement
DESCRIPTION:System-Level Automatic Model Refinement\nby Junyu Peng \nIn a system-level design methodology\, the system under design is represented by models at different abstraction levels. The design process is essentially a series of steps that gradually transform the most abstract specification model into a detailed implementation model. In practice\, all these models are written manually by designers. As the result\, the designers spend long time on this tedious and error-prone model-writing task. In addition\, it is not possible to verify the equivalence between the models written manually. In this dissertation we present our work on automatic model generation\, where models are generated automatically by tools rather than manually by designers. This kind of automation not only relieves designers from the mundane and time-consuming coding task but also makes it possible to formally verify the functional equivalence between models. \nThis dissertation in particular focuses on the architecture refinement\, which is aimed to automatically generate an architecture model from the input specification model after architecture exploration when architecture allocation and partitioning decisions are made. We approach the problem by first formally defining the semantics and styles of the input specification model and the output architecture model. Based on the differences between the input and output models\, we are able to define a refinement flow which consist of a series of formally-defined transformations. \nDistinguishing itself from other similar approaches\, our approach addresses the quality issue of the automatically generated models. We defined a set of quality metrics that are relevant to architecture refinement. Then we devised several optimization algorithms which can be embedded into the transformations to improve the quality of the output model. \nIn order to prove the feasibility of our approach\, we implemented an automatic model refinement engine which is targeted at the SpecC language. We validated the effectiveness of our approach by applying the refinement engine to a couple of large\, real-life applications. Experimental results demonstrate that 1000x productivity gain is achievable with automatic model generation.
URL:https://www.cecs.uci.edu/event/system-level-automatic-model-refinement/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040322T150000
DTEND;TZID=America/Los_Angeles:20040322T160000
DTSTAMP:20231011T183336Z
CREATED:20231011T183336Z
LAST-MODIFIED:20231011T183336Z
UID:14300-1079967600-1079971200@www.cecs.uci.edu
SUMMARY:Bluespec: Why chip design can't be left to EE's
DESCRIPTION:Lecture Slides \nBluespec: Why chip design can’t be left to EE’s\n\n\n\n\nSpeaker\n\n\nProfessor Arvind\nCSAIL (formerly LCS and AI Lab)\nMassachusetts Institute of Technology\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 22\, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHundred million-gate ASICs are possible by the end of the decade. However\, numerous problems related to process technology and design need to be solved before such large chips will become commonplace. Computer scientists are much better equipped to solve the new problems related to the design-in-the-large. Bluespec is a language/methodology that promotes correctness-by-construction. Its underlying execution model is based on atomic actions on state elements (such as flip-flops\, registers\, …)\, i.e.\, any legal behavior is explainable in terms of a sequence of atomic actions on the state. Expressiveness of Bluespec is achieved by keeping its static semantics orthogonal to its hardware execution semantics — the source program is turned into a flat interconnection of modules by “static elaboration” during the compile phase.This talk will present Bluespec via examples and show some of the designs done so far.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nArvind is the Johnson Professor of Computer Science and Engineering at the Massachusetts Institute of Technology. His work at MIT on high-level specification\, modeling\, synthesis and verification of architectures and protocols using Term Rewriting Systems (TRSs) laid the foundations for Sandburst and more recently Bluespec Inc. Previously\, he contributed to the development of dynamic dataflow architectures\, and together with Dr R.S.Nikhil published the book “Implicit Parallel Programming in pH”. Arvind is an IEEE Fellow and was awarded the Charles Babbage Outstanding Scientist Award in 1994. He has received the Distinguished Alumni Awards from the Indian Institute of Technology\, Kanpur\, and the University of Minnesota.\n\n\n\nBluespec: Why chip design can’t be left to EE’s\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/bluespec-why-chip-design-cant-be-left-to-ees/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040319T150000
DTEND;TZID=America/Los_Angeles:20040319T160000
DTSTAMP:20231011T184637Z
CREATED:20231011T184637Z
LAST-MODIFIED:20231011T184637Z
UID:14344-1079708400-1079712000@www.cecs.uci.edu
SUMMARY:Specification-driven Validation of Programmable Embedded Systems
DESCRIPTION:Specification-driven Validation of Programmable Embedded Systems\nby Prabhat Mishra\nValidation of programmable embedded systems\, consisting of processor cores\, coprocessors\, and memory subsystems\, is one of the major bottlenecks in current System-on-Chip (SOC) design methodology. One of the most important problems in validation of such systems is the lack of a golden reference model. As a result\, many existing validation techniques employ a bottom-up approach to design verification\, where the functionality of an existing architecture is\, in essence\, reverse-engineered from its implementation. \nThis thesis presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification. We have developed validation techniques to ensure that the static and dynamic behaviors of the specified architecture are well formed. The validated specification is used as a golden reference model. \nA major challenge in top-down validation methodology is the ability to generate executable models from the specification for a wide variety of programmable architectures. We have developed a functional abstraction technique that enables specification-driven model generation for simulation\, hardware generation\, and property checking. The generated simulator and hardware models are used for design space exploration of programmable architectures. \nWe have explored two top-down validation scenarios: design validation and test generation. First\, the generated hardware is used as a reference model to verify the hand-written implementation using a combination of symbolic simulation and equivalence checking. Second\, we have proposed a functional coverage based test generation technique for validation of pipelined processor architectures. The experiments demonstrate the utility of the specification-driven validation methodology for programmable embedded systems.
URL:https://www.cecs.uci.edu/event/specification-driven-validation-of-programmable-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040305T150000
DTEND;TZID=America/Los_Angeles:20040305T160000
DTSTAMP:20231011T190303Z
CREATED:20231011T190303Z
LAST-MODIFIED:20231011T190303Z
UID:14387-1078498800-1078502400@www.cecs.uci.edu
SUMMARY:CECS Bids Farewell to Sumit Gupta
DESCRIPTION:Over 45 graduate students\, staff and faculty gathered together on March 5 to wish Dr. Sumit Gupta a warm farewell as he departs CECS to join the Tallwood Venture Capital group in Silicon Valley. Sumit was an integral member of CECS for 6 years\, graduating with a Ph.D. in June 2003\, followed by one-year as a Post-Doctoral Researcher. At CECS he worked on parallelizing high-level synthesis\, reconfigurable computing\, and low-power mobile computing. Professor Nikil Dutt\, who hosted the event\, is shown congratulating Sumit. \n\nview larger image \n\nview larger image
URL:https://www.cecs.uci.edu/event/cecs-bids-farewell-to-sumit-gupta/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040206T150000
DTEND;TZID=America/Los_Angeles:20040206T160000
DTSTAMP:20231011T183337Z
CREATED:20231011T183337Z
LAST-MODIFIED:20231011T183337Z
UID:14301-1076079600-1076083200@www.cecs.uci.edu
SUMMARY:Embedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond
DESCRIPTION:Lecture Slides \nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\nSpeakers\n\n\nJonathan R. Haigh and Michael W. Wilkerson\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Veidenbaum\nalexv@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, February 6\, 2004\nRefreshments at 10:30am\, Seminar begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOptimizing power consumption is a primary goal in the design of embedded microprocessors even as the push for higher performance continues.  Managing the microprocessor’s power dissipation while still striving to push the design into GHz speeds provides a significant challenge.  As designs move to 90 nm and beyond\, device scaling has reduced oxide thicknesses and V T to the point where standby leakage power is on the same order of magnitude as active power.  Today’s successful designs need to aggressively manage both active and standby currents.  A collection of methods to control both active and leakage power in Cache and Translation Lookaside Buffer (TLB) circuits\, while minimizing the impact to performance\, will be discussed.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nJonathan R. Haigh: \nJon is the lead L1 cache designer for the current generation of XScale products.  He began his EE career at GE in 1996 followed by the former Digital Semiconductor in 1998.  He joined Intel Corporation in 2000 and has been working on the XScale cache circuit design team since joining the company.  He received his B.S. degree in Electrical Engineering concentrating in VLSI design from the University of Cincinnati .Michael W. Wilkerson: \nMike received the B.S. and M.S. degrees in electrical engineering from the University of Florida in 1991 and 1997.  He was in the U.S. Navy from 1983 to 1996 and joined Intel Corporation in 1998.  He has worked in logic verification and VLSI circuit design for Itanium and XScale microprocessors while at Intel.  He most recently completed the physical design of the data path memory management unit\, which includes a TLB structure\, for a new XScale core.\n\n\n\nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\n\n\n\nclick on the thumbnails to view the full-sized images\n\n\n\n\n\n\nThe lecture was held at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh and Mike Wilkerson are members of the team designing the Intel XScale embedded processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon and Mike chatting with CECS students before delivering their talk. Professor Alex Veidenbaum\, left background\, hosted the event.  \nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nMike Wilkerson discussing embedded processor design challenges. At 90 nm\, it is important to employ architectural techniques that emphasize power reduction.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh explaining cache memory design strategies for the XScale processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nA lively Q & A session followed the presentation.\nview larger image
URL:https://www.cecs.uci.edu/event/embedded-microprocessor-cache-and-translation-lookaside-buffer-tlb-low-power-circuit-techniques-for-90nm-and-beyond/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040127T150000
DTEND;TZID=America/Los_Angeles:20040127T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14348-1075215600-1075219200@www.cecs.uci.edu
SUMMARY:System-Level Design Methodology
DESCRIPTION:Presented by Professor Daniel Gajski\, University of California\, Irvine\nASP-DAC 2004\nPacifico Yokohama\, Yokohama\, Japan\nJanuary 27\, 2004\ndownload pdf
URL:https://www.cecs.uci.edu/event/system-level-design-methodology/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040116T150000
DTEND;TZID=America/Los_Angeles:20040116T160000
DTSTAMP:20231011T183337Z
CREATED:20231011T183337Z
LAST-MODIFIED:20231011T183337Z
UID:14302-1074265200-1074268800@www.cecs.uci.edu
SUMMARY:System-Level Design: Only the Radical Will Survive
DESCRIPTION:  \nLecture Slides \nSystem-Level Design: Only the Radical Will Survive\n\n\n\n\nSpeaker\n\n\nDr. Reinaldo Bergamaschi\nIBM T. J. Watson Research Center\, Yorktown Heights \, NY\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, January 16\, 2004\nRefreshments served at 10:00 a.m.\, lecture begins at 10:30 a.m.\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe term “system-level design” has been defined\, used and abused countless times by designers\, cad developers and most of all\, tools sales people. By now we all know what is supposed to be\, and it ‘ain’t pretty` (despite the claims by cad vendors). In this talk\, I will argue that for the past 5 years (at least) we have tried to develop system-level tools by fattening the already beaten up ASIC design methodology\, by exaggerating the advantages of high-level languages\, by overblowing the benefits of software-related methodologies for designing hardware\, among other very incremental approaches. The design methodologies and tools currently used for system-on-chip design are an evolution of ASIC and board-level design tools. Such an incremental approach has been ineffective in closing the productivity design gap. I will analyze the current push to use high-level languages and software approaches for hardware design\, and try to convince the audience that such attempts\, while in the right direction\, are far from sufficient. I will argue that radical new approaches for system design are needed if we want to be able to design new products in shorter time-to-market. I will discuss some of the approaches we are developing at IBM Research and speculate on possible new research avenues.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nReinaldo Bergamaschi graduated in Electronics Engineering from the Aeronautics Institute of Technology\, Sao Jose dos Campos\, Brazil \, in 1982\, and in 1984 he received the M.E.E degree from the Philips International Institute\, Eindhoven\, The Netherlands. In 1989 he obtained the Ph.D. degree in Electronics and Computer Science from the University of Southampton\, Southampton\, England\, and joined the IBM T. J. Watson Research Center\, Yorktown Heights \, USA. He has worked extensively on RTL\, behavioral and system-level design tools and methodologies. He was the main architect of IBM’s high-level synthesis system and he is currently developing system-level modeling and synthesis tools for core-based\, platform-based designs. He has participated in numerous conference committees and given several tutorials and lectures on high-level and system-level design issues and tools.\n\n\n\nSystem-Level Design: Only the Radical Will Survive\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/system-level-design-only-the-radical-will-survive/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040113T150000
DTEND;TZID=America/Los_Angeles:20040113T160000
DTSTAMP:20231011T193551Z
CREATED:20231011T185036Z
LAST-MODIFIED:20231011T193551Z
UID:14355-1074006000-1074009600@www.cecs.uci.edu
SUMMARY:The Nicholas Endowment Presents CECS a $100\,000 Gift
DESCRIPTION:The Nicholas Endowment Presents CECS a $100\,000 Gift\nJanuary 13 \, 2004 \nThe Center for Embedded Computer Systems at the University of California\, Irvine recently received a $100\,000 gift from The Nicholas Endowment. Craig S. Gunther\, Chairmen of Board of Trustees\, The Nicholas Foundation\, presented the gift to Daniel D. Gajski\, The Henry Samueli “Turing” Endowed Chair and Director\, Center for Embedded Computer Systems. The gift will support two UCI graduate students performing interdisciplinary research in embedded systems for the 2005-2006 academic year. The selected students will be designated Henry T. Nicholas\, III Research Fellows. The fellowships will provide a stipend plus the payment of tuition and fees for one academic year. The candidates will be selected by an independent committee composed of CECS faculty and representatives from The Nicholas Endowment. \nNicolaos G. Alexopoulos\, Dean of the Henry Samueli School of Engineering at UCI stated: “This gift by Dr. and Mrs. Henry T. Nicholas\, III will strengthen our efforts to create a cluster of outstanding graduate students in Embedded Systems Design. This is a pervasive and expanding field in all sectors of technology and therefore it impacts our economy to a significant degree.”
URL:https://www.cecs.uci.edu/event/the-nicholas-endowment-presents-cecs-a-100000-gift/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031219T150000
DTEND;TZID=America/Los_Angeles:20031219T160000
DTSTAMP:20231011T184638Z
CREATED:20231011T184638Z
LAST-MODIFIED:20231011T184638Z
UID:14345-1071846000-1071849600@www.cecs.uci.edu
SUMMARY:Estimation and Exploration Automation of System Level Design
DESCRIPTION:Estimation and Exploration Automation of System Level Design\nby Lukai Cai\nRecently\, as system design is becoming more and more challenging due to decreasing timeto-\nmarket and increasing system complexities\, trends are emerging to move the design process to\nhigher levels of abstraction. System-level design demands corresponding approaches that efficiently explore the complete system design space and rapidly evaluate a large number of design alternatives in a short amount of time. \nThis work proposes fast estimation and efficient exploration approaches for system synthesis\ndesign flow. It starts with the system behavior which represents the design functionality\, generates\nthe system architecture from the system behavior\, and finally maps the system behavior to the\nsystem architecture. \nIn this work\, we target at complex system design: the system behavior is modeled concurrently\nand hierarchically\, the system architecture is assembled by processing elements with\ndifferent attributes and incompatible communication protocols. Because our approaches are all\nimplemented at high abstraction levels and have relatively low time complexities\, we meet the\nrequirement for fast estimation and exploration of the system level design.
URL:https://www.cecs.uci.edu/event/estimation-and-exploration-automation-of-system-level-design/
CATEGORIES:PhD Defenses
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031209T150000
DTEND;TZID=America/Los_Angeles:20031209T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14303-1070982000-1070985600@www.cecs.uci.edu
SUMMARY:The Fundamentals: Moore's Law\, Microarchitecture\, and the Microprocessor of the Year 2014
DESCRIPTION:The Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\nSpeaker\n\n\nProfessor Yale Patt\nThe University of Texas at Austin\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Jean-Luc Gaudiot\ngaudiot@uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 9\, 2003\nRefreshments at 1:15pm\, Lecture begins at 1:30pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nMoore’s Law promises very soon more than a billion transistors on a chip processing at more than 10 GHz. But\, what else does Moore ‘s Law tell us about the future of high performance microprocessors. Is there anything left to do in the microarchitecture to make use of all this capability\, or should we fold our tents and go home? Many claim we have reached the end of our rope. In this talk\, I hope to spend a little time discussing the rationale of the naysayer and then move on to what we can do. Per usual\, I plan to tie my comments to the fundamentals\, because I believe it is always the fundamentals that provide the insights to new knowledge. Finally\, I will discuss what I think we will see in the microprocessor of the year 2014\, including the block-structured ISA\, stronger use of SSMT\, greater use of microcode\, dedicated infrequently used functional units\, and most importantly\, a stronger coupling with the compiler\, language\, and algorithm technologies. If time permits\, I will discuss some things I do not think we will see on the chip\, like qbits and machines that think.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nYale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell\, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He directs the Ph.D. research of 12 graduate students in computer architecture and teaches both the freshman introduction to computing and his graduate course in Microarchitecture. He has received the highest honors in his field for his research and teaching\, including the 1996 IEEE/ACM Eckert-Mauchly Award for his contributions to high performance microprocessor design and the 2000 ACM Karl V. Karlstrom Outstanding Educator Award for his contributions to education. He has had\, for the past 35 years\, an active consulting practice\, including long term associations with Intel\, Digital\, NCR\, Motorola\, and others. His freshman textbook “Introduction to Computing Systems: from bits and gates to C and beyond\,” has been adopted by more than 100 universities world-wide. It is co-authored with Professor Sanjay Patel of the University of Illinois . McGraw-Hill just released the second edition this fall. Yale Patt is a Fellow of both the IEEE and the ACM.\n\n\n\nThe Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\n\n\n\nMcDonnell Douglas Auditorium at Engineering Gateway.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nLecture began at 1:30pm at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nProfessor Yale Patt talking about microarchitecture.\nview larger image
URL:https://www.cecs.uci.edu/event/the-fundamentals-moores-law-microarchitecture-and-the-microprocessor-of-the-year-2014/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031120T150000
DTEND;TZID=America/Los_Angeles:20031120T160000
DTSTAMP:20231011T184837Z
CREATED:20231011T184837Z
LAST-MODIFIED:20231011T184837Z
UID:14349-1069340400-1069344000@www.cecs.uci.edu
SUMMARY:System Debugging and Verification: A New Challenge
DESCRIPTION:Presented by Professor Daniel Gajski and Samar Abdi\, University of California\, Irvine\nVerify 2003\nNovember 20\, 2003\ndownload pdf
URL:https://www.cecs.uci.edu/event/system-debugging-and-verification-a-new-challenge/
CATEGORIES:PhD Defenses
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