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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090309T150000
DTEND;TZID=America/Los_Angeles:20090309T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T181037Z
LAST-MODIFIED:20231011T192457Z
UID:14252-1236610800-1236614400@www.cecs.uci.edu
SUMMARY:Nonlinear Symbolic Program Analysis for Increased Parallelization
DESCRIPTION:Nonlinear Symbolic Program Analysis for Increased Parallelization\n\n\n\n\nSpeaker\n\n\nProfessor Kleanthis Psarris \nDepartment of Computer Science\nThe University of Texas at San Antonio\, TX\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Nicolau\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 9\, 2009\nRefreshments at 2:30 pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHigh end parallel and multi-core processors rely on compilers to perform the necessary optimizations and exploit concurrency in order to achieve higher performance. However\, source code for high performance computers is extremely complex to analyze and optimize. In particular\, program analysis techniques often do not take into account complex expressions during the data dependence analysis phase. Most data dependence tests are only able to analyze linear expressions\, even though non-linear expressions occur very often in practice. Therefore\, considerable amounts of potential parallelism remain unexploited. In this talk we propose new data dependence analysis techniques to handle such complex instances of the dependence problem and increase program parallelization. Our method is based on a set of polynomial time techniques that can prove or disprove dependences in source codes with non-linear and symbolic expressions\, complex loop bounds\, arrays with coupled subscripts\, and if-statement constraints. In addition our algorithm can produce accurate and complete direction vector information\, enabling the compiler to apply further transformations. To validate our method we performed an experimental evaluation and comparison against the I-Test\, the Omega test and the Range test in the Perfect and SPEC benchmarks. The experimental results indicate that our dependence analysis tool is accurate\, efficient and more effective in program parallelization than the other dependence tests. The improved parallelization results into higher speedups and better program execution performance in several benchmarks.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nKleanthis Psarris is Professor and Chair of the Department of Computer Science at the University of Texas at San Antonio. His research interests are in the areas of Parallel and Distributed Systems\, Compilers and Programming Languages. He received his B.S. degree in Mathematics from the National University of Athens\, Greece in 1984. He received his M.S. degree in Computer Science in 1987\, his M.Eng. degree in Electrical Engineering in 1989 and his Ph.D. degree in Computer Science in 1991\, all from Stevens Institute of Technology in Hoboken\, New Jersey. He has published extensively in top journals and conferences in the field and his research has been funded by the National Science Foundation and Department of Defense agencies. He is an Editor of the Parallel Computing journal. He has served on the Program Committees of several international conferences including the ACM International Conference on Supercomputing (ICS) in 1995\, 2000\, 2006 and 2008\, the IEEE International Conference on High Performance Computing and Communications (HPCC) in 2008 and 2009\, and the ACM Symposium on Applied Computing (SAC) in 2003\, 2004\, 2005 and 2006.
URL:https://www.cecs.uci.edu/event/nonlinear-symbolic-program-analysis-for-increased-parallelization/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090227T150000
DTEND;TZID=America/Los_Angeles:20090227T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14324-1235746800-1235750400@www.cecs.uci.edu
SUMMARY:Automatic Design and Optimization of Application Specific Processors
DESCRIPTION:Automatic Design and Optimization of Application Specific Processors\nby Jelena Trajkovic \nThe stringent performance and power requirements of modern applications have fueled the need for application specific computing platforms. Conventional general purpose embedded processor do not provide the necessary throughput for meeting the applications’ performance and power needs. On the other hand\, manual hardware design is too expensive and results in inflexible implementation. The short time to market demands also make hardware design prohibitive. Therefore\, there exists a need for automatic design methods and tools that provide a high performance\, programmable and energy-efficient implementation starting from standard application descriptions such as C reference code. High level synthesis and application specific processor tools are a step in this direction\, but suffer from scalability\, quality and controllability issues. In this dissertation\, we present techniques for automatic processor design from C code that are scalable to thousands of lines of C code\, are controllable at each step of the design process and provide quality of results comparable to manual design. \nOur contributions enable a system level design methodology for application specific processors that starts with a reference C code of the application. An initial processor data path is constructed from a database of available components such as function units\, register files and buses. The initial data path is based on the types of operations and available concurrency in the application. The data path is then iteratively refined until an efficient architecture is derived. The key optimization goal is to keep performance within given boundaries while maximizing resource utilization. We further optimize the processor design using a novel algorithm for automatic custom pipelining based on the C code. The pipelining optimization also targets both resource utilization and performance. Our experimental results with large applications such as DCT and MP3 decoder show that automatically generated architectures are comparable to manual designs\, but can be obtained in a matter of few seconds\, leading to significant productivity gains. \nOur final contribution to design methods for embedded systems deals with low power memory design. Typically\, DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high\, exceeding that of the data cache or even that of the processor. We present and evaluate a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small\, cache-like structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption\, 23%\, on average\, and reduction in the energy-delay product\, 44%\, on average. The approach also improves performance: the CPI is reduced by 26%\, on average.
URL:https://www.cecs.uci.edu/event/automatic-design-and-optimization-of-application-specific-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081119T150000
DTEND;TZID=America/Los_Angeles:20081119T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14282-1227106800-1227110400@www.cecs.uci.edu
SUMMARY:My Work and My Life
DESCRIPTION:by Prof. Leonard KleinrockDepartment of Computer Science\nUniversity of California\, Los Angeles\nMcDonnell Douglas Auditorium\nDistinguished Lecture\, November 19\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/my-work-and-my-life/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081104T150000
DTEND;TZID=America/Los_Angeles:20081104T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192254Z
UID:14243-1225810800-1225814400@www.cecs.uci.edu
SUMMARY:Geppeto*: Consumer’s Approach to Programming
DESCRIPTION:Prof. Sinisa Srbljic\, School of Electrical Engineering and Computing\, University of Zagreb\, CroatiaNovember 4\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/geppeto-consumers-approach-to-programming/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080709T150000
DTEND;TZID=America/Los_Angeles:20080709T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14325-1215615600-1215619200@www.cecs.uci.edu
SUMMARY:Improving Packet Latencies of Live Streams in Wired Networks
DESCRIPTION:Improving Packet Latencies of Live Streams in Wired Networks\nby Arijit Ghosh (Advisor: Prof. Tony Givargis)\nDate: July 9\, 2008 \nLive streaming is becoming increasingly popular. In a study published in January 2008\, Cisco predicted that Internet-to-TV video will account for 30% of all Internet traffic. If all kinds of video traffic are considered\, then it will be 90% of consumer traffic by 2012. We distinguish live streams from on demand streams. Live streams are sent as the data is being generated\, is typically of long duration\, requires high bandwidth and associated with flash crowd behavior. As such\, live streams place tremendous demand on network resources. \nIn this thesis\, we proposed network techniques to improve packet latencies of live streams in wired networks. In particular\, we made the following contributions. First\, we proposed a technique that allows multicasting at the access network\, the proverbial last mile which presents tremendous bandwidth limitations. Second\, we reduced nodal processing by a tunelling scheme based on source routing. Essentially\, using routing computed at source and a novel network encoding scheme\, we eliminated intermediate processing. Third\, we presented a queueing algorithm that schedules packets based on application deadlines\, reduces the number of sorting iterations\, thereby improving performance\, has low complexity\, exhibits good fairness and provides a bounded delay for a single packet that is independent of the number of flows. Finally\, we proposed a variation of QoS routing that works with only partial network state information.
URL:https://www.cecs.uci.edu/event/improving-packet-latencies-of-live-streams-in-wired-networks/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080708T150000
DTEND;TZID=America/Los_Angeles:20080708T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14326-1215529200-1215532800@www.cecs.uci.edu
SUMMARY:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems
DESCRIPTION:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems\nby Minyoung Kim (Advisor: Prof. Nikil Dutt)\nDate: July 8\, 2008 \nResource limited mobile real-time embedded systems can benefit greatly from  dynamic adaptation of system parameters. This thesis proposes a novel framework  xTune that employs iterative tuning using light-weight formal verification at runtime with feedback for dynamic adaptation. One objective of this approach is to enable tradeoff analysis across multiple layers (for example\, application\, middleware\, operating system) and predict the possible property violations as the system evolves dynamically over time. Specifically\, an executable formal specification is developed for each layer of the mobile real-time system under consideration. The formal specification is then analyzed using statistical model checking and statistical quantitative analysis\, to determine the impact of various resource management policies for achieving desired a variety of end-to-end properties in a quantifiable manner. The integration of formal analysis with dynamic behavior from system execution results in a feedback loop that enables model refinement and further optimization of policies and parameters. Finally\, we propose a composition method for coordinated interaction of optimizers at different layers. The core idea of our approach is that each participating optimizer can restrict its own parameters and exchange refined parameters with its associated layers. We demonstrate the applicability of the proposed methodology to the adaptive provisioning of mobile real-time embedded systems by treating a multimedia case study on resource-limited devices.
URL:https://www.cecs.uci.edu/event/xtune-a-formal-methodology-for-cross-layer-tuning-of-mobile-real-time-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080616T150000
DTEND;TZID=America/Los_Angeles:20080616T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14327-1213628400-1213632000@www.cecs.uci.edu
SUMMARY:A Runtime System for Memory-Constrained Distributed Embedded Systems
DESCRIPTION:A Runtime System for Memory-Constrained Distributed Embedded Systems\nby Jiwon Hahn (Advisor: Prof. Pai Chou)\nDate: June 16\, 2008 \nWearable and embedded wireless sensor platforms are often highly constrained in size and power consumption in order to operate in unintrusive ways. To meet these constraints\, the memory is kept as small as possible to reduce area and power\, but at the same time it poses new challenges on programming. To address these problems\, this dissertation proposes \n(1) a framework for synthesis of host-assisted scripting engines\, \n(2) a minimum-overhead yet powerful runtime system based on recursive threaded code\, and \n(3) a host-assisted memory optimization technique that exploits high-level knowledge in models of computation. The benefits are three-fold: first\, the interactive access between programmer and embedded system improve productivity of programmers. Second\, the low runtime overhead and memory requirements enable this runtime system to run on compact platforms while providing high flexibility and composability. Third\, a new memory optimization scheme combined with the dispatching structure expose regularity of dataflow models to enable memory and scheduling optimizations\, sometimes in ways better than manual coding. \nExperimental results show that systems developed using these techniques have unleashed the power of these resource-constrained distributed embedded systems. As memory is currently the limiting factor\, the lightweight runtime system and systematic memory optimization technique presented in this dissertation are enabling technology for a new class of real-world\, ultra-compact distributed embedded systems.
URL:https://www.cecs.uci.edu/event/a-runtime-system-for-memory-constrained-distributed-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14375-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:CECS DAC Open House
DESCRIPTION:The 45th Design Automation Conference (DAC) is being held in Anaheim\, CA on June 8-13\, 2008. CECS cordially invites DAC attendees to an Open House on Friday afternoon\, June 13\, 2008 from 2:00PM to 4:00PM in our CECS office on the 2rd floor of the Anteater Instruction & Research Building (AIRB). We are planning a buffet of sandwiches\, cookies\, and soft drinks for a relaxed atmosphere. Many of our research affiliates and graduate students will be available to informally discuss new directions in technology and research.\nFor those attending DAC\, kindly consider attending this open house to see first hand our research programs and visit with our professors and graduate students. We are planning an informal environment and hope you will attend and enjoy the CECS hospitality.\nView Flyer with Directions
URL:https://www.cecs.uci.edu/event/cecs-dac-open-house/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14244-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models
DESCRIPTION:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models\n\n\n\n\nSpeaker\n\n\nDr. Christian Haubelt\nUniversity of Erlangen-Nuremberg\, Germany\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Tower\, Room 331\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 13 \, 2008\nTalk begins 11:00am\nRefreshments at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n80% of all design decisions are made in the first 20% of the design time. Thus\, a substantiated knowledge about possible solutions is mandatory in early design phases in order to design high quality products. SystemCoDesigner is a software tool for automatic design space exploration at the electronic system level and for platform-based prototyping of hardware/software systems. By exploring the design space\, a designer becomes more confident in decisions to be done. Starting from a behavioral SystemC description different solutions are generated automatically by using software synthesis techniques and Forte Design Systems’ Cynthesizer for behavioral hardware synthesis. In order to allow such a degree of automation\, SystemCoDesigner requires the behavioral SystemC model to be representable in a well-defined Model of Computation\, called FunState. As a case study\, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput\, ranging from software only solutions up to pure hardware implementations which reach real-time performance for QCIF streams on a 50MHz FPGA. In this talk\, the SystemCoDesigner overall design flow\, the FunState Model of Computation\, and some automatic transformation are presented using the Motion-JPEG case study.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nChristian Haubelt received his diploma degree in Electrical Engineering from the University of Paderborn\, Germany\, in 2001. He received his Ph.D. in Computer Science from the University of Erlangen-Nuremberg\, Germany\, in 2005. Since 2004\, he is head of the System-Level Design Automation Group at the Chair of Hardware/Software Co-Design\, University of Erlangen-Nuremberg\, Germany. Dr. Haubelt’s research interests include electronic system level design\, system level design automation\, and multi-objective optimization.\n\n\n\n\n\n\n\n\n\n\nWeb Site\n\n\nhttp://www12.informatik.uni-erlangen.de/people/haubelt/
URL:https://www.cecs.uci.edu/event/systemcodesigner-automatic-design-space-exploration-and-rapid-prototyping-from-behavioral-models/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080604T150000
DTEND;TZID=America/Los_Angeles:20080604T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14328-1212591600-1212595200@www.cecs.uci.edu
SUMMARY:Source Re-coding to Create Parallel and Flexible MPSoC Models for Embedded System Design and Exploration
DESCRIPTION:by Pramod Chandraiah\, University of California\, Irvine\nJune 4\, 2008\nview details
URL:https://www.cecs.uci.edu/event/source-re-coding-to-create-parallel-and-flexible-mpsoc-models-for-embedded-system-design-and-exploration/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080512T150000
DTEND;TZID=America/Los_Angeles:20080512T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14329-1210604400-1210608000@www.cecs.uci.edu
SUMMARY:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip
DESCRIPTION:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip\nby Sudeep Pasricha (advisor: Prof. Nikil Dutt)\nDate: May 12\, 2008 \nWith the increasing performance demands of emerging convergence applications and advances in process technology\, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance\, power\, cost and reliability. Consequently\, the design\, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today. \nIn this dissertation\, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis\, comprehensively and automatically generating both the topology and protocol parameters\, while trading off multiple design constraints such as power\, performance\, area and cost.Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality\, better complexity management\, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs.
URL:https://www.cecs.uci.edu/event/commsyn-on-chip-communication-architecture-synthesis-for-multi-processor-systems-on-chip/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080510T150000
DTEND;TZID=America/Los_Angeles:20080510T160000
DTSTAMP:20231205T135317Z
CREATED:20231011T185235Z
LAST-MODIFIED:20231205T135317Z
UID:14359-1210431600-1210435200@www.cecs.uci.edu
SUMMARY:NISC: No-Instruction-Set-Computer
DESCRIPTION:Release Date: May 2008 (NISC Toolset 2008.05)NISC Demo: https://www.cecs.uci.edu/~nisc/  \nNo-Instruction-Set-Computer (NISC) Technology is the next generation of tools for Design Synthesis.\nWith NISC Technology\, you can simultaneously gain higher productivity and better quality of results. Other techniques only offer one of these benefits. \nTwo popular approaches for designing digital systems: \n\nLow-level design at Register Transfer Level (RTL).\n\nCan lead to efficient IPs but the development time and cost is very high.\nHigh-Level-Synthesis (HLS) goal: improve productivity\n\nAutomatically converts high-level description of the IP (e.g. written in C language) to RTL\nDesigner has little control over the quality of the generated RTL in terms of clock frequency\, area\, manufacturability\, power\, etc\n\nResult quality typically bad.\n\n\n\n\n\n\nHigh-level design using general-purpose or custom processors.\n\nDevelopment time and cost is much lower\, but the efficiency and implementation quality is also much lower.\nApplication-Specific-Instruction-Processors (ASIP) goal: improve quality\n\nAdds application-specific instructions to the processor\n\nFinding suitable custom instructions and adding them to the toolset (compiler\, simulator\, etc.) is a very challenging task.\nBecause of their instruction-set\, processors (including ASIPs) impose a minimum overhead in terms of area\, power\, and performance.\n\n\nThe processor-based implementation may become more appealing only when the IP design complexity is above a certain level (relatively very high).\n\nNot suitable if you want to run a few algorithms or design a hardware block\n\n\n\n\n\n\n\nReferences:\nD. Gajski\, “NISC: The Ultimate Reconfigurable Component\,” TR 03-28\, October 1\, 2003.\ndownload pdf
URL:https://www.cecs.uci.edu/event/nisc-no-instruction-set-computer/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080429T150000
DTEND;TZID=America/Los_Angeles:20080429T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14283-1209481200-1209484800@www.cecs.uci.edu
SUMMARY:Hardware-Accelerated Formal Verification
DESCRIPTION:by Prof. Masahiro FujitaVLSI Design and Education Center\nUniversity of Tokyo\, Tokyo\, Japan\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, April 29\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/hardware-accelerated-formal-verification/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080328T150000
DTEND;TZID=America/Los_Angeles:20080328T160000
DTSTAMP:20231205T135316Z
CREATED:20231011T185234Z
LAST-MODIFIED:20231205T135316Z
UID:14358-1206716400-1206720000@www.cecs.uci.edu
SUMMARY:ESE: Embedded System Environment
DESCRIPTION:Release Date: March 28\, 2008Web Site: https://www.cecs.uci.edu/~ese/ \nESE is a toolset for modeling\, synthesis and validation of multi-processor embedded system designs. It builds on over 15 years of research in system level design at CECS under Prof. Daniel Gajski. It consists of two parts: ESE Front End and ESE Back End. \nESE Front End provides automatic generation of SystemC transaction level models (TLMs) from graphical capture of system platform and application C/C++ code. ESE generated TLMs can be used either as virtual platforms for SW development or for fast and early timing estimation of system performance. The retargetable performance estimation utilizes the LLVM infrastructure. \nESE Back End provides automatic synthesis from TLM to Pin-Cycle Accurate Model (PCAM) consisting of RTL interfaces\, system SW and prototype ready FPGA project files. ESE generated RTL can be synthesized using standard logic synthesis tools and system SW can be compiled along with application code for a given processor. ESE automatically creates Xilinx EDK projects for download to Xilinx boards. \nThe key advantages of ESE are huge productivity gain (provided by model automation and higher design abstraction) and ease of use for non-experts (provided by C-based and graphical design input). To learn more about ESE or to download ESE Front End\, please visit the ESE Web Site. \nReference:\nD. Gajski\, A. Gerstlauer\, and S. Abdi\, “Embedded System Design: Concepts and Tools\,” ASP-DAC 2007 Pacifico Yokohama\, Yokohama\, Japan\, January 23\, 2007.\ndownload pdf
URL:https://www.cecs.uci.edu/event/ese-embedded-system-environment/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080324T150000
DTEND;TZID=America/Los_Angeles:20080324T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14284-1206370800-1206374400@www.cecs.uci.edu
SUMMARY:On Numerical Modeling of Large Strain Elastoplastic Structural Responses
DESCRIPTION:By Jurica Sori?Institute of Applied Mechanics\nFaculty of Mechanical Engineering and Naval Architecture\, University of Zagreb\, Croatia\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, Mar 24\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/on-numerical-modeling-of-large-strain-elastoplastic-structural-responses/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080306T150000
DTEND;TZID=America/Los_Angeles:20080306T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14245-1204815600-1204819200@www.cecs.uci.edu
SUMMARY:Tiptoe: A Compositional Real-Time Operating System
DESCRIPTION:Prof. Christoph Kirsch\, Dept. of Computer Sciences\, University of SalzburgDonald Bren Hall (DBH) 3011\, University of California\, Irvine\nMarch 06\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/tiptoe-a-compositional-real-time-operating-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080303T150000
DTEND;TZID=America/Los_Angeles:20080303T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14330-1204556400-1204560000@www.cecs.uci.edu
SUMMARY:Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design
DESCRIPTION:by Gunar Schirner\, University of California\, Irvine\nMarch 3\, 2008\nview details
URL:https://www.cecs.uci.edu/event/analysis-and-optimization-of-transaction-level-models-for-multi-processor-system-on-chip-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080110T150000
DTEND;TZID=America/Los_Angeles:20080110T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14285-1199977200-1199980800@www.cecs.uci.edu
SUMMARY:Opportunities for Power and Performance Optimization in Digital Feedback-Controllers
DESCRIPTION:By Prof. Forrest Brewer\, Deptment of Electrical & Computer EngineeringUniversity of California\, Santa Barbara\nEngineering Gateway\, Room 3161\, University of California\, Irvine\nLecture\, Jan 10\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/opportunities-for-power-and-performance-optimization-in-digital-feedback-controllers/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071229T150000
DTEND;TZID=America/Los_Angeles:20071229T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14286-1198940400-1198944000@www.cecs.uci.edu
SUMMARY:Passive Supply Voltage And Frequencey Scaling (PVS)
DESCRIPTION:By Prof. Naehyuck Chang\, EECS Department\, Seoul National UniversityBren Hall Room. 3011\, Unversity of California\, Irvine\nLecture\, Dec 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/passive-supply-voltage-and-frequencey-scaling-pvs/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071206T150000
DTEND;TZID=America/Los_Angeles:20071206T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14331-1196953200-1196956800@www.cecs.uci.edu
SUMMARY:Synthesis and Optimization of Low-Power Custom NISC Processors
DESCRIPTION:by Bita Gorjiara\, University of California\, Irvine\nDecember 6\, 2007\nview details
URL:https://www.cecs.uci.edu/event/synthesis-and-optimization-of-low-power-custom-nisc-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071026T150000
DTEND;TZID=America/Los_Angeles:20071026T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14376-1193410800-1193414400@www.cecs.uci.edu
SUMMARY:CECS Faculty-Students Gathering 2007
DESCRIPTION:Faculty and students mingle at the 2007 CECS Student-Faculty Gathering\, held in our new office at 2010 Anteater Instruction Research Building (AIRB). We would like to welcome all the new faces and welcome back returning faculty and students.\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/cecs-faculty-students-gathering-2007/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071003T000000
DTEND;TZID=America/Los_Angeles:20071003T000000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14195-1191369600-1191369600@www.cecs.uci.edu
SUMMARY:Gabor Madl wins prestigious ACM Award
DESCRIPTION:Gabor Madl\, a CECS graduate student pursuing a PhD in Computer Science\, received the 2008 ACM SIGBED/SIGSOFT Frank Anger Memorial Award at the 2007 Embedded Systems Week Conference held in Salzburg\, Austria. This award recognizes one student researcher from each of the professional societies (ACM SIGBED and ACM SIGSOFT)\, promoting the crossover of ideas between the embedded software and software engineering research communities. Gabor’s research focuses on applying formal methods to enable analysis and evaluation of embedded computer systems\, and is a member of Professor Nikil Dutt’s research group.\nA photograph of Gabor receiving his award can be viewed at: http://cs.uni-salzburg.at/ 
URL:https://www.cecs.uci.edu/event/gabor-madl-wins-prestigious-acm-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070920T150000
DTEND;TZID=America/Los_Angeles:20070920T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14332-1190300400-1190304000@www.cecs.uci.edu
SUMMARY:Software Architecture for High Data Rate Wireless Body Sensor Applications
DESCRIPTION:Software Architecture for High Data Rate Wireless Body Sensor Applications\nby Seung-Mok Yoo \nFor wireless body area sensor networks\, the wearable nodes are highly constrained by low power\, low cost\, and small size while deliverly high throughput and low latency in a multiple access environment. To accomplish these goals\, the hardware must be kept simple\, and as a result\, the traditional abstractions with separate layers of the protocol stack and application must be merged and made as streamlined as possible. This dissertation identifies and removes two bottlenecks with data transfers: one is between the base station and its sensor nodes\, and the other is within the sensor node. \nFirst\, we propose a thin-server\, fat-client architecture. It supports a pulling protocol that achieves intra-network collision-free multiple access as in TDMA but without the time synchronization overhead. It also achieves high data throughput of air bandwidth and adaptivity of CSMA protocols but without collision or complexity on the node side. \nSecond\, for intra-node transfers\, another known bottleneck is the system bus. We identify the double-transaction problem\, which is common to SPI\, DMA\, and other interfaces. We propose the Master-Handoff Protocol to eliminate the redundant transaction and improve latency significantly\, and it is compatible with existing controllers. It not only halves the data transfer time but also achieves energy reduction. Together\, these techniques enable highly constrained hardware to meet strict size and power constraints for high wearability without sacrificing performance.
URL:https://www.cecs.uci.edu/event/software-architecture-for-high-data-rate-wireless-body-sensor-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070918T150000
DTEND;TZID=America/Los_Angeles:20070918T160000
DTSTAMP:20231011T184245Z
CREATED:20231011T184245Z
LAST-MODIFIED:20231011T184245Z
UID:14333-1190127600-1190131200@www.cecs.uci.edu
SUMMARY:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract
DESCRIPTION:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract\nby Mehrdad Reshadi \nToday\, depending on the size and complexity of a program\, there are two options for synthesizing a program to hardware: (1) using High Level Synthesis (HLS)\, and (2) using Application-Specific-Instruction-Processor (ASIP). \nTraditional HLS techniques can only support relatively small applications and do not give enough control to the designer over the quality of results. Poor quality of results and limited application domain has prevented the HLS from wide spread usage. \nEmbedded processors often run only one or a few applications in the life-time of the system. Therefore\, they can be customized for the target applications and significantly improve the quality of the embedded system in terms of cost\, performance\, power consumption\, etc. This is the goal in ASIP approaches. Instruction-based architectures limit the customizations because: (a) hardware designer is limited by instruction coding\, size and complexity of the decoder; (b) compilers can support certain class of instructions and hence instructions cannot be very complex; and (c) manually updating compilers to incorporate the custom instructions is not practical and developing compilers that automatically utilize hardware customizations through new custom instructions is very complex. \nIn this talk I present a new design approach called NISC (No-Instruction-Set-Computer) Technology. In NISC\, the datapath and controller are generated in two different phases. First the datapath is generated or selected from a database based on the application behavior. At the core of NISC technology\, there is a cycle-accurate compiler that maps a given application directly on a given datapath and generates the control words (CWs) that control the datapath resources in every clock cycle. The NISC architecture style is similar to the old nanocode machines. However\, instead of using nanocodes inside the process for implementing the microcodes and in turn instructions\, in NISC the nanocode (CWs) are directly used to program the datapath. \nNISC simplifies customization and allows designer to fully control design quality. NISC simplifies ASIP (Application-Specific-Instruction-Processor) approach by removing the complex task of finding and designing “most profitable” custom instructions. In NISC only the datapath needs to be specified and NISC compiler generates code “as if” each basic block of the program is executed with one custom instruction. On the other hand\, NISC improves resource constrained HLS techniques by adding the connectivity constraints\, on top of the traditional resource constraints\, into synthesis process. This enables the designer to control every thing in datapath including wires\, which are becoming increasingly more critical in newer technologies. In fact NISC combines the ASIP and HLS techniques. \nTo realize the NISC Technology design flow\, several challenging categories of problems must be solved. Mainly we need: \n1. Techniques for efficiently designing and customizing a datapath for an application\n2. Techniques for efficiently compiling any application on any given datapath\n3. Techniques for efficiently synthesizing a controller from the output of compiler and then generating synthesizable code for different target implementations. \nIn my thesis\, I focus on the compilation problems to enable practical use of NISC IPs in a system. A working compiler and other NISC tools are available for public use from NISC websitehttps://www.cecs.uci.edu/~nisc/. An online version of the tools can be also directly accessed at this website.
URL:https://www.cecs.uci.edu/event/no-instruction-set-computer-nisc-modeling-and-compilation-abstract/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070615T150000
DTEND;TZID=America/Los_Angeles:20070615T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192949Z
UID:14236-1181919600-1181923200@www.cecs.uci.edu
SUMMARY:The ADRES & DRESC dynamically reconfigurable architecture and ANSI C compiler
DESCRIPTION:Dr. Bjorn De Sutter\, IMEC Research Labs\, Belgium Calit2 Room 3008\, University of California\, Irvine\nJune 15\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/the-adres-dresc-dynamically-reconfigurable-architecture-and-ansi-c-compiler/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070608T150000
DTEND;TZID=America/Los_Angeles:20070608T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192031Z
UID:14237-1181314800-1181318400@www.cecs.uci.edu
SUMMARY:A Methodology for Creating Application Specific Processor Architectures
DESCRIPTION:Prof. Anshul Kumar\, Indian Institute of Technology\, Delhi Calit2 Room 3008\, University of Califonria\, Irvine\nJune 08\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/a-methodology-for-creating-application-specific-processor-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070601T230000
DTEND;TZID=America/Los_Angeles:20070601T230000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14196-1180738800-1180738800@www.cecs.uci.edu
SUMMARY:Jelena and Gajski Receive IESS Best Paper Award
DESCRIPTION:Jelena Trajkovic\, a PhD candidate in computer science\, and Professor Daniel D Gajski\, received best paper award at the second International Embedded System Symposium that took place in Irvine\, California from May 30th to June 1st 2007. Their paper is titled “Automatic Data Path Generation from C Code for Custom Processors.” The paper was selected from over 60 submissions on the basis of technical quality and presentation. The authors of the best paper received an Altera Nios II Embedded Development Kit.\nAutomatic generation of architectures from C code is a fundamentally novel way of addressing the problem of system design. In traditional design methods\, architecture is assumed as fixed for implementing an application. Compilers must then figure out the best mapping of the application on the given architecture. This method may result in poor performance because the given architecture may not carry the best features to execute the application code. Moreover\, the architecture may carry features that are never used by the application\, resulting in wasted power and area. Architecture generation from C code attempts to solve this problem by automatically creating an architecture that “matches” the C code. \nIn their paper\, Jelena and Prof. Gajski present first results for the generation of matching architecture from C code. They address the selection of function units to meet performance goals while maximizing architecture utilization. Their experimental results demonstrate that the architecture could be generated for large C code\, including an MP3 decoder with over 14K lines of code\, under an hour. The optimizations improved architecture utilization by 30 to 60 percent while meeting performance constraints. \nCECS congratulates the researchers on their achievement and wishes them success in their future endeavors.
URL:https://www.cecs.uci.edu/event/jelena-and-gajski-receive-iess-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T192031Z
UID:14239-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Adaptive Mechanisms for Meeting Energy and Real-Time Constraints in MPSoC Platforms
DESCRIPTION:Prof. Flavio R. Wagner\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/adaptive-mechanisms-for-meeting-energy-and-real-time-constraints-in-mpsoc-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T193148Z
UID:14238-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Transparent Acceleration of Data Dependent Instructions for General Purpose Processors
DESCRIPTION:Prof. Luigi Carro\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract 
URL:https://www.cecs.uci.edu/event/transparent-acceleration-of-data-dependent-instructions-for-general-purpose-processors/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070528T210000
DTEND;TZID=America/Los_Angeles:20070528T210000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14198-1180386000-1180386000@www.cecs.uci.edu
SUMMARY:Payam Heydari Wins Guillemin-Cauer
DESCRIPTION:Payam Heydari\, associate professor of electrical engineering and computer science\, and a Calit2 academic affiliate at UC Irvine\, has won this year’s prestigious Guillemin- Cauer Award from the IEEE Circuits and Systems Society. Heydari is also the recipient of the 2005 IEEE Circuits and Systems Society Darlington Award\, which puts him in an elite group of only seven researchers who\, in the 40-year history of the awards\, have received both.\nHeydari was recognized for his paper “Model-Order Reduction Using Variational Balanced Truncation with Spectral Shaping\,” which was published in the IEEE Transactions on Circuits and Systems\, Vol. 53\, April 2006. \nThe latest integrated circuit technology – geared to the nanoscale – continues to create new possibilities for designers to substantially reduce chip size and increase speed. The technology\, however\, also presents challenges\, most notably to the yield and reliability of the circuits and on-chip wires. \nIt is essential to capture statistical fluctuations caused by process variations\, but testing such complicated systems can require days of computer simulation. Heydari’s approach dramatically reduces the time needed for this statistical modeling from days to just minutes. It significantly reduces the order of the original system while retaining important circuit characteristics\, such as frequency and timedomain. Most notably\, this technique accounts for statistical variation due to changes in process. \nIn addition\, Heydari’s approach provides a proven boundary for error between the reduced order model and the original system. The work has since been the foundation for several key papers published by other researchers on the same topic. \nThe Guillemin-Cauer Award recognizes the best journal paper published in IEEE Transactions on Circuits and Systems during the two calendar years preceding the award. The award is based on general quality\, originality\, contributions\, subject matter and timeliness.
URL:https://www.cecs.uci.edu/event/payam-heydari-wins-guillemin-cauer/
CATEGORIES:Awards
END:VEVENT
END:VCALENDAR