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X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080512T150000
DTEND;TZID=America/Los_Angeles:20080512T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14329-1210604400-1210608000@www.cecs.uci.edu
SUMMARY:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip
DESCRIPTION:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip\nby Sudeep Pasricha (advisor: Prof. Nikil Dutt)\nDate: May 12\, 2008 \nWith the increasing performance demands of emerging convergence applications and advances in process technology\, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance\, power\, cost and reliability. Consequently\, the design\, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today. \nIn this dissertation\, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis\, comprehensively and automatically generating both the topology and protocol parameters\, while trading off multiple design constraints such as power\, performance\, area and cost.Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality\, better complexity management\, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs.
URL:https://www.cecs.uci.edu/event/commsyn-on-chip-communication-architecture-synthesis-for-multi-processor-systems-on-chip/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080510T150000
DTEND;TZID=America/Los_Angeles:20080510T160000
DTSTAMP:20231205T135317Z
CREATED:20231011T185235Z
LAST-MODIFIED:20231205T135317Z
UID:14359-1210431600-1210435200@www.cecs.uci.edu
SUMMARY:NISC: No-Instruction-Set-Computer
DESCRIPTION:Release Date: May 2008 (NISC Toolset 2008.05)NISC Demo: https://www.cecs.uci.edu/~nisc/  \nNo-Instruction-Set-Computer (NISC) Technology is the next generation of tools for Design Synthesis.\nWith NISC Technology\, you can simultaneously gain higher productivity and better quality of results. Other techniques only offer one of these benefits. \nTwo popular approaches for designing digital systems: \n\nLow-level design at Register Transfer Level (RTL).\n\nCan lead to efficient IPs but the development time and cost is very high.\nHigh-Level-Synthesis (HLS) goal: improve productivity\n\nAutomatically converts high-level description of the IP (e.g. written in C language) to RTL\nDesigner has little control over the quality of the generated RTL in terms of clock frequency\, area\, manufacturability\, power\, etc\n\nResult quality typically bad.\n\n\n\n\n\n\nHigh-level design using general-purpose or custom processors.\n\nDevelopment time and cost is much lower\, but the efficiency and implementation quality is also much lower.\nApplication-Specific-Instruction-Processors (ASIP) goal: improve quality\n\nAdds application-specific instructions to the processor\n\nFinding suitable custom instructions and adding them to the toolset (compiler\, simulator\, etc.) is a very challenging task.\nBecause of their instruction-set\, processors (including ASIPs) impose a minimum overhead in terms of area\, power\, and performance.\n\n\nThe processor-based implementation may become more appealing only when the IP design complexity is above a certain level (relatively very high).\n\nNot suitable if you want to run a few algorithms or design a hardware block\n\n\n\n\n\n\n\nReferences:\nD. Gajski\, “NISC: The Ultimate Reconfigurable Component\,” TR 03-28\, October 1\, 2003.\ndownload pdf
URL:https://www.cecs.uci.edu/event/nisc-no-instruction-set-computer/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080429T150000
DTEND;TZID=America/Los_Angeles:20080429T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14283-1209481200-1209484800@www.cecs.uci.edu
SUMMARY:Hardware-Accelerated Formal Verification
DESCRIPTION:by Prof. Masahiro FujitaVLSI Design and Education Center\nUniversity of Tokyo\, Tokyo\, Japan\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, April 29\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/hardware-accelerated-formal-verification/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080328T150000
DTEND;TZID=America/Los_Angeles:20080328T160000
DTSTAMP:20231205T135316Z
CREATED:20231011T185234Z
LAST-MODIFIED:20231205T135316Z
UID:14358-1206716400-1206720000@www.cecs.uci.edu
SUMMARY:ESE: Embedded System Environment
DESCRIPTION:Release Date: March 28\, 2008Web Site: https://www.cecs.uci.edu/~ese/ \nESE is a toolset for modeling\, synthesis and validation of multi-processor embedded system designs. It builds on over 15 years of research in system level design at CECS under Prof. Daniel Gajski. It consists of two parts: ESE Front End and ESE Back End. \nESE Front End provides automatic generation of SystemC transaction level models (TLMs) from graphical capture of system platform and application C/C++ code. ESE generated TLMs can be used either as virtual platforms for SW development or for fast and early timing estimation of system performance. The retargetable performance estimation utilizes the LLVM infrastructure. \nESE Back End provides automatic synthesis from TLM to Pin-Cycle Accurate Model (PCAM) consisting of RTL interfaces\, system SW and prototype ready FPGA project files. ESE generated RTL can be synthesized using standard logic synthesis tools and system SW can be compiled along with application code for a given processor. ESE automatically creates Xilinx EDK projects for download to Xilinx boards. \nThe key advantages of ESE are huge productivity gain (provided by model automation and higher design abstraction) and ease of use for non-experts (provided by C-based and graphical design input). To learn more about ESE or to download ESE Front End\, please visit the ESE Web Site. \nReference:\nD. Gajski\, A. Gerstlauer\, and S. Abdi\, “Embedded System Design: Concepts and Tools\,” ASP-DAC 2007 Pacifico Yokohama\, Yokohama\, Japan\, January 23\, 2007.\ndownload pdf
URL:https://www.cecs.uci.edu/event/ese-embedded-system-environment/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080324T150000
DTEND;TZID=America/Los_Angeles:20080324T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14284-1206370800-1206374400@www.cecs.uci.edu
SUMMARY:On Numerical Modeling of Large Strain Elastoplastic Structural Responses
DESCRIPTION:By Jurica Sori?Institute of Applied Mechanics\nFaculty of Mechanical Engineering and Naval Architecture\, University of Zagreb\, Croatia\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, Mar 24\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/on-numerical-modeling-of-large-strain-elastoplastic-structural-responses/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080306T150000
DTEND;TZID=America/Los_Angeles:20080306T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14245-1204815600-1204819200@www.cecs.uci.edu
SUMMARY:Tiptoe: A Compositional Real-Time Operating System
DESCRIPTION:Prof. Christoph Kirsch\, Dept. of Computer Sciences\, University of SalzburgDonald Bren Hall (DBH) 3011\, University of California\, Irvine\nMarch 06\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/tiptoe-a-compositional-real-time-operating-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080303T150000
DTEND;TZID=America/Los_Angeles:20080303T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14330-1204556400-1204560000@www.cecs.uci.edu
SUMMARY:Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design
DESCRIPTION:by Gunar Schirner\, University of California\, Irvine\nMarch 3\, 2008\nview details
URL:https://www.cecs.uci.edu/event/analysis-and-optimization-of-transaction-level-models-for-multi-processor-system-on-chip-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080110T150000
DTEND;TZID=America/Los_Angeles:20080110T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14285-1199977200-1199980800@www.cecs.uci.edu
SUMMARY:Opportunities for Power and Performance Optimization in Digital Feedback-Controllers
DESCRIPTION:By Prof. Forrest Brewer\, Deptment of Electrical & Computer EngineeringUniversity of California\, Santa Barbara\nEngineering Gateway\, Room 3161\, University of California\, Irvine\nLecture\, Jan 10\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/opportunities-for-power-and-performance-optimization-in-digital-feedback-controllers/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071229T150000
DTEND;TZID=America/Los_Angeles:20071229T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14286-1198940400-1198944000@www.cecs.uci.edu
SUMMARY:Passive Supply Voltage And Frequencey Scaling (PVS)
DESCRIPTION:By Prof. Naehyuck Chang\, EECS Department\, Seoul National UniversityBren Hall Room. 3011\, Unversity of California\, Irvine\nLecture\, Dec 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/passive-supply-voltage-and-frequencey-scaling-pvs/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071206T150000
DTEND;TZID=America/Los_Angeles:20071206T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14331-1196953200-1196956800@www.cecs.uci.edu
SUMMARY:Synthesis and Optimization of Low-Power Custom NISC Processors
DESCRIPTION:by Bita Gorjiara\, University of California\, Irvine\nDecember 6\, 2007\nview details
URL:https://www.cecs.uci.edu/event/synthesis-and-optimization-of-low-power-custom-nisc-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071026T150000
DTEND;TZID=America/Los_Angeles:20071026T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14376-1193410800-1193414400@www.cecs.uci.edu
SUMMARY:CECS Faculty-Students Gathering 2007
DESCRIPTION:Faculty and students mingle at the 2007 CECS Student-Faculty Gathering\, held in our new office at 2010 Anteater Instruction Research Building (AIRB). We would like to welcome all the new faces and welcome back returning faculty and students.\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/cecs-faculty-students-gathering-2007/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071003T000000
DTEND;TZID=America/Los_Angeles:20071003T000000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14195-1191369600-1191369600@www.cecs.uci.edu
SUMMARY:Gabor Madl wins prestigious ACM Award
DESCRIPTION:Gabor Madl\, a CECS graduate student pursuing a PhD in Computer Science\, received the 2008 ACM SIGBED/SIGSOFT Frank Anger Memorial Award at the 2007 Embedded Systems Week Conference held in Salzburg\, Austria. This award recognizes one student researcher from each of the professional societies (ACM SIGBED and ACM SIGSOFT)\, promoting the crossover of ideas between the embedded software and software engineering research communities. Gabor’s research focuses on applying formal methods to enable analysis and evaluation of embedded computer systems\, and is a member of Professor Nikil Dutt’s research group.\nA photograph of Gabor receiving his award can be viewed at: http://cs.uni-salzburg.at/ 
URL:https://www.cecs.uci.edu/event/gabor-madl-wins-prestigious-acm-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070920T150000
DTEND;TZID=America/Los_Angeles:20070920T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14332-1190300400-1190304000@www.cecs.uci.edu
SUMMARY:Software Architecture for High Data Rate Wireless Body Sensor Applications
DESCRIPTION:Software Architecture for High Data Rate Wireless Body Sensor Applications\nby Seung-Mok Yoo \nFor wireless body area sensor networks\, the wearable nodes are highly constrained by low power\, low cost\, and small size while deliverly high throughput and low latency in a multiple access environment. To accomplish these goals\, the hardware must be kept simple\, and as a result\, the traditional abstractions with separate layers of the protocol stack and application must be merged and made as streamlined as possible. This dissertation identifies and removes two bottlenecks with data transfers: one is between the base station and its sensor nodes\, and the other is within the sensor node. \nFirst\, we propose a thin-server\, fat-client architecture. It supports a pulling protocol that achieves intra-network collision-free multiple access as in TDMA but without the time synchronization overhead. It also achieves high data throughput of air bandwidth and adaptivity of CSMA protocols but without collision or complexity on the node side. \nSecond\, for intra-node transfers\, another known bottleneck is the system bus. We identify the double-transaction problem\, which is common to SPI\, DMA\, and other interfaces. We propose the Master-Handoff Protocol to eliminate the redundant transaction and improve latency significantly\, and it is compatible with existing controllers. It not only halves the data transfer time but also achieves energy reduction. Together\, these techniques enable highly constrained hardware to meet strict size and power constraints for high wearability without sacrificing performance.
URL:https://www.cecs.uci.edu/event/software-architecture-for-high-data-rate-wireless-body-sensor-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070918T150000
DTEND;TZID=America/Los_Angeles:20070918T160000
DTSTAMP:20231011T184245Z
CREATED:20231011T184245Z
LAST-MODIFIED:20231011T184245Z
UID:14333-1190127600-1190131200@www.cecs.uci.edu
SUMMARY:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract
DESCRIPTION:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract\nby Mehrdad Reshadi \nToday\, depending on the size and complexity of a program\, there are two options for synthesizing a program to hardware: (1) using High Level Synthesis (HLS)\, and (2) using Application-Specific-Instruction-Processor (ASIP). \nTraditional HLS techniques can only support relatively small applications and do not give enough control to the designer over the quality of results. Poor quality of results and limited application domain has prevented the HLS from wide spread usage. \nEmbedded processors often run only one or a few applications in the life-time of the system. Therefore\, they can be customized for the target applications and significantly improve the quality of the embedded system in terms of cost\, performance\, power consumption\, etc. This is the goal in ASIP approaches. Instruction-based architectures limit the customizations because: (a) hardware designer is limited by instruction coding\, size and complexity of the decoder; (b) compilers can support certain class of instructions and hence instructions cannot be very complex; and (c) manually updating compilers to incorporate the custom instructions is not practical and developing compilers that automatically utilize hardware customizations through new custom instructions is very complex. \nIn this talk I present a new design approach called NISC (No-Instruction-Set-Computer) Technology. In NISC\, the datapath and controller are generated in two different phases. First the datapath is generated or selected from a database based on the application behavior. At the core of NISC technology\, there is a cycle-accurate compiler that maps a given application directly on a given datapath and generates the control words (CWs) that control the datapath resources in every clock cycle. The NISC architecture style is similar to the old nanocode machines. However\, instead of using nanocodes inside the process for implementing the microcodes and in turn instructions\, in NISC the nanocode (CWs) are directly used to program the datapath. \nNISC simplifies customization and allows designer to fully control design quality. NISC simplifies ASIP (Application-Specific-Instruction-Processor) approach by removing the complex task of finding and designing “most profitable” custom instructions. In NISC only the datapath needs to be specified and NISC compiler generates code “as if” each basic block of the program is executed with one custom instruction. On the other hand\, NISC improves resource constrained HLS techniques by adding the connectivity constraints\, on top of the traditional resource constraints\, into synthesis process. This enables the designer to control every thing in datapath including wires\, which are becoming increasingly more critical in newer technologies. In fact NISC combines the ASIP and HLS techniques. \nTo realize the NISC Technology design flow\, several challenging categories of problems must be solved. Mainly we need: \n1. Techniques for efficiently designing and customizing a datapath for an application\n2. Techniques for efficiently compiling any application on any given datapath\n3. Techniques for efficiently synthesizing a controller from the output of compiler and then generating synthesizable code for different target implementations. \nIn my thesis\, I focus on the compilation problems to enable practical use of NISC IPs in a system. A working compiler and other NISC tools are available for public use from NISC websitehttps://www.cecs.uci.edu/~nisc/. An online version of the tools can be also directly accessed at this website.
URL:https://www.cecs.uci.edu/event/no-instruction-set-computer-nisc-modeling-and-compilation-abstract/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070615T150000
DTEND;TZID=America/Los_Angeles:20070615T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192949Z
UID:14236-1181919600-1181923200@www.cecs.uci.edu
SUMMARY:The ADRES & DRESC dynamically reconfigurable architecture and ANSI C compiler
DESCRIPTION:Dr. Bjorn De Sutter\, IMEC Research Labs\, Belgium Calit2 Room 3008\, University of California\, Irvine\nJune 15\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/the-adres-dresc-dynamically-reconfigurable-architecture-and-ansi-c-compiler/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070608T150000
DTEND;TZID=America/Los_Angeles:20070608T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192031Z
UID:14237-1181314800-1181318400@www.cecs.uci.edu
SUMMARY:A Methodology for Creating Application Specific Processor Architectures
DESCRIPTION:Prof. Anshul Kumar\, Indian Institute of Technology\, Delhi Calit2 Room 3008\, University of Califonria\, Irvine\nJune 08\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/a-methodology-for-creating-application-specific-processor-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070601T230000
DTEND;TZID=America/Los_Angeles:20070601T230000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14196-1180738800-1180738800@www.cecs.uci.edu
SUMMARY:Jelena and Gajski Receive IESS Best Paper Award
DESCRIPTION:Jelena Trajkovic\, a PhD candidate in computer science\, and Professor Daniel D Gajski\, received best paper award at the second International Embedded System Symposium that took place in Irvine\, California from May 30th to June 1st 2007. Their paper is titled “Automatic Data Path Generation from C Code for Custom Processors.” The paper was selected from over 60 submissions on the basis of technical quality and presentation. The authors of the best paper received an Altera Nios II Embedded Development Kit.\nAutomatic generation of architectures from C code is a fundamentally novel way of addressing the problem of system design. In traditional design methods\, architecture is assumed as fixed for implementing an application. Compilers must then figure out the best mapping of the application on the given architecture. This method may result in poor performance because the given architecture may not carry the best features to execute the application code. Moreover\, the architecture may carry features that are never used by the application\, resulting in wasted power and area. Architecture generation from C code attempts to solve this problem by automatically creating an architecture that “matches” the C code. \nIn their paper\, Jelena and Prof. Gajski present first results for the generation of matching architecture from C code. They address the selection of function units to meet performance goals while maximizing architecture utilization. Their experimental results demonstrate that the architecture could be generated for large C code\, including an MP3 decoder with over 14K lines of code\, under an hour. The optimizations improved architecture utilization by 30 to 60 percent while meeting performance constraints. \nCECS congratulates the researchers on their achievement and wishes them success in their future endeavors.
URL:https://www.cecs.uci.edu/event/jelena-and-gajski-receive-iess-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T192031Z
UID:14239-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Adaptive Mechanisms for Meeting Energy and Real-Time Constraints in MPSoC Platforms
DESCRIPTION:Prof. Flavio R. Wagner\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/adaptive-mechanisms-for-meeting-energy-and-real-time-constraints-in-mpsoc-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T193148Z
UID:14238-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Transparent Acceleration of Data Dependent Instructions for General Purpose Processors
DESCRIPTION:Prof. Luigi Carro\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract 
URL:https://www.cecs.uci.edu/event/transparent-acceleration-of-data-dependent-instructions-for-general-purpose-processors/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070528T210000
DTEND;TZID=America/Los_Angeles:20070528T210000
DTSTAMP:20231011T180118Z
CREATED:20231011T180118Z
LAST-MODIFIED:20231011T180118Z
UID:14198-1180386000-1180386000@www.cecs.uci.edu
SUMMARY:Payam Heydari Wins Guillemin-Cauer
DESCRIPTION:Payam Heydari\, associate professor of electrical engineering and computer science\, and a Calit2 academic affiliate at UC Irvine\, has won this year’s prestigious Guillemin- Cauer Award from the IEEE Circuits and Systems Society. Heydari is also the recipient of the 2005 IEEE Circuits and Systems Society Darlington Award\, which puts him in an elite group of only seven researchers who\, in the 40-year history of the awards\, have received both.\nHeydari was recognized for his paper “Model-Order Reduction Using Variational Balanced Truncation with Spectral Shaping\,” which was published in the IEEE Transactions on Circuits and Systems\, Vol. 53\, April 2006. \nThe latest integrated circuit technology – geared to the nanoscale – continues to create new possibilities for designers to substantially reduce chip size and increase speed. The technology\, however\, also presents challenges\, most notably to the yield and reliability of the circuits and on-chip wires. \nIt is essential to capture statistical fluctuations caused by process variations\, but testing such complicated systems can require days of computer simulation. Heydari’s approach dramatically reduces the time needed for this statistical modeling from days to just minutes. It significantly reduces the order of the original system while retaining important circuit characteristics\, such as frequency and timedomain. Most notably\, this technique accounts for statistical variation due to changes in process. \nIn addition\, Heydari’s approach provides a proven boundary for error between the reduced order model and the original system. The work has since been the foundation for several key papers published by other researchers on the same topic. \nThe Guillemin-Cauer Award recognizes the best journal paper published in IEEE Transactions on Circuits and Systems during the two calendar years preceding the award. The award is based on general quality\, originality\, contributions\, subject matter and timeliness.
URL:https://www.cecs.uci.edu/event/payam-heydari-wins-guillemin-cauer/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070501T220000
DTEND;TZID=America/Los_Angeles:20070501T220000
DTSTAMP:20231011T180103Z
CREATED:20231011T180103Z
LAST-MODIFIED:20231011T180103Z
UID:14197-1178056800-1178056800@www.cecs.uci.edu
SUMMARY:Bita Gorjiara Takes Hami and Best Paper Award
DESCRIPTION:Bita Gorjiara has won the prestigious Hami Award of Excellence in Engineering Education for the year 2007. Sponsored by the Fanni Reunion Foundation\, the Hami award recognizes outstanding M.Sc. and Ph.D. graduates with a previous degree from University of Tehran. Each year\, Hami award is given to one or two students with excellent academic record in terms of GPA\, number of publications\, and overall contribution in their field of study. Bita has also received the Best Student Paper Award for her journal paper\, “Ultra-Fast and Efficient Algorithm for Energy Optimization by Gradient-based Stochastic Voltage and Task Scheduling\,” which has also been accepted for publication in ACM Transactions on Design Automation of Electronic Systems (TODAES).\nThis paper award is an honor given by the EECS department for first-time authors. In her paper\, co-authored by Professor Bagherzadeh and Professor Chou\, Bita proposes an ultra-fast and voltage scheduling algorithm called Adaptive Stocahstic Gradient Voltage-and-Task Scheduling (ASG-VTS) that is used for power optimization of designs with voltage islands. This unique technique was shows to surpass the energy savings of previously published results while reducing number of voltage transitions. Compared to an optimal ILP algorithm\, her technique converges 1000 times faster while generating results as good as the optimal solution. She has also developed a web-based tool for her algorithm that allows researchers to capture the model of their system and run ASG-VTS. Research groups use Bita’s tool for evaluating new algorithms\, and some universities have used as part of their course curriculum. \nCurrently\, and for the past three years\, Bita has been working on No-Instruction-Set Computer (NISC) project under supervision of Prof. Gajski. She has developed an Architecture Description Language (ADL) for NISC called GNR that is used for automatic generation of RTL code. She has also proposed techniques to reduce power consumption and code size of NISCs while improving their performance via architecture customization.
URL:https://www.cecs.uci.edu/event/bita-gorjiara-takes-hami-and-best-paper-award/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070426T150000
DTEND;TZID=America/Los_Angeles:20070426T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192254Z
UID:14240-1177599600-1177603200@www.cecs.uci.edu
SUMMARY:High Level Systems Validation Using Hierarchical Message Sequence Charts
DESCRIPTION:Dr. Praveen Murthy\, Fujitsu Labs of AmericaCalit2 Auditorium\, University of California\, Irvine\nApril 26\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/high-level-systems-validation-using-hierarchical-message-sequence-charts/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070423T150000
DTEND;TZID=America/Los_Angeles:20070423T160000
DTSTAMP:20231011T184245Z
CREATED:20231011T184245Z
LAST-MODIFIED:20231011T184245Z
UID:14334-1177340400-1177344000@www.cecs.uci.edu
SUMMARY:Software for Embedded Systems: Serializing Compilers and Its Applications
DESCRIPTION:Software for Embedded Systems: Serializing Compilers and Its  Applications\nby Andre Costi Nacul \nIn order to cope with the complexity of systems\, engineers are  turning to software. In part\, well established programming models\,  highly evolved tool chains\, ease of software reuse\, availability of  open-source software\, and expeditious nature of the design-compile- execute paradigm make developing a new feature in software more  favorable. It is assumed that\, in coming years\, more than 70% of  product features are going to be supported by software.\nIn particular\, the concurrent programming paradigm is an ideal model  of computation for design of embedded systems\, which often encompass  inherent concurrency. The support for concurrent programming is  usually provided by a real-time operating system (RTOS). Usually\, an  RTOS is a generic framework which can be used across a large number  of processors and applications. An RTOS provides coarse grained  timing support\, and is loosely coupled to the running tasks. As a  result\, an RTOS is seldom optimized for any particular application. \nDespite of all the recent enhancements to compiler technology\,  current compilers have a limited understanding of tasks. Generally\,  the compiler is tightly integrated with the platform. Traditional  compilers are efficient in using platform specific resources\, and in  generating an optimized instruction sequence. Current compiler  technology is capable of extracting instruction-level parallelism  (ILP)\, to varying degrees. Traditionally\, ILP comes from optimizing  loops\, and most likely analyzes code at the basic block level. Today\,  there is no compiler that can detect parallelism at the task level.  Parallelism detection is usually restricted to basic block  structures\, or higher level constructs such as loops. Moreover\,  compilers also lack support for timing constraints of real-time  applications. \nIn this thesis\, we propose an alternative to an RTOS based on the  idea of serializing compilers. A serializing compiler is an automated  software synthesis methodology that can transform a multitasking  application into an equivalent and optimized monolithic sequential  code\, to be compiled with the embedded processor’s native optimizing  compiler. The serializing compiler can analyze the tasks at compile  time and generate a fine-tuned\, application specific infrastructure  to support multitasking\, resulting in a more efficient executable  than one that is intended to run on top of a generic RTOS. By having  control over the application execution and context switches\, the  serializing compiler enables the fine grain control of task timing  while enhancing overall performance. Our serializing compiler  technology strengthens existing compilers\, making them timing and  task-aware. \nThe Phantom Compiler\, our implementation of a serializing compiler\,  provides a fully automated mechanism to synthesize a single threaded\,  ANSI C/C++ program from a multithreaded C/C++ (extended with POSIX)  program. The Phantom generated code is highly tuned for the input  application. With a serializing compiler such as the Phantom  Compiler\, it is possible to generate a multitasking infrastructure  that is small in size\, very efficient when context-switching\, and  customized for each specific application.
URL:https://www.cecs.uci.edu/event/software-for-embedded-systems-serializing-compilers-and-its-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070411T150000
DTEND;TZID=America/Los_Angeles:20070411T160000
DTSTAMP:20231011T184638Z
CREATED:20231011T184638Z
LAST-MODIFIED:20231011T184638Z
UID:14346-1176303600-1176307200@www.cecs.uci.edu
SUMMARY:New Strategies for System-Level Design
DESCRIPTION:New Strategies for System-Level Design: Where to Go?\nKeynote Talk \n\n\n\n\nSpeaker\n\n\nProfessor Gajski \nElectrical Engineering and Computer Science\nUniversity of California at Irvine\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nThe 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems\, Kraków\, Poland\n\n\n\n \n\n\n \n\n\n\nDate\n\n\nApril 11\, 2007\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nWith complexities of Systems-on-Chip rising almost daily\, the design community has been searching for new vision that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution\, such as increasing levels of abstraction\, introducing variety of IPs or offering new design languages will not solve the problem but only prolong the present status of inefficiency and confusion. What is needed is a drastic change in design automation for complex systems that consist of software and hardware. In order to design such systems efficiently\, we need a new approach with a new design flow\, with new models with well defined semantics and a new formalism that will support system synthesis and verification of software and hardware. \nIn order to find the solution\, we will look first at the system gap between SW and HW designs and derive requirements for the design flow that includes software as well as hardware. In order to enable new EDA tools for model generation\, simulation\, synthesis and verification\, the design flow has to be well defined with unique abstraction levels\, model semantics and model transformations corresponding to design decisions made by the designers. We will introduce the concept of model algebra that supports this approach and can serve as an enabler for the extreme makeover of EDA. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of complex systems to the basic principles of design science only.\n\n\n\n\n\n\n\n\n\n\nSlides\n\n\nDownload slides\n\n\n\n \n\n\n \n\n\n\nBiography\n\n\n  \n\n \n\nDaniel Gajski\, a leader in the areas of embedded systems\, design methodologies and languages\, headed the research teams that created new design concepts\, methodologies\, tools and languages. He was instrumental in developing formalisms such as Y-chart\, and numerous algorithms for high-level synthesis\, the definition of the control-data-flow-graph (CDFG) and finite-state-machine with data (FSMD)\, system level languages such as SpecCharts and SpecC\, and design tools such as SpecSyn and Embedded-System Environment. Many of these concepts have been adapted by academia and industry in the last 25 years. \nGajski directs the UCI Center for Embedded Computer Systems\, with a research mission to incorporate embedded systems into automotive\, communications\, and medical applications. He has authored over 300 papers and numerous textbooks\, including Principles of Digital Design (Englewood Cliffs\, NJ: Prentice Hall\, 1997) that has been translated into several languages. \nHe holds Dipl. Ing. and M.S. degrees in electrical engineering from the University of Zagreb\, Croatia\, and a doctoral degree in computer and information sciences from the University of Pennsylvania\, Philadelphia. After 10 years as Professor at University of Illinois he has joined UCI\, where he presently holds The Henry Samueli Endowed Chair in Computer System Design.
URL:https://www.cecs.uci.edu/event/new-strategies-for-system-level-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070325T150000
DTEND;TZID=America/Los_Angeles:20070325T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14287-1174834800-1174838400@www.cecs.uci.edu
SUMMARY:Operating system kernel as a building block for scalable and fast network topology emulation
DESCRIPTION:Marko Zec\, University of Zagreb\, Croatia5251 California Ave.\, Suite 210 ( CECS Research Park Office)\, Unversity of California\, Irvine\nLecture\, May 25\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/operating-system-kernel-as-a-building-block-for-scalable-and-fast-network-topology-emulation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070316T150000
DTEND;TZID=America/Los_Angeles:20070316T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14241-1174057200-1174060800@www.cecs.uci.edu
SUMMARY:Embedded Control Software Engineering Methods and Tools Research at ISL\, Bangalore
DESCRIPTION:Dr. S. Ramesh\, Technical Fellow\, India Science Lab\, GM R&D Labs\, Bangalore\, IndiaCalit2 Auditorium\, University of California\, Irvine\nMarch 16\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/embedded-control-software-engineering-methods-and-tools-research-at-isl-bangalore/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070309T150000
DTEND;TZID=America/Los_Angeles:20070309T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14242-1173452400-1173456000@www.cecs.uci.edu
SUMMARY:Arithmetic Optimizations for System Design
DESCRIPTION:Dr. Farzan Fallah\, Fujitsu LaboratoriesCalit2 Auditorium\, University of Califonia\, Irvine\, CA\nLecture\, March 09\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/arithmetic-optimizations-for-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070305T150000
DTEND;TZID=America/Los_Angeles:20070305T160000
DTSTAMP:20231011T184246Z
CREATED:20231011T184246Z
LAST-MODIFIED:20231011T184246Z
UID:14335-1173106800-1173110400@www.cecs.uci.edu
SUMMARY:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems
DESCRIPTION:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems\nby Radu Cornea \nRecent advances in processor\, wireless and graphics technology have fueled a convergence of traditional PDA and cellphone functionality into complex\, media-centric mobile devices. A popular class of applications emerging on these platforms is represented by multimedia\, in particular content streaming (video\, audio). However\, all this added functionality has not come without an expense in one of the most important area for a mobile device: battery life. Multimedia streaming in particular\, with its stringent compu tation\, communication and quality of service requirements further aggravates battery life on these already constrained devices. \nOn the other hand\, multimedia applications have very regular execution patterns\, the only changes being introduced by variations in the data stream itself. This thesis presents a new way to optimize power consumption for multimedia applications\, based on content analysis and annotations. Specifically\, we pre-process the multimedia streams and utilize annotations to capture and carry content-related information to the client device at the receiving end. Annotations allow us to perform more accurate and aggressive optimizations\, with knowledge of the actual content and without relying to less accurate prediction models. \nWe investigate the use of annotation for content-aware optimizations at all level of abstraction (hardware/OS\, network\, application) for the most important system components in a mobile device: CPU/memory\, network interface\, display. Our experimental results show that important energy savings can be achieved for all these components through annotations. Finally\, we integrate the techniques at all levels of abstraction for an increased user experience and battery functionality. We also show how cross-layer trade-offs between power and quality can lead to even higher energy savings with minimal quality degradation.
URL:https://www.cecs.uci.edu/event/content-annotation-for-power-and-quality-trade-offs-in-mobile-multimedia-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070222T150000
DTEND;TZID=America/Los_Angeles:20070222T160000
DTSTAMP:20231011T183308Z
CREATED:20231011T183308Z
LAST-MODIFIED:20231011T183308Z
UID:14288-1172156400-1172160000@www.cecs.uci.edu
SUMMARY:Automatic Parallelization with Hybrid Analysis
DESCRIPTION:Dr. Lawrence Rauchwerger\,Texas A&M UniversityCalit2\, Room 3008\, University of Califonia\, Irvine\, CA\nLecture\, February 22\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/automatic-parallelization-with-hybrid-analysis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070220T150000
DTEND;TZID=America/Los_Angeles:20070220T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14289-1171983600-1171987200@www.cecs.uci.edu
SUMMARY:Research Challenges in High Performance VLSI/SoC Circuits and Systems
DESCRIPTION:Professor. Eby G. Friedman\, University of RochesterMcDonnell Douglas Auditorium\, University of Califonia\, Irvine\, CA\nDistinguished Lecture\, February 20\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/research-challenges-in-high-performance-vlsi-soc-circuits-and-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR