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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140923T150000
DTEND;TZID=America/Los_Angeles:20140923T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14418-1411484400-1411488000@www.cecs.uci.edu
SUMMARY:Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture
DESCRIPTION:Title:� Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture\nSpeaker:� Francis Caster II \nLocation/Time:� September 23\, 2014\, 3PM\nCommittee Members:\nPayam Heydari\nFilippo Capolino\nH. Kumar Wickramasinghe\nAbstract: Multi-pixel passive imaging arrays are presently fabricated in expensive processes with low integration levels. Imaging arrays designed in inexpensive processes with higher levels of integration would result in cheaper larger arrays. The objective of this work is twofold: 1) to develop a highly integrated silicon-based passive imaging receiver integrating the entire receiver frontend from antenna to detector; and 2) to develop a highly scalable architecture for use in focal plane arrays of arbitrary dimensions\, incorporating new features to address large-array issues while retaining the pixel density of conventional focal plane arrays. A new area-efficient beam-steerable imaging array receiver architecture suitable to integrated circuit realization up to sub-THz frequencies is presented. A direct-detection-based receiver array utilizing the proposed architecture is designed and implemented in an advanced 0.18�m BiCMOS process. The receiver chip achieves a peak measured coherent responsivity of 1\,150MV/W\, a measured incoherent responsivity of 1\,000MV/W\, a minimum NEP of 0.28fW/sqrtHz and a front-end 3-dB bandwidth from 87-108GHz\, while consuming 225mW per receiver element. The measured NETD of the SiGe receiver chip is 0.45K with a 20ms integration time. The proposed architecture uses a new concept of spatial-overlapping super-pixels which results in (1) improved SNR at the pixel level through a reduction of spillover losses\, (2) partially correlated adjacent super-pixels\, (3) a 2�2 window averaging function in the RF domain\, (4) the ability to compensate for the systematic time delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point\, and (5) the ability to compensate for mutual coupling effects among the array elements.
URL:https://www.cecs.uci.edu/event/design-analysis-and-implementation-of-an-area-efficient-beam-steerable-sub-terahertz-imaging-receiver-array-architecture/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140910T150000
DTEND;TZID=America/Los_Angeles:20140910T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14417-1410361200-1410364800@www.cecs.uci.edu
SUMMARY:Self-interference Cancellation in Full-duplex Wireless Systems
DESCRIPTION:Title:  Self-Interference Cancellation in Full-duplex Wireless Systems \nSpeaker:  Elsayed Ahmed \nDate/Time:  August 28\, 2014\, 10:00AM \nLocation:  Engineering Hall 4106 \nCommittee Members:Ahmed Eltawil (Chair)Ender AyanogluA. Lee Wsindlehurst \nAbstract: Due to the tremendous increase in wireless data traffic\, one of the major challenges for future wireless systems is the utilization of the available spectrum to achieve better data rates over limited spectrum. Currently\, systems operate in what is termed “Half Duplex Mode\,” where they are either transmitting or receiving\, but never both using the same temporal and spectral resources. Full-duplex transmission promises to double the spectral efficiency where bidirectional communications is carried out over the same temporal and spectral resources. The main limitation impacting full-duplex transmission is managing the strong self-interference signal imposed by the transmit antenna on the receive antenna within the same transceiver. Several recent publications have demonstrated that the key challenge in practical full-duplex systems is un-cancelled self-interference power caused by a combination of hardware imperfections\, especially Radio Frequency (RF) circuits’ impairments. In this thesis\, we consider the problem of self-interference cancellation in full-duplex systems. The ultimate goal of this work is to design and build a complete\, real-time\, full-duplex system that is capable of achieving wireless full-duplex transmission using practical hardware platforms. Since RF circuits’ impairments are shown to have significant impact on the self-interference cancellation performance\, first\, we present a thorough analysis of the effect of RF impairments on the cancellation performance\, with the aim of identifying the main performance limiting factors and bottlenecks. Second\, the thesis proposes several impairments mitigation techniques to improve the overall self-interference cancellation capability by mitigating most of the transceiver RF impairments. In addition to impairments mitigation\, two novel full-duplex transceiver architectures that achieve significant self-interference cancellation performance are proposed. The performance of the proposed techniques is analytically and experimentally investigated in practical wireless environments. Finally\, the proposed self-interference cancellation techniques are used to build a complete full-duplex system with a 90% experimentally proven full-duplex rate improvement compared to half-duplex systems.
URL:https://www.cecs.uci.edu/event/self-interference-cancellation-in-full-duplex-wireless-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140910T150000
DTEND;TZID=America/Los_Angeles:20140910T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14416-1410361200-1410364800@www.cecs.uci.edu
SUMMARY:Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor Platforms
DESCRIPTION:Title:  Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor  Platforms \nSpeaker:  Kyoungwon Kim \nDate/Time:  August 28\, 2014\, 2:oopm \nLocation:  Engineering Hall 3206 \nCommittee Members:Daniel Gajski (Chair)Tony Givargis Rainer Doemer \nAbstract:  Embedded system designers continuously face a twofold challenge handling the ever-increasing complexity of design and meeting the ever-shrinking time-to-market timeline. To meet such a challenge\, the system design paradigm has shifted to platform-based design characterized by intensive use of software and aggressive reuse of verified components. More and more designs are turning to heterogeneous platforms to meet design constraints in multiple criteria. However the use of such and heterogeneity generates more challenges for platform-based design. To address the challenges\, system designers must utilize system-level methodologies for specification and design. Here the designers begin the design process by coming up with a computation model that captures the behavior of the system. The computation model is successively refined down to the structural model in the system level. In each refinement\, the designers explore the design space. The design space comprises a set of alternatives concerning hardware/software partitioning\, platform selection\, and mapping. The design space is huge\, however\, necessitating the automation of its exploration. The platform is very often fixed regarding either availability or legacy reasons\, making mapping crucial. This dissertation focuses on the automatic mapping of the computation model for the given heterogeneous platform. This dissertation presents a new automatic mapping technique based on the input computation model. The proposed technique consists of two separate phases: initial mapping and improvement driven by cycle-approximate estimation. Existing mapping techniques depend on early estimation so a dilemma arises from the fact that cycle-approximate estimation cannot precede mapping. The dilemma can be gotten around by our performing initial mapping based on rough estimation and then making iterative improvements based on cycle-approximate estimation. While earlier work has been domain specific\, the mapping techniques in the proposed work are driven by a general computation model that includes hierarchy\, state transitions\, dynamic data-oriented behaviour\, and imperative languages\, while previous work is domain specific.The proposed work also addresses mapping with an awareness of general hierarchy in pipelined applications. The size of the design space explored is limited by the speed of cycle-approximate estimation. Orders of magnitude faster than Simulation-based cycle-approximate estimation\, the new trace-driven estimation presented in this disseration is cycle-approximate and applicable to both software and hardware. The new trace-driven estimation assumes that the execution path of each task depends on data only. As the trace-driven estimation handles a portion of applications\, it complements the existing simulation-based cycle-approximate estimation. We have applied the proposed mapping techniques to multiple multimedia applications and the techniques outperformed in terms of execution time the competitors by proportions ranging from 23.3% through 36.3%.
URL:https://www.cecs.uci.edu/event/computation-model-based-automatic-design-space-exploration-for-heterogeneous-multiprocessor-platforms/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140723T150000
DTEND;TZID=America/Los_Angeles:20140723T160000
DTSTAMP:20231011T190437Z
CREATED:20231011T190437Z
LAST-MODIFIED:20231011T190437Z
UID:14414-1406127600-1406131200@www.cecs.uci.edu
SUMMARY:New Circuit Techniques Enabling Millimeter-Wave and Terahertz Transceivers in Nonoscale Silicon
DESCRIPTION:Title:  New Circuit Techniques Enabling Millimeter-Wave and Terahertz Transceivers in Nonoscale Silicon \nSpeaker:  Zheng Wang \nDate/Time:  Monday\, June 2\, 2014\, 2:00PM \nLocation:  Engineering Hall 2111 \nCommittee Members:Payam Heydari (Chair)Michael GreenEnder Ayaloglu \nAbstract: The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device _fT_/_fmax_\, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. This dissertation mainly focuses on the design of a 210GHz fundamental transceiver and also covers the design of a W-band fully integrated imaging system utilizing a novel concept of spatial-overlapping super pixels.Firstly\, a 210GHz transceiver with OOK modulation in a 32nm SOI CMOS process is presented. The transmitter (TX) employs a 2´2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillator (VCO) at 210GHz with an on-off-keying (OOK) modulator\, a power amplifier (PA) driver\, a novel balun-based differential power distribution network\, four PAs and an on-chip 2´2 dipole antenna array. The non-coherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna\, a low noise amplifier (LNA)\, and a power detector. The VCO generates measured -13.5dBm output power; and the PA shows a measured 15dB gain and 4.6dBm Psat. The LNA exhibits a measured in-band gain of 18dB and minimum in-band noise figure (NF) of 11dB. The TX achieves an EIRP of 5.13dBm at 10dB back-off from saturated power. It achieves an estimated EIRP of 15.2dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200GHz frequency range. \nSecondly\, a W-band direct-detection-based receiver array in an advanced 0.18µm BiCMOS process is presented\, which incorporates a new concept of spatial-overlapping super-pixels for millimeter-wave imaging\napplications. The use of spatial-overlapping super-pixels results in (1) improved SNR at the pixel level through a reduction of spillover losses\, (2) partially correlated adjacent super-pixels\, (3) a 2×2 window\naveraging function in the RF domain\, (4) the ability to compensate for the systematic phase delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point\, and (5)\nthe ability to compensate for mutual coupling effects among the array elements. The receiver chip achieves a measured peak coherent responsivity of 1\,150MV/W\, an incoherent responsivity of 1\,000MV/W\, a\nminimum noise-equivalent power (NEP) of 0.28fW/√Hz and a front-end 3-dB bandwidth from 87-108GHz\, while consuming 225mW per receiver element. The measured noise-equivalent temperature difference (NETD) of the SiGe\nreceiver chip is 0.45K with a 20ms integration time.\n\n 
URL:https://www.cecs.uci.edu/event/new-circuit-techniques-enabling-millimeter-wave-and-terahertz-transceivers-in-nonoscale-silicon/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140723T150000
DTEND;TZID=America/Los_Angeles:20140723T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14413-1406127600-1406131200@www.cecs.uci.edu
SUMMARY:Performance-Optimized Terahertz Signal Sources in Silicon
DESCRIPTION:Title:  Performance-Optimized Terahertz Signal Sources in Silicon \nSpeaker:  Pei-Yuan Chiang \nDate/Time:  Monday\, June 2\, 2014\, 10:00AM \nLocation: Engineering Hall 2111 \nCommittee Members:Payam Heydari (Chair)Michael GreenOzdal Boyraz \nAbstract: Terahertz (THz) and sub-millimeter wave band are known to provide unique applications in spectroscopy\, imaging and high-data-rate wireless communication. An imaging system operating in this frequency region exhibits non-invasive and high-resolution characteristics due to the non-ionized and short-wavelength radiation waves\, which makes it attracting for security surveillance. On the other hand\, the THz wireless transceiver operating in the license-free spectrum is capable of achieving tens of gigabits-per-second by utilizing a simple modulation scheme. All the benefits mentioned above make THz a promising research topic. Towards realization of a high-performance THz system\, one of the most challenging steps is to design a frequency synthesizer. \nA voltage-controlled oscillator (VCO) is one of the important building blocks within a synthesizer. Due to the server performance degradation of varactors and transistors at high frequencies\, new ways of designing VCOs need to be investigated. Here\, two different ideas are proposed. First\, an inductive-tuning mechanism with high quality-factor and wide tuning-range is introduced. This tuning technique is based on a variable inductor seen at the emitter terminal of a base-degenerated transistor. By adding a series RL at the base terminal\, the variable inductor\, exhibiting low loss and high tunability\, improves the VCO output power and phase noise while achieving a wide tuning range. The second idea\, double-stacked cross-coupled VCO\, is to design a strong negative resistance cell to compensate for the server loss of the varactor at THz frequencies. By implementing a source-degenerated negative resistor of a conventional cross-coupled pair\, the overall negative resistance is enhanced. It also reduces the parasitic capacitance\, making it an attracting approach for THz applications. \nFinally\, a novel THz frequency synthesizer is proposed. A 300GHz phase-locked-based synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a three-phase injection locked divider is introduced. The CAV is used to tune the oscillation frequency\, enhance output power\, and buffer the VCO’s fundamental signal. The divider’s locking-range is vastly increased attribute to the three-phase injection. This work demonstrates the highest-frequency synthesizer in silicon.
URL:https://www.cecs.uci.edu/event/performance-optimized-terahertz-signal-sources-in-silicon/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140712T150000
DTEND;TZID=America/Los_Angeles:20140712T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14415-1405177200-1405180800@www.cecs.uci.edu
SUMMARY:New Perspectives on Designing An Effective Management Policy for Multi-level Cache Hierarchy
DESCRIPTION:Date/Time:  February 25\, 2014\, 3:00PM \nLocation:  DBH 3011 \nCommittee Members:Alexander V. Veidenbaum (Chair)Alexandru NicolauTony GivargisRainer Doemer \nAbstract: Designing an effective cache management policy for a multi-level cache hierarchy has been a hot research topic to bridge the gap between the fast microprocessor and the long memory latency. It is becoming critically important in modern microprocessors due to the emerge of new hardware architectures\, new technologies and new applications. However\, it has been shown that this is not an easy task due to the complexity of the inputs that computer architects must take into account. \nThe bottom-up approach has been used in designing such a policy. Rather than tackling the problem with all the possible inputs\, a management policy is broken down into smaller problems\, each targeting a smaller number of inputs. Sub-policies\, such as replacement\, bypass\, migration and partitioning\, are studied for a specific event or configuration. Solutions have been proposed for these individual policies or their combinations. In either case\, the new policies must be shown to work well with existing baseline policies. \nIn this dissertation\, using the bottom-up approach\, we propose new management policies for a multi-level cache hierarchy. Using new ideas about an effective policy or improving existing methods for new hardware architectures\, we further optimize the current state-of-the-art policies. Specifically\, we propose three new sets of management policies. First\, new migration policies are proposed for an L0/L1 cache hierarchy for embedded processors. We propose two new cache designs to enhance operations of the L1 caches. Second\, we propose a new combined replacement\, bypass and partitioning policy for a last-level cache by achieving the balance between cache reuse and pollution. The new policy is shown to reduce pollution due to keeping cache lines too long in the cache\, a problem which was not addressed by prior work. And third\, we propose a new coordinated bypass policy for a multi-level cache hierarchy using the new classifications of cache lines and their reuse probabilities. This policy works well with any existing policies and architectures which allow bypass. \nThe new cache management policies are shown to improve existing policies or optimize the design with an acceptable performance loss. They are shown to work well with the baseline policies. We also present hardware architectures and application classes that each new policy will be applied to. Hardware design is also described and is shown to be feasible and have low overhead.
URL:https://www.cecs.uci.edu/event/new-perspectives-on-designing-an-effective-management-policy-for-multi-level-cache-hierarchy/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130827T150000
DTEND;TZID=America/Los_Angeles:20130827T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14412-1377615600-1377619200@www.cecs.uci.edu
SUMMARY:Cognitive Power Management and Error Resilient Algorithms for Memory Dominated Wireless Communication Systems
DESCRIPTION:Date/Time:  Friday\, August 23\, 2013 \nLocation:  Engineering Hall 4106 \nCommittee Members:Ahmed Eltawil (Chair)Fadi KurdahiA. Lee Swindlehurst \nAbstract: \nAdvanced CMOS technology exhibits increasing variations in performance\, power consumption and reliability parameters. These variations led to extensive overdesigning and increased power consumption to guarantee 100% reliable operation. However\, with the continuous shrinking of device parameters\, future semiconductor industry needs to shift from the assumption of 100% reliable computation to a fault-tolerant approach. Fortunately\, many important application domains such as communication and multimedia are inherently error-aware\, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. Specifically\, embedded memories in communication systems are perfect candidates for exploring error-aware designs\, since the share of the System-on-Chips (SoCs) that is dedicated to memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoCs for wireless standards such as Long-Term Evolution (LTE)\, Digital Video Broadcasting (DVB)\,  and Worldwide Interoperability for Microwave Access (WiMAX). Furthermore\, a large portion of the memory is typically used for buffering data that already has a high level of redundancy (e.g. buffering memories in wireless chips). In the context of wireless communication systems\, given that the incoming buffered data is already corrupted by time varying noise and interference\, there is no need to store the data samples in memories that are error free\, 100% of the time. Rather\, Voltage over-scaling (VoS) techniques can be adopted as an efficient means to achieve energy efficient systems via trading off reliability versus power.  However\, reducing the supply voltage of buffering memory through VoS results in spatially uniform random errors which in turn corrupt the stored data in the buffering memories and increase the noise floor. \nIn this thesis\, the predominance of embedded memories in current and emerging wireless transceivers is utilized as a means to save power via channel state aware voltage scaling. While the wireless channel is a stochastic channel where the designer has little control on its variables\, embedded memories are considered as an extension of the channel where the designer can control its quality via VoS. The thesis presents a unified statistical model that captures both errors in embedded memories due to voltage over-scaling and wireless channel impairments into a single Gaussian distribution model that represents a combination of communication channel noise and hardware noise. The proposed model is used to investigate different cognitive power management policies that capture the performance of the system as a function of both channel and hardware dynamics\, thus creating a much richer design space of power\, performance and reliability. Furthermore\, based on that model\, error-resilient algorithm for Viterbi decoder\, multiple input multiple output (MIMO) detector and memory-based computation are presented.
URL:https://www.cecs.uci.edu/event/cognitive-power-management-and-error-resilient-algorithms-for-memory-dominated-wireless-communication-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130726T150000
DTEND;TZID=America/Los_Angeles:20130726T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14411-1374850800-1374854400@www.cecs.uci.edu
SUMMARY:System Level Approaches for Low Power Wireless Architectures
DESCRIPTION:Date/Time:  Thursday\, August 1\, 2013 \nLocation:  Engineering Hall 4106 \nCommittee Members:Professor Ahmed Eltawil (Chair)Professor Fadi KurdahiProfessor Nikil Dutt \nAbstractThere are emerging needs to build energy efficient platforms to support co-operation between heterogeneous wireless networks. This necessitates building efficient frameworks for reconfigurable platforms that can support seamless reconfiguration among different wireless scenarios. Towards achieving that goal\, this thesis addresses the problem of building energy efficient wireless architectures from two perspectives. First\, we develop a high level framework that generates a reconfigurable MPSoC architecture from a library of heterogeneous processing resources that can be reconfigured to support various modes of operation. The framework proposes joint task and core mapping with system level floorplanning. With the objective of minimizing energy\, we develop an analytical probabilistic model that considers static\, dynamic\, reconfiguration and communication energy components for multiple applications characterized by certain probabilities of execution. Fast and efficient heuristics have been developed that can achieve solutions very close to those obtained via optimal solvers\, with several orders of magnitude speedup. \nWhile\, the first perspective focused on system level solutions\, the second perspective focuses on the block level optimizations. It utilizes the fact that the use of embedded memory in its various forms and implementations for cellular base-stations and mobile handhelds has experienced unprecedented growth recently\, significantly affecting area and power consumption metrics. Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories\, which allows acceptable hardware errors to flow through the processing chain as a cost of considerable power savings. This thesis presents a model that captures the statistics of both channel noise and buffering memory failures. Furthermore\, it introduces modified forward error correction (FEC) decoders that are aware of both the channel errors as well as the buffering memory errors. The decoding maximizes the likelihood of the received data based on the statics of the combined channel and buffering memory noise. The idea is applicable to three widely used FEC decoders; namely Viterbi\, Turbo\, and LDPC decoders. The modified decoders are able to preserve the system performance very close to the hardware error-free case with negligible area overhead in implementation.
URL:https://www.cecs.uci.edu/event/system-level-approaches-for-low-power-wireless-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190419Z
CREATED:20231011T190419Z
LAST-MODIFIED:20231011T190419Z
UID:14409-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Exploiting Master-Slave Bus Architecture and Storage Devices to Enable High-Performance\, Low-Power Logging for Sensor Systems
DESCRIPTION:By Eunbae YoonJune 24\, 2013 \nread more
URL:https://www.cecs.uci.edu/event/exploiting-master-slave-bus-architecture-and-storage-devices-to-enable-high-performance-low-power-logging-for-sensor-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14408-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Optimizing Program Performance via Similarity\, Using Feature-aware and Feature-agnostic Characterization Approaches
DESCRIPTION:By Rosario CammarotaMay 31\, 2013 \nread more
URL:https://www.cecs.uci.edu/event/optimizing-program-performance-via-similarity-using-feature-aware-and-feature-agnostic-characterization-approaches/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190344Z
CREATED:20231011T190344Z
LAST-MODIFIED:20231011T190344Z
UID:14402-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Out-of-order Parallel Discrete Event Simulation for Electronic System-Level Design
DESCRIPTION:Date/Time: Thursday\, June 6th\, 10:00 a.m. – 11:00 a.m.Location: CECS Conference Room\, Engineering Hall 3206 \nCommittee Members:Rainer Dömer (Chair)Daniel GajskiBrian Demsky \nAbstractThe large size and complexity of the modern embedded systems poses great challenges to design and validation. At the so called electronic system level (ESL)\, designers start with a specification model of the system and follow a systematic top-down design approach to refine the model to different abstraction levels by adding step-by-step implementation details. ESL models are usually written in C-based System-level Description Languages (SLDLs)\, and contain the essential features such as clear structure and hierarchy\, separate computation and communication\, and explicit parallelism. The validation of ESL models typically relies on simulation. Fast yet accurate simulation is highly desirable for efficient and effective system design. \nThe out-of-order parallel discrete event simulation (OoO PDES) is a novel approach for efficient validation of system-level designs by exploiting the parallel capabilities of todays multi-core PCs for system level description languages. OoO PDES breaks the global simulation-cycle barrier of traditional DE simulation by localizing the simulation time into each thread\, carefully delivering notified events\, and handling a dynamic management of simulation sets. Potential conflicts caused by parallel accesses to shared variables and out-of-order thread scheduling are prevented by an advanced predictive static model analyzer in the compiler. As such\, OoO PDES allows the simulator to effectively exploit the parallel processing capability of the multicore system to achieve fast speed simulation without loss of simulation and timing accuracy. \nWe perform simulation experiments on both highly parallel benchmark examples and real- world embedded applications including a JPEG image encoder\, an edge detector\, a MP3 audio decoder\, a H.264 video decoder\, and a H.264 video encoder. Experimental results show that our approach can achieve significant simulation speedup on multicore simulation hosts with negligible compilation cost. \nBased on our parallel simulation infrastructure\, we then propose a tool flow for dynamic race condition detection to increase the observability for parallel ESL model development. It helps the designer to quickly narrow down the debugging targets in faulty ESL models with par- allelism. This approach helps to reveals a number of risky race conditions in our in- house embedded multi-media application models and enabled us to safely eliminate these hazards. Our experimental results also show very little overhead for race condition diagnosis during compilation and simulation. \nOverall\, our work provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development. It helps the embedded system designers to build better products in shorter time-to-market.
URL:https://www.cecs.uci.edu/event/out-of-order-parallel-discrete-event-simulation-for-electronic-system-level-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14404-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:The Delft Reconfigurable VLIW Processor
DESCRIPTION:Speaker: Prof. Stephan Wong\, Computer Engineering Laboratory\, Delft University of Technology\, NetherlandsTitle: The Delft Reconfigurable VLIW ProcessorDate: Tuesday\, March 26\, 2013Time: 2:00pm – 3:00pmLocation: 2111 Engineering Hall \nHost: Prof. Fadi Kurdahi \nView Details \nAdditional information
URL:https://www.cecs.uci.edu/event/the-delft-reconfigurable-vliw-processor/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14405-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Functionality\, Performance\, and Power Consumption Challenges in Smartphones
DESCRIPTION:Speaker: Prof. Sung-Soo Lim\, Kookmin University\, South KoreaTitle: Functionality\, Performance\, and Power Consumption Challenges in SmartphonesDate: Friday\, April 12\, 2013Time: 11:00am – 12:00pmLocation: Donald Bren Hall 6011 \nHost: Prof. Eli Bozorgzadeh \nView Details
URL:https://www.cecs.uci.edu/event/functionality-performance-and-power-consumption-challenges-in-smartphones/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14406-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Models and Architectures for Heterogeneous System Design
DESCRIPTION:Speaker: Prof. Andreas Gerstlauer\, University of Texas\, AustinTitle: Models and Architectures for Heterogeneous System DesignDate: Monday\, May 6\, 2013Time: 11:00am – 12:00pmLocation: Harut Barsamian Colloquia Room (2430 Engineering Hall) \nHost: Prof. Rainer Dömer \nView Details
URL:https://www.cecs.uci.edu/event/models-and-architectures-for-heterogeneous-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14407-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Evaluating GALS Systems for System Integration-Outlook and Future Prospects
DESCRIPTION:Speaker: Dr. Milos KrsticDate: Friday May 17\, 2013Time: 2:00pm – 3:00pmLocation: Donald Bren Hall 4011 \nHost: Dr. Steffen Peter \nView Details
URL:https://www.cecs.uci.edu/event/evaluating-gals-systems-for-system-integration-outlook-and-future-prospects/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190344Z
CREATED:20231011T190344Z
LAST-MODIFIED:20231011T190344Z
UID:14403-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Distinguished Lecture at CECS
DESCRIPTION:Speaker: Prof. Jorg Henkel\, Karlsruhe Institute of Technology\, GermanyTitle: A Thermal Perspective of Dependability in Systems on ChipDate: Monday\, February 25\, 2013Time: 11:00am – 12:00pmLocation: Harut Barasmian Colloquia Room (EH 2430) \nHost: Prof. Daniel Gajski \nView Details
URL:https://www.cecs.uci.edu/event/distinguished-lecture-at-cecs/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130524T150000
DTEND;TZID=America/Los_Angeles:20130524T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14401-1369407600-1369411200@www.cecs.uci.edu
SUMMARY:Designer-in-the-Loop Recoding for Creating Safe and Parallel ESL Models
DESCRIPTION:Date/Time: Thursday\, May 30\, 2013\, 10:00 a.m. – 11:00 a.m.Location: CECS Conference Room\, Engineering Hall 3206 \nCommittee Members:Rainer Dömer (Chair)Daniel GajskiFadi Kurdahi \nAbstractThe design complexity of embedded systems increases as more processors and subsystems integrated on one chip. In order to overcome the design bottlenecks and shorten time to market\, system engineers are motivated to design from a higher abstraction level\, namely Electronic System Level (ESL). ESL design methodology has emerged to address the design complexity by supporting HW/SW co-specification and co-simulation\, system design space exploration and high-level synthesis. \nESL design relies on an input ESL model\, namely the specification model. Creating structured and parallel specification models efficiently is a prerequisite for building cost-effective embedded systems in ESL design. Practically\, application reference code is reused to create the ESL models. However\, the referee models lack the necessary characteristics\, such as explicit parallelism\, structural hierarchy and synthesizability\, for ESL design. It is a time-consuming and error-prone process to manuallyrecode the reference models into desired ESL models. \nThis dissertation addresses on the automation gap of recoding. We follow the design-in-the-loop recoding methodology which efficiently combines the automation tools with designer’s knowledge. Our approach aim to expose parallelism in the ESL model and guarantee that the parallel model is safe from race conditions. \nFirst\, we identifies the essential steps in recoding and defines a recoding design flow to create safe and parallel ESL models.Second\, we contribute three automated recoding operations: variable dependency analysis to provide prompt analysis during model development\, race condition analysis to assist verifying and debugging the parallelism and a high-level transformation function to instantly create loop-level parallelism. Third\, we develop a recoding development platform based on Eclipse tointegrate recoding tools and facilitate the designer-in-the-loop approach. \nThe effectiveness of the recoding functions is shown with experiments on a set of embedded applications. Also\, an classroom experiment with 68 graduate students shows our recoding approach using the Eclipse-based recoding platform increases the productivity and reduces errors in parallel ESL model development.
URL:https://www.cecs.uci.edu/event/designer-in-the-loop-recoding-for-creating-safe-and-parallel-esl-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130520T150000
DTEND;TZID=America/Los_Angeles:20130520T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14410-1369062000-1369065600@www.cecs.uci.edu
SUMMARY:Context-based Service Performance Profile Management System in SOA
DESCRIPTION:Date/Time:  Tuesday\, May 28th\, 2:00 p.m. – 3:00 p.m. \nLocation:  Engineering Hall 4106 \nCommittee Chair:Kwei-Jay Lin \nAbstractService-Oriented Architecture (SOA) is a software paradigm for providing a uniform means to discover\, interact with and use capabilities to produce desired effects consistent withmeasurable preconditions and expectation. SOA also provides a framework for service com-position by putting together of a number of services to make a more complex one to fulfill a business process and service reconfiguration by replacing faulty services with better perform-ing services to have seamless business process execution. In general\, service integration tries to maximize the performance of a business process such as to have a minimum latency\, the shortest response time\, the optimal reliability\, an acceptable level of security and so on. Al-though technology exists to optimize the performance in terms of the above QoS attributes\, it still may not meet the need of all users\, since user may have unique service requirement at some specific context. \nIn order to address this issue\, in this dissertation\, we present an approach to improve over-all performance for the execution of business process by considering context-based serviceperformance profile management through Context Manager. Context Manager is designed to collect service performance feedback from users along with their context data\, maintainservice performance profile data\, distinguish influential context for service performance\, pre-dict how the service would perform under user context and provide most-adaptive service for user context.Our experiment results indicate that context manager system effectively maintains service performance profile data\, clearly understands the influence of some specific context attributes on service performance and provides context-adaptive services as users expect. Moreover\, integrating context-awareness into SOA brings significant performance improvement in terms of lower rate of service failure and reconfiguration\, and more optimal response time between service requester and service provider.
URL:https://www.cecs.uci.edu/event/context-based-service-performance-profile-management-system-in-soa/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130513T150000
DTEND;TZID=America/Los_Angeles:20130513T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14400-1368457200-1368460800@www.cecs.uci.edu
SUMMARY:Embedded Computer Vision Systems for Image Based Motion and Speckle Image Analysis
DESCRIPTION:Date/Time:  Friday\, May 10\, 2013\, 2:00 p.m. – 3: 00p.m.Location:  4011 Donald Bren Hall \nCommittee Members:\nPai H. Chou (Chair)\nBernard Choi\nGlenn Healey\n \nAbstract:  Motion is common in taking images using conventional cameras. If there is motion either on camera or the object or on the both sides during the exposure time\, the image is blurred\, which is called motion blurred image. Motion blurred image is an interesting research subject in several areas including computer vision\, biomedical engineering. In general\, motion is undesirable to acquire clear image. Modern cameras are equipped with the mechanical structure to compensate motion artifact. However\, mechanical structure has limit in compensating huge motion. To compensate huge motion\, computer vision algorithm called motion deblurring is developed. Basically\, it estimates the best latent image from the blurry image using several assumptions (or priors) on the latent image and camera motion. The information included in the motion blur can be useful for biomedical applications. Laser speckle imaging is one good example. When laser light of certain frequency (visible laser is widely used) is illuminated on the skin\, the scattered laser light from the surface has random distribution if there is no motion. With motion\, the speckle pattern is interfered by the motion and no longer random for the region with motion. Since the laser light can penetrate into skin\, it is possible to measure blood perfusion near skin without invasion. Both motion deblurring and laser speckle imaging require huge computation time. That is the reason why they are developed on personal computers or workstations. However\, the physical size\, power consumption\, and cost make them harder to penetrate into wider-range of applications (e.g. A super-fast motion deblurring algorithm that can run on embedded platforms like portable digital cameras or smart phones or portable laser speckle imaging system for an emergency vehicle). Nowadays\, embedded processors become more and more powerful. The CPU clock frequency of those processors have already passed 1Ghz. Some of them use multiple number of cores for processing like x86 processors. However\, even with such high performance processors\, special design considerations are required. In this dissertation\, we suggest embedded hardware and software systems for motion deblurring and laser speckle imaging applications. In the first part of the dissertation\, we will discuss about our motion deblurring systems. We developed an extremely light-weight motion deblurring algorithm to make it fast enough to be suitable for embedded computing platforms. The developed algorithm is up to 100 times faster than the most recent deblurring algorithms. We also developed a hardware/software system for extremely accurate motion deblurring. The hardware system is composed of IMU\, a control board\, and the Microsoft Kinect. Using the hardware system and software algorithm\, our system can reconstruct the relative motion of each pixel during the exposure time with 6-DoF. The second part is about the embedded laser speckle imaging systems that we developed. The mobile LSI (mLSI) system is a battery-powered laser speckle imaging system to meet the portability requirements of special applications (e.g. emergency vehicle\, battle field). We designed the automated power control (APC) circuit based laser diode driver to reduce the power consumption while maintaining the accuracy of the data. We evaluated the pulsed operation of the laser diode with always-on operation using the driver. The mLSI system showed equivalent performance from the evaluation with the clinical LSI system. The small field of view of conventional LSI systems is not adequate to be used for the applications that require fast treatment on large area (e.g. burn wounds). The multi-camera LSI (mcLSI) system was developed to address the requirement. mcLSI shows significant improvement in spatio-temporal resolution over conventional LSI systems. The unit based design enables users to expand the FoV without the sacrifice of the system performance (e.g. average speckle contrast\, spatial/temporal resolution).
URL:https://www.cecs.uci.edu/event/embedded-computer-vision-systems-for-image-based-motion-and-speckle-image-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130508T150000
DTEND;TZID=America/Los_Angeles:20130508T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14399-1368025200-1368028800@www.cecs.uci.edu
SUMMARY:Cooperative Communication for Wireless Physical Layer Security
DESCRIPTION:Date/Time: Friday\, May 10\, 2013\, 11:00 a.m. – 12:00 p.m.Location: 3206 Engineering Hall  \nCommittee Members:Professor A. Lee Swindlehurst (Chair)Professor Ender AyanogluProfessor Ahmed Eltawil \nAbstract:Cooperative communication in relay networks facilitates high spectral efficiency and large wireless transmission coverage. Despite the advances of improved cooperative diversity and flexible node deployment\, the relay network has more transmission nodes exposed in wireless environment than conventional single hop network\, and also extends the area over which the private transmitted signals may be intercepted by unintended receivers or eavesdroppers. Unlike the traditional approach of cryptographic design in the application layer\, in this work we investigate security issues in relay networks from a physical layer perspective. \nWe start with a two-hop multiple-input multiple-output (MIMO) relay network and propose cooperative beamforming and jamming strategies to maximize the secrecy rate. The corresponding power allocation is also optimized via geometric programming. Both cases with known and unknown eavesdropper’s channel state information (ECSI) are considered. Next\, we study a case where the relay is untrusted although it helps with forwarding message to the destination. The exact secrecy outage probability (SOP) is characterized with the impact of the number of antennas at the relay. Antenna selection\, beamforming and node selection schemes are proposed to suppress the wiretapping ability of the untrusted relay. Then we consider utilizing a buffer-aided relay that can dynamically control its receive and transmit phases. A link selection scheme that takes into account both the two-hop transmission efficiency and security constraints is proposed and shown to significantly improve the secrecy throughput. Finally\, we study robust transmit design when the relay acts as a pure cooperative jammer. The ECSI is assumed to be partially known and norm-bounded. The transmit covariance matrices are optimized via semidefinite programming\, based on maximizing the worst-case secrecy rate. Through this work\, we show that by taking advantage of the features of relay networks\, the security performance can be significantly improved in terms of secrecy rate and secrecy outage probability.
URL:https://www.cecs.uci.edu/event/cooperative-communication-for-wireless-physical-layer-security/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130322T150000
DTEND;TZID=America/Los_Angeles:20130322T160000
DTSTAMP:20231011T190322Z
CREATED:20231011T190322Z
LAST-MODIFIED:20231011T190322Z
UID:14398-1363964400-1363968000@www.cecs.uci.edu
SUMMARY:Delft Reconfigurable VLIW Processor
DESCRIPTION:Speaker: Prof. Stephan Wong\, Computer Engineering Laboratory\, Delft University of Technology\, NetherlandsLocation: 2111 Engineering HallDate/Time: Tuesday\, March 26\, 2013\, 2:00pm to 3:00pmView Details 
URL:https://www.cecs.uci.edu/event/delft-reconfigurable-vliw-processor/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130221T150000
DTEND;TZID=America/Los_Angeles:20130221T160000
DTSTAMP:20231011T190321Z
CREATED:20231011T190321Z
LAST-MODIFIED:20231011T190321Z
UID:14396-1361458800-1361462400@www.cecs.uci.edu
SUMMARY:A Thermal Perspective of Dependability in Systems on Chip
DESCRIPTION:Speaker: Prof. Jörg Henkel\, Karlsruhe Institute of Technology\, GermanyLocation: Harut Barsamian Colloquia Room (EH 2430)Date/Time: Monday\, February 25\, 2013\, 11:00am to 12:00pmView Details
URL:https://www.cecs.uci.edu/event/a-thermal-perspective-of-dependability-in-systems-on-chip/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130220T150000
DTEND;TZID=America/Los_Angeles:20130220T160000
DTSTAMP:20231011T192456Z
CREATED:20231011T190320Z
LAST-MODIFIED:20231011T192456Z
UID:14395-1361372400-1361376000@www.cecs.uci.edu
SUMMARY:Introduction to Consumer Computing
DESCRIPTION:Speaker:  Prof. Sinisa SrbljicLocation: Harut Barsamian Colloquia Room (EH 2430)Time/Date: Monday\, February 4\, 2013\, 11:00am-12:00pmView Details
URL:https://www.cecs.uci.edu/event/introduction-to-consumer-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130220T150000
DTEND;TZID=America/Los_Angeles:20130220T160000
DTSTAMP:20231011T193347Z
CREATED:20231011T190319Z
LAST-MODIFIED:20231011T193347Z
UID:14394-1361372400-1361376000@www.cecs.uci.edu
SUMMARY:An Online Methodology For Individualized Education
DESCRIPTION:by Daniel D. Gajski\, Quoc-Viet Dang\, and WenLiang He \nIntroduction\nOnline courses\, the latest hot topic in education\, have been debated by various sources\, including Governor Jerry Brown\, the UC regents\, and numerous college administrators\, faculty\, and students. The motivation behind such discussion is varied. Administrators see offering online courses as a way to increase the number of students despite the shortage of large lecture halls\, while generating some financial savings. Faculty and students are more skeptical\, fearing they will miss the face to face student-lecturer interaction in and out of the classroom. Of course\, with some traditional in-class courses\, having hundreds of students with varying backgrounds and motivation\, the student-lecturer interaction has already been severely diminished from smaller classroom sizes\, which are no longer feasible due to the shrinking educational budget. Since there is no standard in online education\, it has produced erratic results in terms of student performance and costs to students as well as administration. \nHowever\, online tools\, if managed and prepared for properly\, have the opportunity to provide the highly regarded individualized learning experience of the small classroom with the lower costs of large lecture halls while decreasing overall overhead costs. In fact\, the tools used for online courses can be utilized to improve the existing traditional classroom dynamic. Students are trained from high school to prepare for testing by memorizing as many facts and examples as possible in order to answer each question. On the other hand\, college professors tend to follow a top-down approach in teaching where they cover concepts\, some math or algorithms\, and methods or processes of finding proper solutions. These processes\, especially in Engineering\, must be understood and not just memorized because they have many steps involved: specification\, analysis\, design and synthesis\, optimization\, verification\, implementation\, and testing. In a small college classroom of 20-30 students\, lecturers can help students who fall behind individually by expending their out-of-class time. In a larger class of 150 students or more\, the small classroom teaching style doesn’t work as well since the time commitment for both the lecturer and students are dramatically increased for the same duration of time. \nThe tools and methodology presented in this article aid in providing the small classroom experience in a much larger setting while keeping overall costs and time commitment down. Such tools and methodology can be applied to any learning environment\, not just online\, to better prepare students for learning concepts and solving problems. It must cover \n(a)   Lectures \n(b)   Sample problems with solutions \n(c)   Questions and answers \n(d)   Homework \n(e)   Tests \nImproving a Typical In-Class Environment\nWe will compare the typical teaching methodology for a large classroom with a modified methodology that utilizes online tools to provide a richer learning environment for students. Our initial research compares two groups of students (Group A & Group B) taking a Digital Logic Design Engineering course during two separate quarters. Online course material consisted of custom content developed specifically for this Digital Design course as well as existing UCI tools through EEE (Electronic Educational Environment). We compare the students across 3 exams: \nExam 1: Both groups are taught based on a typical teaching methodology (overviewed below). Online lecture videos are available but no special emphasis is given to them. All material is covered in lecture and/or discussion sections. This exam is used to normalize the results for the following two exams. \nExam 2: Group A continues to be taught using the typical teaching methodology. Group B is presented with a typical Online course methodology. All lectures & samples are to be reviewed online via online videos. In-class lecture & discussion sections are now treated like online meetings; the professor and teaching assistants only cover questions asked and do not repeat any lectures. \nExam 3: Group A continues to be taught the typical teaching methodology. Group B is presented with a hybrid methodology based on in-class and online processes. A general lecture is given per topic each classroom session. Students are expected to review specific details and caveats that are covered by online videos & submit questions before the next classroom session. In the following lecture or discussion\, specific questions are answered that are submitted by students\, similar to an online course web meeting. \nA Typical In-Class Learning Environment\nThe in-class teaching environment was originally developed for small classes (20-40 students). However\, enrollment in many college courses has grown to over 100 students per class. Lectures for a couple hundred students in a large lecture hall for 1-2 hours are very difficult because \n(a)   schedulers have problems with room sizes and cannot schedule too many short lectures or discussions. \n(b)   a single presentation needs to cater to the varying skill levels and knowledge of all 100-200 students. \n(c)   many students are not prepared and have no questions\, exacerbating the above situations. Much of the information the students need is presented once in a lecture and/or discussion. If they miss the lecture or get lost on a concept taught\, they fall further and further behind as the class progresses. \nTherefore\, the presentation is general and not helpful to many students with weak backgrounds or insufficient skills while leaving other students bored and non-attentive. To help alleviate some of these issues\, sample problems can be covered in discussion sections with fewer students\, but the above situation still applies\, just on a smaller scale. Weekly homework is assigned to keep students on track; however\, due to learning habits from students’ past educational experiences\, assignments are generally completed to gain points rather than understanding the concept from the material. \nIn the typical in-class environment with ever increasing classroom size and varying student skill levels\, most of the lecture and discussion time available is used to cover examples\, go over homework solutions\, and prepare for testing. There is simply not enough time available to individualize the learning experience for many students with the current teaching methodology. \n  \nFigure A: A Typical In-Class Methodology Work Flow. \n  \nIn the figure above\, a typical in-class methodology is presented. Students are given a 1-2 hour lecture\, which may cover several concepts. During this time\, general questions are covered. Follow-up questions are not typically asked since students need to think about the material\, read more references\, or do some homework before they have additional questions. When they attempt the homework\, they may have initial questions. These are answered during the discussion section\, along with some follow-up questions from the lecture. This method is not efficient since it moves at the rate of the slowest students and much of the time is spent answering general questions since follow-up questions require additional review of the material. \nAdding an Online Methodology\nIn order to have more advanced discussion and cover concepts that help struggling students as well as advanced students in a large class\, the “what\, where\, when\, and how” of information to be presented and consumed must be improved upon. First\, we will address general lectures and sample problems. Traditionally\, they are presented in class\, leading to the problems described previously. By using online tools to “flip the classroom\,” a popular concept that has been around for years but is much better realized with the easy accessibility of the Internet\, we can cater to a much wider audience and more efficiently use our time in the classroom. Flipping the classroom involves moving most of the general lecture material from in-class to at-home. Students now review the general lectures and examples at home in between lectures while lectures are used to answer student questions and provide a more interactive and dynamic learning environment. \nLectures can be succinct and split into individual modules or concepts instead of a weekly 1-2 hour lecture session which usually covers several topics. Students can review the material multiple times\, refer to references at their own pace\, and discuss with classmates\, teaching assistants\, and the professor regarding the material presented. Classroom time can now be utilized for more advanced discussion and better targeted toward student skill levels based on the content they discuss through available online tools\, such as the course mailing lists and message boards. \nFigure B: A Typical Online Methodology Work Flow \n  \nIn the Online methodology work flow\, students begin by reviewing 15-20 minute lecture and/or example modules. Any initial questions regarding the lecture\, example\, or homework can typically be answered by reviewing the module again in more detail\, which is not typically possible with a traditional in-class environment. If there are follow-up questions\, they can be answered using online tools\, such as message boards or mailing lists. \nThe turn-around time per concept is much quicker than a typical in-class work flow and can happen multiple times throughout any given week. An in-class or streaming lecture and discussion can still take place; however\, note that the majority of questions asked now are follow-up questions\, which allows for more efficient use of interaction time and discussion of more advanced topics. The overall amount of time spent in this work flow is similar to the in-class work flow since lectures and discussions can be decreased in favor of using online tools and modules to cover the general concepts. Students can also work at their own pace\, allowing for a more individualized experience. \nPreliminary Results\nThe initial results are encouraging. We compared Group A & Group B as a whole\, as well as in 3 separate groups based on performance (top third\, middle third\, and bottom third). \nAs stated earlier\, we will be using Exam 1 as the normalization factor. Students in Group A & Group B received the same typical in-class teaching methodology for material leading up to Exam 1. On average\, students from Group B score between 4-8% lower than students in Group A. All other factors being equal\, we expect this performance to stay in that range. Since we change the teaching and learning methodology for Exam 2 & 3\, we expect some changes in performance as well. \nFor the material covered in Exam 2\, a typical online methodology was used\, which just moved lectures from in-class to online videos. This can help address in-class problems like scheduling of large lecture halls\, being able to present to students of varying skill levels by allowing them to choose the appropriate videos\, and keep overhead costs down in a general sense. There is a minor improvement in allowing the lecturer to reach out to students of different skill levels through the videos and online message boards; much of this effectiveness depends on the students’ willingness to and frequency of which they use the technology. Since some material is offloaded outside the classroom\, there is more time to spend on individual student questions during the classroom session. Similar to the video and online message board issue\, this also depends on the students’ motivation to take advantage of these opportunities. \nAs a whole\, students in Group B showed a marginal improvement over students in Group A (1.37%). When split into three separate groups based on performance\, the top third of students in Group B outperformed the top third of students in Group A by approximately 4.55% after normalization is considered\, the middle third of Group B did 1.27% better\, and the bottom third did 1.57% worse than Group A. \nIn an attempt to bring learning to a more individual level using online tools\, Group B students were taught using an online hybrid methodology that goes beyond the typical in-class or online methodologies for Exam 3. Students in Group A continued to receive a traditional in-class teaching educational environment. \nIn the hybrid methodology\, we combine the advantages of in-class and online environments. The classroom is still “flipped\,” where much of the learning is done outside of the classroom through online videos\, mailing lists\, and discussion on message boards in between scheduled class sessions. However\, we help guide students with introductory lectures and answer general questions during an early classroom session. Since a significant portion of the material is covered outside of the classroom\, there is more time for individualized help and advanced discussion in the classroom itself. From there\, students are required to go through online lecture and sample videos. Finally\, they must take notes and submit questions on concepts they wish to be discussed in following lectures. \nUsing this method\, students in Group B performed significantly better than students in Group A as a whole and as smaller groups. After the normalization factor\, Group B averaged 7.44% higher on the exam\, with the top third performing 6.24% better in Group B\, middle third 7.14% better\, and bottom third 9.18% better than Group A. \nTable 1: Group A vs Group B \n  \nStudent Feedback\nStudent feedback regarding the traditional\, online\, and hybrid methodologies have shown that online videos and tools are aiding in improving their overall performance. \nFirst\, we review how students ranked each format of instruction in terms of helpfulness in understanding the course content in Table 2. \nTable 2: Helpfulness of Different Formats of Instruction for Students in Group B \n  \nIn general\, online lecture and TA example videos are preferred to in-class lectures and examples. Reading the textbook is the least preferred of the 5 learning formats. As mentioned earlier\, lectures were not formatted as traditional lectures\, but were handled similar to Q&A type sessions; therefore\, the basic knowledge required for the class is presented in the videos. More time is spent discussing deeper concepts in-class\, which was more useful to students who were studying more often or participating more often in-class. TA examples were more popular than concept lectures since they are given similar homework problems and solutions to review. \nNext\, we look at how students are spending their time studying outside of the classroom in Table 3. \nTable 3: Study Habits of Students in Group B after Class \n  \nAgain\, students in our Digital Design Logic course preferred watching online lecture and TA example videos over reading textbooks. The videos were able to better target varying skill levels of students and could be updated throughout or between the quarters. Since students receive a general overview and more detailed example in short concise videos\, they can more efficiently prepare for the next lecture or homework as well as discuss problems rather than reading long chapters in a textbook. \nLastly\, we review how much time is actually spent studying for this course compared to other courses in Table 4. \nTable 4: Study Frequency of Students in Group B Outside of Class \n  \nConsidering 3-4 classes is a typical full-time course load\, students are studying more for this course than any other single course in their curriculum. This is due to the more rigorous studying methodology required for the Digital Design course including studying online videos\, completing homework based on the videos\, and submitting questions for lectures based on each set of online lecture and example videos. However\, they are still studying well under the 40 hours total that is typical of a full-time course load. A typical course requires about 10 hours per week of total studying; with more students studying in the 6-10 hour range\, we would expect the performance of the students to be even higher. \nConclusion\nThis modest sampling of using online teaching methods to improve an existing large in-class environment has been shown to be effective. Overall\, students have varying amounts of motivation to ensure they do well and get the most out of their learning experience. Initial feedback suggests that the online videos are well received once they are presented with our hybrid teaching methodology. By using online tools\, making small changes to how in-class sessions are utilized\, and adjusting how students learn inside and outside the classroom\, student performance can be increased without impacting factors such as cost and quality of education. In fact\, by utilizing new technology and spending time to find effective means of conveying concepts and materials like that of the hybrid online methodology we can provide a more individualized experience for larger student classes in this time of increased enrollment\,  with a small increase in the number of TAs\, and some initial online investment.
URL:https://www.cecs.uci.edu/event/an-online-methodology-for-individualized-education/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20121128T150000
DTEND;TZID=America/Los_Angeles:20121128T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14392-1354114800-1354118400@www.cecs.uci.edu
SUMMARY:Power-Saving Method for DRAM/eDRAM and 3D-DRAM expoliting the process variations\, temperature changes\, device degradation\, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service
DESCRIPTION:Date/Time: Friday\, December 7\, 2012\, 3:30-5:00PM\nLocation: Engineering Hall 3206 \nCommittee Members:\nProfessor Fadi Kurdahi (Chair)\nProfessor Ahmed Eltawil \nAbstract:\nIn this dissertation\, we have devised an innovative approach to dynamically set supply voltages and refresh cycle for Dynamic Random Access Memory (DRAM) and 1T1C embedded Dynamic Random Access Memory (eDRAM). The approach helps us to reduce power consumption. The DRAM/eDRAM is usually designed to sustain the worst operating conditions\, and the chip is very rarely operated under these conditions. We exploit the design slack while operating under more favorable conditions to power consumptions. Simulation results indicate that power consumption can be saved more than 10 times when the chip is normally operated. This keeps the chip cool and the operating temperature will be well under control\, which helps in averting device degradation and ultimate breakdown. In addition\, it is possible to extend the eDRAM data retention time\, which helps to improve the memory availability and system performance. Then a mixed-signal controller that implements our algorithm is presented in detail. Our proposed control circuit dynamically adjusts the supply voltages and the refresh cycle with an awareness of process variations\, temperature changes\, and device degradation to minimize power consumption or maximize memory availability. We use the Predictive Technology Model(PTM) 45nm to design and simulate the controller. The silicon area of the controller is only 0.052 mm2which is equivalent to the area of a 1.5 Megabit memory array. It operates at 100 MHz frequency and consumes about 260µW. Compared to a circuit which is designed to accommodate the worst case scenario\, we can save power consumption or extend the memory availability more than ten times when our chip operates under normal conditions. After that an innovative memory management approach which utilize both 3D-DRAM and external DRAM (ex-DRAM) is presented. Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive\, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads\, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for “latency sensitive”\, “bandwidth sensitive”\, and “insensitive” applications. To improve the performance and satisfy a certain level of QoS\, memory blocks of distinct application types are allocated differently. Compared to the scratchpad memory management mechanism\, the average memory access latency of our approach decreases by 19% and 23%\, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover\, using our approach\, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead\, particularly for applications which have high spatial memory locality. Finally\, we present a power-saving method for 3D-DRAM with an awareness of memory access workload variations. We dynamically and independently adjust supply voltages and refresh cycles of different 3D-DRAM dies to minimize their power consumption in the active and idle states. In fact\, the same power saving method for DRAM/eDRAM\, which exploits the design slack due to process variations and temperature changes\, is applied for 3D-DRAM. In both states\, we can still read/write normally and our method does not cause any performance overhead. The difference between these two states is the mechanism to minimize the power consumption: read/write operations and refresh operations consume the most power in the active and the idle state respectively. In addition\, we implement a memory relocation mechanism so that recently accessed memory blocks are gathered together into common 3D-DRAM dies. That allows the others to be in the idle state to save power consumption. The memory relocation mechanism is also an extension of the proposed heterogeneous memory management approach. The overhead of our memory relocation mechanism is negligible. Our simulation shows that if there is no memory access (all 3D-DRAM dies change into the idle state) our method can save power consumption up to 75%. If the memory access workload is low\, our method can save power consumption by almost 50%.
URL:https://www.cecs.uci.edu/event/power-saving-method-for-dram-edram-and-3d-dram-expoliting-the-process-variations-temperature-changes-device-degradation-and-memory-access-workload-variations-and-innovative-heterogeneous-memory-man/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120924T150000
DTEND;TZID=America/Los_Angeles:20120924T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14390-1348498800-1348502400@www.cecs.uci.edu
SUMMARY:Cyber-Physical Systems at Small and Large Scales
DESCRIPTION:Speaker:  Prof. Marilyn Wolf\, Georgia Institute of TechnologyLocation:  4011 Donal Bren Hall\nDate/Time: Friday\, September 28\, 2012\, 2:00-3:00PM\nView Details
URL:https://www.cecs.uci.edu/event/cyber-physical-systems-at-small-and-large-scales/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120906T150000
DTEND;TZID=America/Los_Angeles:20120906T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14389-1346943600-1346947200@www.cecs.uci.edu
SUMMARY:Flexible Error Handling for Resource-Constrained Embedded Systems
DESCRIPTION:Speaker:  Dr. Michael Engel\, TU Dortmund University\, GermanyLocation:  2430 Engineering Hall\nDate/Time:   Friday\, August 31\, 2012\, 2:30-4:00PM\nView Details
URL:https://www.cecs.uci.edu/event/flexible-error-handling-for-resource-constrained-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14308-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Millimeter-Wave Circuits for W-band Applications
DESCRIPTION:Location:Calit2 3355\nDate and Time: March 8th\, 2012\, 10:00AM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Filippo Capolino\nProfessor A. Lee Swindlehurst \nTitle: Silicon-Based Millimeter-Wave Circuits for W-band Applications \nAbstract:\nHistorically\, monolithic microwave integrated circuits (MMICs) have been designed using III-V semiconductor technologies\, such as GaAs and InP. In recent years\, the number of publications reporting silicon-based millimeter-wave (mm-wave) transmitter\, receivers\, and transceivers has grown steadily. For mm-wave applications including gigabit/s point-to-point links (57-64 GHz)\, automative radar (77-81 GHz) and imaging (94 GHz) to reach mainstream market\, the cost\, size and power consumption of silicon-based solution has to be significantly below what is being achieved today using compound seminconductor technology. This dissertation focuses the effort of designing and implementing silicon-based solutions through circuit- and system-level innovation for applications in the W-band frequency band (750110GHz)\, in particular\, 94GHz passive imaging band. \nA W-band front-end receiver in 65nm CMOS based entirely on slow-wave CPW (SW-CPW) with frequency tripler as the LO is designed and measured. The receiver achieves a total gain of 35-dB\, -3dB-BW of 12 GHz\, a NF of 9-dB\, a P1-dB of -40dBM\, a low power consumption of 108mW under 1.2/0.8V. This front-end receiver chipset in conjuction with an analog back-end can be used to form a radiometer. \nLeveraging the work done in 65nm CMOS\, the first integrated 2×2 focal-plane array (FPA) for passive imaging is implemented in a 0.18um SiGE BiCMOS process (ft/fmax=200/180GHz). The FPA incorporates four Dicke-type receivers. Each receiver employs a direct-conversion architecture consisting of an on-chip slot dipole antenna\, an SPDT switch\, a lower noise amplifier\, a single-balanced mixer\, an injection-locked frequency tripler (ILFT)\, a zero-IF variable gain amplifier\, a power detector\, an active bandpass filter and a synchronous demodulator. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four ILFTx. This work demonstrates the highest level of integration of any silicon-based systems in the 94GHz imaging band. \nFinally\, the main design bottleneck of any wireless transceiver system\, the frequency synthesizer/phase-locked loop is investigated. Two monolithically integrated W-band frequency synthesizer are presented. Implemented in a 0.18um SiGe BiCMOS\, both architectures incorporate the same 30.3-33.8GHz PLL core. One sythesizer uses an injection-locked frequency tripler (ILFT) with locking range of 92.8-98.1GHz and the other employ a harmonic-based frequency tripler (HBFT) with 3-dB bandwidth of 10.5GHz from 90.0-101.4GHz\, respectively. The frequency sythesizer is suitable for integration in mm-wave phased array and multi-pixel systems such as W-band radar/imaging and 120GHz Gb/s communication.
URL:https://www.cecs.uci.edu/event/silicon-based-millimeter-wave-circuits-for-w-band-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14307-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging
DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: March 8th\, 2012\, 2:00-3:30PM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Michael Green\nProfessor Peter Burke \nTitle: Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging \nAbstract:\nSilicon technology\, with its superior integration capability and low cost\, has changed the world dramatically during the past few decades and recently has entered the realm of millimeter-wave (MMW) system design that is used to be dominated by III-V compound semiconductor technologies. Benefiting from the continuous feature size scaling of silicon technology\, passive MMW imagers could be built on chip which paves the way for developing low-cost\, compact wafer-scale imagers. This dissertation focuses on the design of fully integrated W-band passive imager and also covers the design of W-band synthesizer which is one of the most critical and challenging building blocks of the imaging receiver. Two chips for 96GHz frequency generation incorporating the same Ka-band PLL and (1) an injection-locked frequency tripler (ILFT); (2) a harmonic-based frequency tripler (HBFT) in 0.18?m SiGe BiCMOS (fT/fmax=200/180GHz) are presented. The ILFT and HBFT preceded by the same Ka-band PPL achieve measured closed-loop phase noise of -93dBc/Hz and -92dBc/Hz at 1MHz offset\, respectively. Both chips are designed under the same power consumption of 14mW from 1.8V/2.5V supplies. This work presents the first implementation of an injection-locked-based frequency multiplier in SiGe BiCMOS process. W-band transformer-based injection-locked frequency tripler (T-ILFT) is also designed and implemented in 65nm standard CMOS technology using a 0.8V supply voltage. THe use of injection locking topology with on-chip transformer provides several advantages over conventional design. A fully integrated W-band 2×2 focal-plane array (FPA) for passive millimeter-wave imaging is demonstrated in 0.18?m SiGe BiCMOS process. The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture with an on-chip slot folded dipole antenna. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. This imaging receiver (without antenna) achievers a measured average responsivity and noise equivalent power of 285MV/W and 8.1fW/Hz1/2\, respectively\, across the 86-106GHz bandwidth\, which results a calculated NETD of 0.48K with a 30ms integration time. The system NETD increases to 3K with on-chip antenna due to its low efficiency at W-band. This work demonstrates the highest integration level of any silicon-based systems in the 94GHz imaging band.
URL:https://www.cecs.uci.edu/event/silicon-based-integrated-circuits-for-w-band-fully-integrated-passive-imaging/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120627T150000
DTEND;TZID=America/Los_Angeles:20120627T160000
DTSTAMP:20231011T181236Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T181236Z
UID:14257-1340809200-1340812800@www.cecs.uci.edu
SUMMARY:Addressing Supply Chain Security with Split Manufacturing
DESCRIPTION:Addressing Supply Chain Security with Split Manufacturing\n\n\n\n\nSpeaker\n\n\nDr. Ted Huffmire\nNaval Postgraduate School\, Monterey\, California\n\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDBH 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 27\, 2012\nSeminar begins at 11:00am\, Refreshment at 10:45am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nSecurity is an essential design goal in computer architecture\, and security is a concern throughout the entire lifecycle of a system. The process of designing hardware requires trusting intellectual property (IP) cores and computer-aided design (CAD) tools developed by third parties\, as well as the fabrication\, packaging\, assembly\, and delivery of the final system. Valuable IP is vulnerable to theft and modification during tape-out\, even if a perfect design free of security flaws is sent to the foundry. Of course\, no design is ever perfect\, and having a trusted foundry does not solve the problem of flawed designs. Furthermore\, the trusted foundry may not have the capability to deliver the most aggressive technology node\, volume\, yield\, or cost. Even the extraordinary step of building everything from scratch in-house\, including all of the tool chains\, both digital and analog\, is not guaranteed to result in a trustworthy design.  \nThis short\, informal\, seminar-style talk will explore three split manufacturing approaches for addressing hardware supply chain security: reconfigurable hardware\, 2D IC split manufacturing\, and 3D IC split manufacturing. Reconfigurable hardware allows the design to be loaded onto a field-programmable gate array (FPGA) device in a secure facility after fabrication. With 2D IC split manufacturing\, different metal layers of the same wafer are fabricated in different foundries\, one of which is a trusted foundry. With 3D IC split manufacturing\, two or more individual die are fabricated in different foundries\, one of which is a trusted foundry\, and then assembled in a trusted facility. The challenges and opportunities of each of these approaches will be compared and contrasted\, as well as the viability of split manufacturing in general.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nTed Huffmire is an Assistant Professor of Computer Science at the Naval Postgraduate School in Monterey\, California. His research spans both computer security and computer architecture\, focusing on hardware-oriented security and the development of policy enforcement mechanisms for application-specific devices. He has a Ph.D. in computer science from the University of California\, Santa Barbara. He is a member of the IEEE and the ACM. The views presented in this talk are those of the speaker and do not necessarily reflect the views of the United States Department of Defense
URL:https://www.cecs.uci.edu/event/addressing-supply-chain-security-with-split-manufacturing/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR