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DTSTART;TZID=America/Los_Angeles:20091118T150000
DTEND;TZID=America/Los_Angeles:20091118T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14275-1258556400-1258560000@www.cecs.uci.edu
SUMMARY:Concurrency and Communication: Lessons from the SHIM Project
DESCRIPTION:Concurrency and Communication: Lessons from the SHIM Project\n\n\n\n\nSpeaker\n\n\nDr. Stephen A. Edwards\,\nColumbia University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Tony Givargis\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 18\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDescribing parallel hardware and software is difficult\, especially in an embedded setting. Five years ago\, we started the SHIM project to address this challenge by developing a programming language for hardware/software systems. The resulting language describes asynchronously running processes that has the useful property of scheduling-independence: the I/O of a SHIM program is not affected by any scheduling choices. I will present a history of the SHIM project with a focus on the key things we have learned along the way.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nStephen A. Edwards received the B.S. degree in Electrical Engineering from the California Institute of Technology in 1992\, and the M.S. and Ph.D degrees\, also in Electrical Engineering\, from the University of California\, Berkeley in 1994 and 1997 respectively. He is currently an associate professor in the Computer Science Department of Columbia University in New York\, which he joined in 2001 after a three-year stint with Synopsys\, Inc.\, in Mountain View\, California. His research interests include embedded system design\, domain-specific languages\, and compilers.
URL:https://www.cecs.uci.edu/event/concurrency-and-communication-lessons-from-the-shim-project/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091117T150000
DTEND;TZID=America/Los_Angeles:20091117T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14276-1258470000-1258473600@www.cecs.uci.edu
SUMMARY:Advanced SoC Architectures for Multiple DRAMs (Enabled by 3D Die Stacking)
DESCRIPTION:Advanced SoC Architectures for Multiple DRAMs\n(Enabled by 3D Die Stacking)\n\n\n\n\nSpeaker\n\n\nDr. Sungjoo Yoo\nPOSTECH\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 17 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe performance of data-intensive applications is mostly determined by the bandwidth and latency of off-chip DRAM. In order to improve the bandwidth and latency characteristics\, multiple memory-based solutions (enabled by 3D stacking of memory dies on top of LSI dies) are being actively investigated. With multiple DRAMs\, we come to face new architectural problems\, especially\, in memory controllers and on-chip network. In this talk\, we will discuss the architectural problems caused by multiple memories and present our solutions (request parallelizer\, in-network reorder buffer\, etc.) to address the problems. We will summarize this talk with some speculations on future SoC architectures with multiple memories.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Sungjoo Yoo received B.S.\, M.S.\, and Ph.D. at Seoul National University\, Korea\, in 1992\, 1995\, and 2000\, respectively. He worked at TIMA laboratory\, Grenoble\, France from 2000 to 2004 and worked as principal engineer at System LSI Division\, Samsung Electronics from 2004 to 2008. At Samsung\, he led a team which developed AMBA3-based on-chip bus architectures for mobile SoCs\, and low power design solutions such as dynamic voltage and frequency scaling (DVFS) algorithms and performed hardware/software co-optimization of solid state disk products. He joined POSTECH (Pohang university of science and technology) in August 2008. His current research interests include memory hierarchy and network-on-chip for many-core SoC\, low power design based on runtime-distribution and temperature-aware DVFS\, and power efficiency/performance/reliability improvement of solid state disk.
URL:https://www.cecs.uci.edu/event/advanced-soc-architectures-for-multiple-drams-enabled-by-3d-die-stacking/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091116T150000
DTEND;TZID=America/Los_Angeles:20091116T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14277-1258383600-1258387200@www.cecs.uci.edu
SUMMARY:Energy Efficient Computing
DESCRIPTION:Energy Efficient Computing\n\n\n\n\nSpeaker\n\n\nProf. Tajana Simunic Rosing\,\nDepartment of CSE\,\nUC San Diego\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Daniel Gajski\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 16 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk\, we will present the algorithms we have developed at UCSD for lowering the energy consumption in computing systems. We derived optimal power management strategies for stationary workloads that have been implemented both in HW and SW. Run-time adaptation can be done via an online learning algorithm that selects among a set of policies. We generalized the algorithm to include thermal management since we found that minimizing the power consumption does not necessarily reduce the overall energy costs. To reduce the performance costs typically associated with state of the art thermal management techniques\, we also developed a new set of proactive management policies. The experimental results using real datacenter workloads on an actual multicore system show that our proactive technique is able to dramatically reduce the adverse effects of temperature by over 60%. Most recently we have shown that symbiotic scheduling of workloads in virtualized environments can lead to average 15% energy savings with 20% performance benefit in high utilization scenarios.We will also present some of the recent work that address the energy savings in battery powered systems\, as demonstrated in a new kind of “citizen infrastructure”\, an end-to-end health and environmental information system with near real-time data streams and feedback loops from the system to the sensing\, processing\, and actuation infrastructure. We have developed adaptive algorithms to tradeoff accuracy of computation versus the available energy for such systems\, while taking into account the energy harvesting capabilities.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nTajana Simunic Rosing is currently an Assistant Professor in Computer Science Department at UCSD\, a director of System Energy Efficiency Lab at UCSD and a head of the Energy efficient datacenter thrust as a part of the MuSyC center. Her research interests are energy efficient computing\, embedded and wireless systems. She finished her PhD at Stanford University. Prior to pursuing the PhD\, she worked as a Senior Design Engineer at Altera Corporation. She has served at a number of Technical Paper Committees\, and is currently an Associate Editor of IEEE Transactions on Mobile Computing.
URL:https://www.cecs.uci.edu/event/energy-efficient-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091112T150000
DTEND;TZID=America/Los_Angeles:20091112T160000
DTSTAMP:20231011T185436Z
CREATED:20231011T185436Z
LAST-MODIFIED:20231011T185436Z
UID:14365-1258038000-1258041600@www.cecs.uci.edu
SUMMARY:NEC’s Manycore Platforms for Low-Power Embedded System
DESCRIPTION:Naoki NishGeneral Manager\, NEC Central Research Labs\nTokyo\, Japan\nDonald Bren Hall 3011\nNovember 12\, 2009\nAbstract
URL:https://www.cecs.uci.edu/event/necs-manycore-platforms-for-low-power-embedded-system-2/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091112T150000
DTEND;TZID=America/Los_Angeles:20091112T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T180836Z
LAST-MODIFIED:20231011T192457Z
UID:14247-1258038000-1258041600@www.cecs.uci.edu
SUMMARY:NEC's Manycore Platforms for Low-Power Embedded System
DESCRIPTION:NEC’s Manycore Platforms for Low-Power Embedded System\n\n\n\n\nSpeaker\n\n\nNaoki Nishi\nGM\, NEC Central Research Labs\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 12\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAfter short introduction of NEC’s R&D vision related to future ICT system handling real world in real time\, two examples of NEC’s manycore research activities will be presented. First example is an in-vehicle vision processor IMAPCAR-2 which supports SIMD-MIMD morphing\, and the second is a fine grain manycore architecture called STP (Stream TransPoser) engine which is a kind of dynamically reconfigurable hardware with C level language SDK support.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nNaoki Nishi is a general manager at central research labs.\, NEC. He jointed NEC in 1984\, where he worked in research on micro-architectures and LSI development of the NEC SX vector supercomputer\, After the development of CMOS vector supercomputer SX-4 in 1996\, he has been conducting research on high-performance\, low-power multi-/many-cores. Naoki Nishi received his B.E. and M.E. degrees in system engineering from Hiroshima University\, Japan.
URL:https://www.cecs.uci.edu/event/necs-manycore-platforms-for-low-power-embedded-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091110T150000
DTEND;TZID=America/Los_Angeles:20091110T160000
DTSTAMP:20231011T185436Z
CREATED:20231011T183050Z
LAST-MODIFIED:20231011T185436Z
UID:14278-1257865200-1257868800@www.cecs.uci.edu
SUMMARY:Why Circuits Fail
DESCRIPTION:Dr. Sani R. NassifIBM Research Labs\, Austin\, TX\nDonald Bren Hall 3011\nNovember 10\, 2009\nAbstract
URL:https://www.cecs.uci.edu/event/why-circuits-fail/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091022T150000
DTEND;TZID=America/Los_Angeles:20091022T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192031Z
UID:14248-1256223600-1256227200@www.cecs.uci.edu
SUMMARY:A Virtualization-Based Software Architecture for Real-Time Embedded Systems
DESCRIPTION:A Virtualization-Based Software Architecture for Real-Time Embedded Systems\n\n\n\n\nSpeaker\n\n\nDr. Sung-Soo Lim\nAssistant Professor\,\nSchool of Computer Science\,\nKookmin University\,\nSeoul\, Korea\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 22 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThis talk introduces an on-going work in Embedded Systems Laboratory\, Kookmin University to build next generation software architecture for mobile phones cooperating with Samsung Electronics. Future mobile phones need to accommodate both legacy applications and hard real-time communication protocols regardless of the underlying hardware organization. Such support for flexibility and reconfigurability should be accompanied with guarantee of reliability and security.  \nWe design and implement a light-weight hypervisor based on L4 microkernel for real-time embedded systems accommodating both general-purpose and hard real-time operating systems. The virtualization-based software architecture based on our hypervisor could have the reliability with zero-down feature and safety during dynamic software upgrade. We built a prototype smartphone platform running both Linux and uCOS-II on a single ARM11 core using the proposed software architecture. The structure and core techniques used in our software architecture will be introduced in the talk.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nSung-Soo Lim received BS\, MS\, and PhD degrees in Computer Engineering from Seoul National University in 1993\, 1995\, and 2002\, respectively. From 2000 to 2001\, he was a visiting researcher in University of Illinois at Urbana-Champaign. From 2001 to 2004\, he was the CTO of PalmPalm Technology\, Inc. in Korea (a smartphone development company). He is currently an assistant professor in School of Computer Science\, Kookmin University. His research area includes real-time operating systems\, real-time performance analysis\, low-power technology\, and mobile phone architecture.
URL:https://www.cecs.uci.edu/event/a-virtualization-based-software-architecture-for-real-time-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091019T150000
DTEND;TZID=America/Los_Angeles:20091019T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14249-1255964400-1255968000@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 19 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091009T150000
DTEND;TZID=America/Los_Angeles:20091009T160000
DTSTAMP:20231011T192654Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192654Z
UID:14250-1255100400-1255104000@www.cecs.uci.edu
SUMMARY:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA
DESCRIPTION:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA\n\n\n\n\nSpeaker\n\n\nProf. Lei He\nElectrical Engineering Department\,\nUCLA\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Eli Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 9\, 2009\nRefreshments at 10:30am; Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAs devices become smaller\, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired\, especially if no extra area\, power and delay and little change of the existing design flow are introduced. Using FPGA and internet router as a testbed\, this talk first presents fault tolerance techniques applying (1) logic don’t care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both increase MTTF by 2X with little or no overhead. Particularly\, IPR does not change circuit placement and routing\, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. Finally\, I will briefly discuss my ongoing research on cyber-physical systems involving renewal energy storage and environment/water monitoring.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Lei He is an associate professor at electrical engineering department\, UCLA\, and was a faculty member at University of Wisconsin\, Madison between 1999 and 2001. He also held visiting or consulting positions with Intel\, Hewlett-Package\, Cadence and Synopsys\, was a technical advisory board member for Rio Design Automation\, and Apache Design Solutions\, and is a guest professor at Fudan University (China) and China National Laboratory for Optoelectronics.  \nHis research interests include electronic design automation\, VLSI circuits and systems\, and cyber-physical systems. He has published one book and over 200 technical papers and has been a technical program committee member for a number of conferences including Design Automation Conference\, International Conference on Computer-Aided Design\, International Symposium on Low Power Electronics and Design\, International Symposium on Field Programmable Gate Array\, and International Symposium on Physical Design. Dr. He obtained Ph.D. degree in computer science from UCLA in 1999. He was granted National Science Foundation CAREER award in 2000\, UCLA Chancellor’s faculty career development award in 2003\, IBM Faculty Award in 2003\, Northrop Grumman Excellence in Teaching award in 2005\, best paper award at the 2006 International Symposium on Physical Design\, and multiple best paper nominations at Design Automation Conference and International Conference on Computer-Aided Design.
URL:https://www.cecs.uci.edu/event/power-efficient-and-fault-tolerant-circuits-and-systems-using-commodity-fpga/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090901T150000
DTEND;TZID=America/Los_Angeles:20090901T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14318-1251817200-1251820800@www.cecs.uci.edu
SUMMARY:Algorithmic Code Optimization Using Conditional Expression Evaluation
DESCRIPTION:Algorithmic Code Optimization Using Conditional Expression Evaluation\nby Mohammad Ali Ghodrat \nLocation: Bren Hall 3011 \nDate and Time: September 1\, 2009 10:30am \nCommittee:\nProfessor Tony Givargis (Chair)\nProfessor Alex Nicolau\nProfessor Nikil Dutt \nAbstract:\nSoftware is becoming a larger fraction of engineering effort. Aggressive compiler optimization\, in particular those that address loops\, can significantly improve the performance of the software\, thus justifying the additional compilation time requirements. This is in particular true in the embedded system domain where software has become a key element of the design process and performance/energy is of a critical concern. A particular area in software optimization\, where little work has been established\, is control flow performance and energy optimization\, which is the main focus of this thesis. \nArithmetic expressions are the fundamental building blocks of hardware and software systems. In this thesis we first propose a method for solving the arithmetic expression equivalence problem using partial evaluation. In our method\, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Using this technique\, we present three novel control flow optimization techniques to improve performance and energy in software. \nIn the first technique\, we present a short-circuit code transformation method to optimize conditional blocks in high-level programs. Specifically\, the transformation takes advantage of the fact that the Boolean value of the conditional expression\, determining the true/false paths\, can be statically analyzed to determine cases when one or the other of the true/false paths are guaranteed to execute. In such cases\, code is generated to bypass the evaluation of the conditional expression. In instances when the bypass code is faster to evaluate than the conditional expression\, a net performance gain is obtained. \nIn the second technique\, we present a loop transformation method to optimize loops containing nested conditional blocks. Results from conditional expression evaluation combined with loop dependency information are used to partition the iteration space of the nested loop. As a result\, the loop nest is decomposed such as to eliminate the conditional test\, thus substantially reducing the execution time. Our technique completely eliminates the conditional from the loops (unlike previous techniques) thus further facilitating the application of traditional optimizations and improving the overall speedup. \nIn the third technique\, we present a method to lower the software energy consumption using the technique mentioned above for loop transformation. In essence\, each of the smaller loops can be executed at a lower voltage/frequency setting\, yielding overall energy reduction. \nApplying the proposed transformation techniques on kernels taken from different application domains\, we measured a substantial performance and energy improvement.
URL:https://www.cecs.uci.edu/event/algorithmic-code-optimization-using-conditional-expression-evaluation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090805T150000
DTEND;TZID=America/Los_Angeles:20090805T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14279-1249484400-1249488000@www.cecs.uci.edu
SUMMARY:Portable Direct Methanol Fuel Cell System for Green Computing
DESCRIPTION:Portable Direct Methanol Fuel Cell System for Green Computing\n\n\n\n\nSpeaker\n\n\nDr. Naehyuck Chang\nSeoul National University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nCalIT2 Room 3008\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nAugust 5 \, 2009\nRefreshments at 10:00 am\, Lecture begins at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe introduce a hybrid portable direct methanol fuel cell (DMFC) system\nwhich includes a li-ion battery. We demonstrate a hybrid operation of\nthe DMFC stack and the li-ion battery to maintain a constant stack\noutput current regardless of the load current to maximize the\nperformance. We describe the balance of plant (BOP) control system\,\nincluding a 32-bit microprocessor\, and electronics to drive motors\,\nactuators and sensors for reliable operation and protection of a DMFC\nsystem. The dynamics of BOP control is taken into account to design\nmultiple cascaded feedback control loops. We demonstrate robust\noperation of a DMFC system together with introduction of a DMFC system\ndesign. This talk includes a working prototype system demonstration of a\ncomplete DMFC and battery hybrid power source.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nNaehyuck Chang received his BS\, MS and PhD degrees all from Seoul National University\, in 1989\, 1992 and 1996\, respectively. He was a research associate at Dept. of Electrical Engineering and Computer Science at University of Michigan in Ann Arbor in 1997. He joined Seoul National University in Dept. of Computer Science and Engineering in 1997 as a faculty member and now is an Associate Professor in Dept. of Electrical Engineering and Computer Science. He was also a Visiting Associate Professor at Arizona State University in 2005. He has been with Sindoricoh\, Co. Ltd.\, as a Technical Advisor since 2001. He has published more than 70 technical papers in low-power and embedded systems area.
URL:https://www.cecs.uci.edu/event/portable-direct-methanol-fuel-cell-system-for-green-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090724T150000
DTEND;TZID=America/Los_Angeles:20090724T160000
DTSTAMP:20231011T185436Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T185436Z
UID:14280-1248447600-1248451200@www.cecs.uci.edu
SUMMARY:Application Specific Multicore Chips for Medical Services
DESCRIPTION:Dr. Iyad Al Khatib\, Solidux Telecom ABStockholm\, Sweden\nEngineering III 2430\nJuly 24\, 2009\nAbstract
URL:https://www.cecs.uci.edu/event/application-specific-multicore-chips-for-medical-services/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090722T150000
DTEND;TZID=America/Los_Angeles:20090722T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14281-1248274800-1248278400@www.cecs.uci.edu
SUMMARY:Compiler-enabled Power-efficient Register File Protection
DESCRIPTION:Compiler-enabled Power-efficient Register File Protection\n\n\n\n\nSpeaker\n\n\nDr. Jongeun Lee\nEECS\, Ulsan National Institute of Science and Technology\,Korea\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 22\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRegister file (RF) is extremely vulnerable to soft errors\, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor\, but also since it is one of the hottest blocks on the chip\, and therefore adding any extra circuitry to it is not desirable. Software approaches would be ideal in this case\, but previous approaches that are based on program duplication have very significant runtime overheads\, and others based on instruction scheduling are only moderately effective due to local scope.  \nThis talk will be about how compiler alone and in conjunction with microarchitecture can power-efficiently protect the RF. What we have observed is that a significant portion of the RF vulnerability is contributed by long lifetime variables. Protecting only these can result in power-efficient RF protection. Thus the task of the compiler is to identify program variables that have long lifetimes and protect them. Our experiments demonstrate pure compiler techniques can reduce the vulnerability of the RF by 33-37% on average and up to 66%\, with a small (2%) runtime overhead. As compared to hardware protection mechanisms\, compiler analysis can achieve the same level of protection but at up to 75% lesser RF energy consumption.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nJongeun Lee received a BS and an MS in Electrical Engineering and a PhD in Electrical Engineering and Computer Science all from Seoul National University. Previously he was with Samsung SoC R&D Center in Korea\, and is currently a postdoctoral associate at Arizona State University\, working with Dr. Aviral Shrivastava. He is joining Ulsan National Institute of Science and Technology\, Korea\, as an Assistant Professor of EECS. His research interests include configurable/reconfigurable processor architecture design\, compilation for energy and reliability\, and compilation for multicore processors and GPUs.
URL:https://www.cecs.uci.edu/event/compiler-enabled-power-efficient-register-file-protection/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090709T150000
DTEND;TZID=America/Los_Angeles:20090709T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14319-1247151600-1247155200@www.cecs.uci.edu
SUMMARY:Transducer Synthesis for Heterogeneous Multi-processor Systems
DESCRIPTION:Transducer Synthesis for Heterogeneous Multi-processor Systems\nby Hansu Cho \nLocation: EH 2210 \nDate and Time: July 9\, 2009\, 8:30 AM \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nContemporary system design requires more computational power than ever. To overcome this problem\, MPSoC is widely used\, but design complexity have been increased rapidly. Meanwhile\, short time to market forced system designer to reduce development time. Therefore\, designer raised the level of abstraction into the higher level called transaction level. But\, current high level synthesis tools are dedicated to computational components only. To our best knowledge\, there is no synthesis tool for communication components from the transaction level model down to RTL model. In this dissertation\, we present a component called transducer which can handle heterogeneous MPSoC communication with multiple buses. Also\, we presents a tool for automatic synthesis of transducer. The tool captures the communication parameters in the platform at transaction level and generates transducer in RTL. The design and configuration of the transducer depend on several platform components including heterogeneity of the components\, traffic on the bus\, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the transducer can be automatically derived based on these parameters. \nThe advantage of this approach is that the user may modifies transducer parameters to suit specific optimization goals. In contrast to conventional approaches like IP wrappers\, our approach enables the user to generate an application specific interface between any number of buses for any platform configuration. Therefore\, the system designer is not bound to a set of IPs or protocols for their platform definition. Furthermore\, due to automatic generation\, we provide several orders of magnitude savings in interface development cost. We demonstrate the synthesizability and quality of our automatically generated transducers using Xilinx ISE tools and FPGA board. We use industrial strength design drivers such as an MP3 decoder and JPEG encoder to test our automatically generated transducers for a variety of platforms and compare them to manually designed transducers on different quality metrics. Our experimental results show that performance of automatically generated transducers are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 20X of improvement in development time.
URL:https://www.cecs.uci.edu/event/transducer-synthesis-for-heterogeneous-multi-processor-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090618T150000
DTEND;TZID=America/Los_Angeles:20090618T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14320-1245337200-1245340800@www.cecs.uci.edu
SUMMARY:Automatic Generation and Verification of Transaction Level Models
DESCRIPTION:Automatic Generation and Verification of Transaction Level Models\nby Lochi Yu \nLocation: ET 331 \nDate and Time: June 18\, 2009 10:00am \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nThe rising complexity in system designs over the past decades poses great challenges to current designers. One way to cope with this challenge has been to raise the level of abstraction of design\, reducing the number of elements and speeding up design decisions. Transaction Level Models (TLM) have emerged as a new alternative to design Multi-Processor System-on-Chips (MPSoC). TLMs express communication among modules at the transaction level\, without simulating the dozens of individual signals in communication elements such as busses. Nevertheless\, several drawbacks exist: TLMs are fast\, but their accuracy is low\, TLMs are being coded manually\, often by the use of a System Level Design Language (SLDL)\, there is no widely-adopted and tool-supported TLM style\, and there has been little work on verifi cation at the System Level. In this dissertation\, we aimed to contribute in different aspects: We defined a modeling style for SystemC TLMs whose modules have a one-to-one relationship with actual synthesized modules in a FPGA. Then\, we defined a data structure\, complete and flexible enough to describe a complete embedded system\, its hardware platform and application\, and developed generation algorithms that would use it to automatically produce an executable TLM in SystemC. Fourth\, we designed new transformation rules for models in Model Algebra (MA) that allows veri cation on pipelined models in MA. With our approach\, we can have automatic generation and verification of Transaction Level Models\, freeing the designer from error-prone manual coding\, and allows him to focus on higher level design decisions\, speeding up the overall design phase.
URL:https://www.cecs.uci.edu/event/automatic-generation-and-verification-of-transaction-level-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090603T150000
DTEND;TZID=America/Los_Angeles:20090603T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14321-1244041200-1244044800@www.cecs.uci.edu
SUMMARY:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors
DESCRIPTION:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors\nby Ashok Halambi \nLocation: DBH 4013 \nDate and Time: June 3\, 2009 2:00pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Alex Nicolau\nProfessor Alex Viedenbaum \nAbstract:\nEmbedded systems continue to increase in functionality\, complexity and connectivity. Programmable platforms\, consisting of processors programmable in software\, are a popular solution to satisfy the design constraints (such as cost\, performance\, flexibility\, reliability etc.) of such systems. Key challenges in the design of programmable platforms include compiler-in-loop design space exploration (DSE)\, and automatic generation of software toolkit for hardware/software co-design. \nA language-based model of the processor-memory subsystem has several benefits: it serves as a golden reference model for all principals involved in the design; it can be used to drive DSE and automatic software toolkit generation; it can be used to perform top-down (formal) verification and validation; and\, it can be refined down to implementation (register-transfer level). In this dissertation\, we present EXPRESSION\, an architecture description language (ADL) that is designed for DSE of processor-memory sub-system and automatic generation of software toolkit including compiler and cycle-accurate simulator. EXPRESSION has been used to describe various processors from RISC (DLX\, MIPS R4000\, ARM 9)\, VLIW (TI C6x)\, DSP (ST100)\, etc. Our EXPRESSION based DSE methodology permits exploration of a wide range of processor architectures\, and includes compiler-in-loop for accurate analysis of each design configuration. \nTo aid compiler-in-loop DSE\, we developed EXPRESS\, a retargetable\, instruction level parallelizing compiler that accepts programs in “C” and produces assembly code for the target processor described in EXPRESSION. The EXPRESS compiler is capable of handling irregular architectures\, and can adapt to changes in the processor’s instruction-set or micro-architecture. EXPRESS also includes a framework for dynamic customization of the compiler based on the target application and architecture characteristics. These capabilities of EXPRESS make it ideal for use in the DSE of processor-memory subsystems. \nRetargetable compilers suffer from the drawback of poor output code quality as compared to a compiler that is “hand-crafted” for the target processor. Key differences between the two compilers include the presence of target specific optimizations and custom phase ordering of optimization passes in the target specific compiler. In this dissertation\, we propose a framework\, called TransMutations\, that enables dynamic\, run-time customization of a retargetable compiler. It allows for easy integration of optimizations (called mutations) into the compiler and solves the phase ordering problem by applying optimizations in a context-sensitive manner for each region of the application code. The TransMutations framework has been implemented in the EXPRESS compiler and we present results demonstrating the effectiveness of the technique. This framework improves the quality of code generated by retargetable compilers and enables them to be used in accurate compiler-in-loop DSE of programmable embedded systems.
URL:https://www.cecs.uci.edu/event/transmutations-a-framework-for-dynamic-customization-of-retargetable-compilers-for-embedded-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090529T150000
DTEND;TZID=America/Los_Angeles:20090529T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14322-1243609200-1243612800@www.cecs.uci.edu
SUMMARY:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement
DESCRIPTION:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement\nby Aseem Gupta \nLocation: DBH 3011 \nDate and Time: May 29\, 2009 1:30pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Fadi Kurdahi\nProfessor Tony Givargis \nAbstract:\nProcess scaling and shrinking device geometries have resulted in chips with greater performance and complexity levels. However\, these advancements have come at the cost of higher power densities and increased operating temperatures. The inability to control the operating temperatures by existing cooling techniques is the principal reason for discontinuation of an increase in frequencies and introduction of multi-core architectures. Apart from operability\, high temperatures have unfavorable consequences such as: increased leakage power\, reduced interconnect life time\, slowing of interconnects and transistors\, need for expensive package and cooling mechanisms\, and increased manufacturing cost and design effort. Traditionally\, thermal issues have been examined only at the post-synthesis stages of the design flow. This thesis attempts to migrate the “thermal awareness” from the physical level design phase to early stages of the VLSI design flow and utilize it to target various design metrics such as power\, performance\, reliability\, and operability. This thesis advances the procedure of leakage power estimation by coupling it with thermal profile estimation and capturing the positive interdependence between temperature and leakage power. It also advances the traditional role of communication architecture to that of an active thermal manager. The proposed communication architecture based thermal manager delays the execution of chosen components by regulating the flow of data over the on-chip communication fabric. This dissertation demonstrates the need of examining the effects of frequency\, supply voltage\, power dissipation\, and temperature on SRAM reliability in a mutually interrelated manner. Our observation contradicts the conventional belief that increasing supply voltage always reduces the failure rate in SRAMs. Because of thermal effects\, an increase in the supply voltage can also lead to increase in the SRAM failure rate. This thesis also extends the procedure of system level floorplanning to manage the leakage power and reliability of the design. The fundamental contribution of this thesis is that it advances the traditional design flow in the direction of incorporating thermal awareness during various stages of the flow.
URL:https://www.cecs.uci.edu/event/temperature-aware-vlsi-design-for-reduced-power-and-reliability-enhancement/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090527T150000
DTEND;TZID=America/Los_Angeles:20090527T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14323-1243436400-1243440000@www.cecs.uci.edu
SUMMARY:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems
DESCRIPTION:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems\nby Gabor Madl \nLocation: DBH 3011 \nDate and Time: May 27\, 2009 10:00am \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Tony Givargis\nProfessor Ian Harris \nAbstract:\nAs embedded systems become increasingly networked\, and interact with the physical world\, Distributed Real-time Embedded (DRE) systems emerge. DRE systems range from small-scale Multi-processor Systems-on-Chip (MPSoCs) operating in resource constrained environments such as cell phone platforms\, medical devices and sensor networks all the way to large-scale software-intensive systems of systems used in avionics\, ship computing environments\, and in supervisory control and data acquisition systems managing regional power grids. \nThis dissertation focuses on the model-based analysis of event-driven DRE systems. Event-driven DRE systems are based on a reactive communication paradigm\, where the execution of tasks is triggered asynchronously\, invoked by external events\, interrupts\, or by other tasks. Events can also express time\, providing a common semantic domain for the compositional analysis of time- and event-driven DRE systems. \nThe key technical contributions of this dissertation are (1) the specification of a formal semantic domain for DRE systems\, (2) a model checking method for the real-time verification of non-preemptive DRE systems using timed automata\, (3) a performance estimation method for DRE systems by discrete event simulations\, (4) a conservative approximation method for the verification of preemptive event-driven asynchronous DRE systems by timed automata\, (5) a method for the functional verification and performance estimation of MPSoCs built on an industry standard interconnect\, and (6) a cross-abstraction real-time analysis method for MPSoC designs utilizing bus matrix interconnects. \nThe novelty of our approach lies in combining formal methods and symbolic simulations for the system-level evaluation of DRE designs early in the design flow\, and utilizing multiple abstractions to trade off analysis accuracy in scalability. \nWe implemented the proposed analysis methods in the open-source Distributed Real-time Embedded Analysis Method (DREAM) framework for the model-based real-time verification and performance estimation of DRE systems. DREAM focuses on the practical application of formal analysis methods to automate the verification\, development\, configuration\, and integration of event-driven DRE systems. DREAM is available for download at http://dre.sourceforge.net. We applied the proposed design flow to the domain of software-intensive mission-critical avionics DRE applications\, and the domain of multimedia MPSoCs.
URL:https://www.cecs.uci.edu/event/model-based-analysis-of-event-driven-distributed-real-time-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090504T150000
DTEND;TZID=America/Los_Angeles:20090504T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14251-1241449200-1241452800@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n  \n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 4\, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm (Lecture Cancelled)\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090309T150000
DTEND;TZID=America/Los_Angeles:20090309T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T181037Z
LAST-MODIFIED:20231011T192457Z
UID:14252-1236610800-1236614400@www.cecs.uci.edu
SUMMARY:Nonlinear Symbolic Program Analysis for Increased Parallelization
DESCRIPTION:Nonlinear Symbolic Program Analysis for Increased Parallelization\n\n\n\n\nSpeaker\n\n\nProfessor Kleanthis Psarris \nDepartment of Computer Science\nThe University of Texas at San Antonio\, TX\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Nicolau\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 9\, 2009\nRefreshments at 2:30 pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHigh end parallel and multi-core processors rely on compilers to perform the necessary optimizations and exploit concurrency in order to achieve higher performance. However\, source code for high performance computers is extremely complex to analyze and optimize. In particular\, program analysis techniques often do not take into account complex expressions during the data dependence analysis phase. Most data dependence tests are only able to analyze linear expressions\, even though non-linear expressions occur very often in practice. Therefore\, considerable amounts of potential parallelism remain unexploited. In this talk we propose new data dependence analysis techniques to handle such complex instances of the dependence problem and increase program parallelization. Our method is based on a set of polynomial time techniques that can prove or disprove dependences in source codes with non-linear and symbolic expressions\, complex loop bounds\, arrays with coupled subscripts\, and if-statement constraints. In addition our algorithm can produce accurate and complete direction vector information\, enabling the compiler to apply further transformations. To validate our method we performed an experimental evaluation and comparison against the I-Test\, the Omega test and the Range test in the Perfect and SPEC benchmarks. The experimental results indicate that our dependence analysis tool is accurate\, efficient and more effective in program parallelization than the other dependence tests. The improved parallelization results into higher speedups and better program execution performance in several benchmarks.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nKleanthis Psarris is Professor and Chair of the Department of Computer Science at the University of Texas at San Antonio. His research interests are in the areas of Parallel and Distributed Systems\, Compilers and Programming Languages. He received his B.S. degree in Mathematics from the National University of Athens\, Greece in 1984. He received his M.S. degree in Computer Science in 1987\, his M.Eng. degree in Electrical Engineering in 1989 and his Ph.D. degree in Computer Science in 1991\, all from Stevens Institute of Technology in Hoboken\, New Jersey. He has published extensively in top journals and conferences in the field and his research has been funded by the National Science Foundation and Department of Defense agencies. He is an Editor of the Parallel Computing journal. He has served on the Program Committees of several international conferences including the ACM International Conference on Supercomputing (ICS) in 1995\, 2000\, 2006 and 2008\, the IEEE International Conference on High Performance Computing and Communications (HPCC) in 2008 and 2009\, and the ACM Symposium on Applied Computing (SAC) in 2003\, 2004\, 2005 and 2006.
URL:https://www.cecs.uci.edu/event/nonlinear-symbolic-program-analysis-for-increased-parallelization/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090227T150000
DTEND;TZID=America/Los_Angeles:20090227T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14324-1235746800-1235750400@www.cecs.uci.edu
SUMMARY:Automatic Design and Optimization of Application Specific Processors
DESCRIPTION:Automatic Design and Optimization of Application Specific Processors\nby Jelena Trajkovic \nThe stringent performance and power requirements of modern applications have fueled the need for application specific computing platforms. Conventional general purpose embedded processor do not provide the necessary throughput for meeting the applications’ performance and power needs. On the other hand\, manual hardware design is too expensive and results in inflexible implementation. The short time to market demands also make hardware design prohibitive. Therefore\, there exists a need for automatic design methods and tools that provide a high performance\, programmable and energy-efficient implementation starting from standard application descriptions such as C reference code. High level synthesis and application specific processor tools are a step in this direction\, but suffer from scalability\, quality and controllability issues. In this dissertation\, we present techniques for automatic processor design from C code that are scalable to thousands of lines of C code\, are controllable at each step of the design process and provide quality of results comparable to manual design. \nOur contributions enable a system level design methodology for application specific processors that starts with a reference C code of the application. An initial processor data path is constructed from a database of available components such as function units\, register files and buses. The initial data path is based on the types of operations and available concurrency in the application. The data path is then iteratively refined until an efficient architecture is derived. The key optimization goal is to keep performance within given boundaries while maximizing resource utilization. We further optimize the processor design using a novel algorithm for automatic custom pipelining based on the C code. The pipelining optimization also targets both resource utilization and performance. Our experimental results with large applications such as DCT and MP3 decoder show that automatically generated architectures are comparable to manual designs\, but can be obtained in a matter of few seconds\, leading to significant productivity gains. \nOur final contribution to design methods for embedded systems deals with low power memory design. Typically\, DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high\, exceeding that of the data cache or even that of the processor. We present and evaluate a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small\, cache-like structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption\, 23%\, on average\, and reduction in the energy-delay product\, 44%\, on average. The approach also improves performance: the CPI is reduced by 26%\, on average.
URL:https://www.cecs.uci.edu/event/automatic-design-and-optimization-of-application-specific-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081119T150000
DTEND;TZID=America/Los_Angeles:20081119T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14282-1227106800-1227110400@www.cecs.uci.edu
SUMMARY:My Work and My Life
DESCRIPTION:by Prof. Leonard KleinrockDepartment of Computer Science\nUniversity of California\, Los Angeles\nMcDonnell Douglas Auditorium\nDistinguished Lecture\, November 19\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/my-work-and-my-life/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081104T150000
DTEND;TZID=America/Los_Angeles:20081104T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192254Z
UID:14243-1225810800-1225814400@www.cecs.uci.edu
SUMMARY:Geppeto*: Consumer’s Approach to Programming
DESCRIPTION:Prof. Sinisa Srbljic\, School of Electrical Engineering and Computing\, University of Zagreb\, CroatiaNovember 4\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/geppeto-consumers-approach-to-programming/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080709T150000
DTEND;TZID=America/Los_Angeles:20080709T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14325-1215615600-1215619200@www.cecs.uci.edu
SUMMARY:Improving Packet Latencies of Live Streams in Wired Networks
DESCRIPTION:Improving Packet Latencies of Live Streams in Wired Networks\nby Arijit Ghosh (Advisor: Prof. Tony Givargis)\nDate: July 9\, 2008 \nLive streaming is becoming increasingly popular. In a study published in January 2008\, Cisco predicted that Internet-to-TV video will account for 30% of all Internet traffic. If all kinds of video traffic are considered\, then it will be 90% of consumer traffic by 2012. We distinguish live streams from on demand streams. Live streams are sent as the data is being generated\, is typically of long duration\, requires high bandwidth and associated with flash crowd behavior. As such\, live streams place tremendous demand on network resources. \nIn this thesis\, we proposed network techniques to improve packet latencies of live streams in wired networks. In particular\, we made the following contributions. First\, we proposed a technique that allows multicasting at the access network\, the proverbial last mile which presents tremendous bandwidth limitations. Second\, we reduced nodal processing by a tunelling scheme based on source routing. Essentially\, using routing computed at source and a novel network encoding scheme\, we eliminated intermediate processing. Third\, we presented a queueing algorithm that schedules packets based on application deadlines\, reduces the number of sorting iterations\, thereby improving performance\, has low complexity\, exhibits good fairness and provides a bounded delay for a single packet that is independent of the number of flows. Finally\, we proposed a variation of QoS routing that works with only partial network state information.
URL:https://www.cecs.uci.edu/event/improving-packet-latencies-of-live-streams-in-wired-networks/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080708T150000
DTEND;TZID=America/Los_Angeles:20080708T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14326-1215529200-1215532800@www.cecs.uci.edu
SUMMARY:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems
DESCRIPTION:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems\nby Minyoung Kim (Advisor: Prof. Nikil Dutt)\nDate: July 8\, 2008 \nResource limited mobile real-time embedded systems can benefit greatly from  dynamic adaptation of system parameters. This thesis proposes a novel framework  xTune that employs iterative tuning using light-weight formal verification at runtime with feedback for dynamic adaptation. One objective of this approach is to enable tradeoff analysis across multiple layers (for example\, application\, middleware\, operating system) and predict the possible property violations as the system evolves dynamically over time. Specifically\, an executable formal specification is developed for each layer of the mobile real-time system under consideration. The formal specification is then analyzed using statistical model checking and statistical quantitative analysis\, to determine the impact of various resource management policies for achieving desired a variety of end-to-end properties in a quantifiable manner. The integration of formal analysis with dynamic behavior from system execution results in a feedback loop that enables model refinement and further optimization of policies and parameters. Finally\, we propose a composition method for coordinated interaction of optimizers at different layers. The core idea of our approach is that each participating optimizer can restrict its own parameters and exchange refined parameters with its associated layers. We demonstrate the applicability of the proposed methodology to the adaptive provisioning of mobile real-time embedded systems by treating a multimedia case study on resource-limited devices.
URL:https://www.cecs.uci.edu/event/xtune-a-formal-methodology-for-cross-layer-tuning-of-mobile-real-time-embedded-systems/
CATEGORIES:PhD Defenses
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DTSTART;TZID=America/Los_Angeles:20080616T150000
DTEND;TZID=America/Los_Angeles:20080616T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14327-1213628400-1213632000@www.cecs.uci.edu
SUMMARY:A Runtime System for Memory-Constrained Distributed Embedded Systems
DESCRIPTION:A Runtime System for Memory-Constrained Distributed Embedded Systems\nby Jiwon Hahn (Advisor: Prof. Pai Chou)\nDate: June 16\, 2008 \nWearable and embedded wireless sensor platforms are often highly constrained in size and power consumption in order to operate in unintrusive ways. To meet these constraints\, the memory is kept as small as possible to reduce area and power\, but at the same time it poses new challenges on programming. To address these problems\, this dissertation proposes \n(1) a framework for synthesis of host-assisted scripting engines\, \n(2) a minimum-overhead yet powerful runtime system based on recursive threaded code\, and \n(3) a host-assisted memory optimization technique that exploits high-level knowledge in models of computation. The benefits are three-fold: first\, the interactive access between programmer and embedded system improve productivity of programmers. Second\, the low runtime overhead and memory requirements enable this runtime system to run on compact platforms while providing high flexibility and composability. Third\, a new memory optimization scheme combined with the dispatching structure expose regularity of dataflow models to enable memory and scheduling optimizations\, sometimes in ways better than manual coding. \nExperimental results show that systems developed using these techniques have unleashed the power of these resource-constrained distributed embedded systems. As memory is currently the limiting factor\, the lightweight runtime system and systematic memory optimization technique presented in this dissertation are enabling technology for a new class of real-world\, ultra-compact distributed embedded systems.
URL:https://www.cecs.uci.edu/event/a-runtime-system-for-memory-constrained-distributed-embedded-systems/
CATEGORIES:PhD Defenses
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T190240Z
CREATED:20231011T190240Z
LAST-MODIFIED:20231011T190240Z
UID:14375-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:CECS DAC Open House
DESCRIPTION:The 45th Design Automation Conference (DAC) is being held in Anaheim\, CA on June 8-13\, 2008. CECS cordially invites DAC attendees to an Open House on Friday afternoon\, June 13\, 2008 from 2:00PM to 4:00PM in our CECS office on the 2rd floor of the Anteater Instruction & Research Building (AIRB). We are planning a buffet of sandwiches\, cookies\, and soft drinks for a relaxed atmosphere. Many of our research affiliates and graduate students will be available to informally discuss new directions in technology and research.\nFor those attending DAC\, kindly consider attending this open house to see first hand our research programs and visit with our professors and graduate students. We are planning an informal environment and hope you will attend and enjoy the CECS hospitality.\nView Flyer with Directions
URL:https://www.cecs.uci.edu/event/cecs-dac-open-house/
CATEGORIES:Other Events
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DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14244-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models
DESCRIPTION:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models\n\n\n\n\nSpeaker\n\n\nDr. Christian Haubelt\nUniversity of Erlangen-Nuremberg\, Germany\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Tower\, Room 331\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 13 \, 2008\nTalk begins 11:00am\nRefreshments at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n80% of all design decisions are made in the first 20% of the design time. Thus\, a substantiated knowledge about possible solutions is mandatory in early design phases in order to design high quality products. SystemCoDesigner is a software tool for automatic design space exploration at the electronic system level and for platform-based prototyping of hardware/software systems. By exploring the design space\, a designer becomes more confident in decisions to be done. Starting from a behavioral SystemC description different solutions are generated automatically by using software synthesis techniques and Forte Design Systems’ Cynthesizer for behavioral hardware synthesis. In order to allow such a degree of automation\, SystemCoDesigner requires the behavioral SystemC model to be representable in a well-defined Model of Computation\, called FunState. As a case study\, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput\, ranging from software only solutions up to pure hardware implementations which reach real-time performance for QCIF streams on a 50MHz FPGA. In this talk\, the SystemCoDesigner overall design flow\, the FunState Model of Computation\, and some automatic transformation are presented using the Motion-JPEG case study.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nChristian Haubelt received his diploma degree in Electrical Engineering from the University of Paderborn\, Germany\, in 2001. He received his Ph.D. in Computer Science from the University of Erlangen-Nuremberg\, Germany\, in 2005. Since 2004\, he is head of the System-Level Design Automation Group at the Chair of Hardware/Software Co-Design\, University of Erlangen-Nuremberg\, Germany. Dr. Haubelt’s research interests include electronic system level design\, system level design automation\, and multi-objective optimization.\n\n\n\n\n\n\n\n\n\n\nWeb Site\n\n\nhttp://www12.informatik.uni-erlangen.de/people/haubelt/
URL:https://www.cecs.uci.edu/event/systemcodesigner-automatic-design-space-exploration-and-rapid-prototyping-from-behavioral-models/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080604T150000
DTEND;TZID=America/Los_Angeles:20080604T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14328-1212591600-1212595200@www.cecs.uci.edu
SUMMARY:Source Re-coding to Create Parallel and Flexible MPSoC Models for Embedded System Design and Exploration
DESCRIPTION:by Pramod Chandraiah\, University of California\, Irvine\nJune 4\, 2008\nview details
URL:https://www.cecs.uci.edu/event/source-re-coding-to-create-parallel-and-flexible-mpsoc-models-for-embedded-system-design-and-exploration/
CATEGORIES:PhD Defenses
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080512T150000
DTEND;TZID=America/Los_Angeles:20080512T160000
DTSTAMP:20231011T184119Z
CREATED:20231011T184119Z
LAST-MODIFIED:20231011T184119Z
UID:14329-1210604400-1210608000@www.cecs.uci.edu
SUMMARY:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip
DESCRIPTION:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip\nby Sudeep Pasricha (advisor: Prof. Nikil Dutt)\nDate: May 12\, 2008 \nWith the increasing performance demands of emerging convergence applications and advances in process technology\, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance\, power\, cost and reliability. Consequently\, the design\, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today. \nIn this dissertation\, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis\, comprehensively and automatically generating both the topology and protocol parameters\, while trading off multiple design constraints such as power\, performance\, area and cost.Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality\, better complexity management\, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs.
URL:https://www.cecs.uci.edu/event/commsyn-on-chip-communication-architecture-synthesis-for-multi-processor-systems-on-chip/
CATEGORIES:PhD Defenses
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