BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CECS
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20100314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20101107T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20110313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20111106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20120311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20121104T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20130310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20131103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20140309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20141102T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14406-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Models and Architectures for Heterogeneous System Design
DESCRIPTION:Speaker: Prof. Andreas Gerstlauer\, University of Texas\, AustinTitle: Models and Architectures for Heterogeneous System DesignDate: Monday\, May 6\, 2013Time: 11:00am – 12:00pmLocation: Harut Barsamian Colloquia Room (2430 Engineering Hall) \nHost: Prof. Rainer Dömer \nView Details
URL:https://www.cecs.uci.edu/event/models-and-architectures-for-heterogeneous-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190344Z
CREATED:20231011T190344Z
LAST-MODIFIED:20231011T190344Z
UID:14403-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Distinguished Lecture at CECS
DESCRIPTION:Speaker: Prof. Jorg Henkel\, Karlsruhe Institute of Technology\, GermanyTitle: A Thermal Perspective of Dependability in Systems on ChipDate: Monday\, February 25\, 2013Time: 11:00am – 12:00pmLocation: Harut Barasmian Colloquia Room (EH 2430) \nHost: Prof. Daniel Gajski \nView Details
URL:https://www.cecs.uci.edu/event/distinguished-lecture-at-cecs/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130524T150000
DTEND;TZID=America/Los_Angeles:20130524T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14401-1369407600-1369411200@www.cecs.uci.edu
SUMMARY:Designer-in-the-Loop Recoding for Creating Safe and Parallel ESL Models
DESCRIPTION:Date/Time: Thursday\, May 30\, 2013\, 10:00 a.m. – 11:00 a.m.Location: CECS Conference Room\, Engineering Hall 3206 \nCommittee Members:Rainer Dömer (Chair)Daniel GajskiFadi Kurdahi \nAbstractThe design complexity of embedded systems increases as more processors and subsystems integrated on one chip. In order to overcome the design bottlenecks and shorten time to market\, system engineers are motivated to design from a higher abstraction level\, namely Electronic System Level (ESL). ESL design methodology has emerged to address the design complexity by supporting HW/SW co-specification and co-simulation\, system design space exploration and high-level synthesis. \nESL design relies on an input ESL model\, namely the specification model. Creating structured and parallel specification models efficiently is a prerequisite for building cost-effective embedded systems in ESL design. Practically\, application reference code is reused to create the ESL models. However\, the referee models lack the necessary characteristics\, such as explicit parallelism\, structural hierarchy and synthesizability\, for ESL design. It is a time-consuming and error-prone process to manuallyrecode the reference models into desired ESL models. \nThis dissertation addresses on the automation gap of recoding. We follow the design-in-the-loop recoding methodology which efficiently combines the automation tools with designer’s knowledge. Our approach aim to expose parallelism in the ESL model and guarantee that the parallel model is safe from race conditions. \nFirst\, we identifies the essential steps in recoding and defines a recoding design flow to create safe and parallel ESL models.Second\, we contribute three automated recoding operations: variable dependency analysis to provide prompt analysis during model development\, race condition analysis to assist verifying and debugging the parallelism and a high-level transformation function to instantly create loop-level parallelism. Third\, we develop a recoding development platform based on Eclipse tointegrate recoding tools and facilitate the designer-in-the-loop approach. \nThe effectiveness of the recoding functions is shown with experiments on a set of embedded applications. Also\, an classroom experiment with 68 graduate students shows our recoding approach using the Eclipse-based recoding platform increases the productivity and reduces errors in parallel ESL model development.
URL:https://www.cecs.uci.edu/event/designer-in-the-loop-recoding-for-creating-safe-and-parallel-esl-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130520T150000
DTEND;TZID=America/Los_Angeles:20130520T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14410-1369062000-1369065600@www.cecs.uci.edu
SUMMARY:Context-based Service Performance Profile Management System in SOA
DESCRIPTION:Date/Time:  Tuesday\, May 28th\, 2:00 p.m. – 3:00 p.m. \nLocation:  Engineering Hall 4106 \nCommittee Chair:Kwei-Jay Lin \nAbstractService-Oriented Architecture (SOA) is a software paradigm for providing a uniform means to discover\, interact with and use capabilities to produce desired effects consistent withmeasurable preconditions and expectation. SOA also provides a framework for service com-position by putting together of a number of services to make a more complex one to fulfill a business process and service reconfiguration by replacing faulty services with better perform-ing services to have seamless business process execution. In general\, service integration tries to maximize the performance of a business process such as to have a minimum latency\, the shortest response time\, the optimal reliability\, an acceptable level of security and so on. Al-though technology exists to optimize the performance in terms of the above QoS attributes\, it still may not meet the need of all users\, since user may have unique service requirement at some specific context. \nIn order to address this issue\, in this dissertation\, we present an approach to improve over-all performance for the execution of business process by considering context-based serviceperformance profile management through Context Manager. Context Manager is designed to collect service performance feedback from users along with their context data\, maintainservice performance profile data\, distinguish influential context for service performance\, pre-dict how the service would perform under user context and provide most-adaptive service for user context.Our experiment results indicate that context manager system effectively maintains service performance profile data\, clearly understands the influence of some specific context attributes on service performance and provides context-adaptive services as users expect. Moreover\, integrating context-awareness into SOA brings significant performance improvement in terms of lower rate of service failure and reconfiguration\, and more optimal response time between service requester and service provider.
URL:https://www.cecs.uci.edu/event/context-based-service-performance-profile-management-system-in-soa/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130513T150000
DTEND;TZID=America/Los_Angeles:20130513T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14400-1368457200-1368460800@www.cecs.uci.edu
SUMMARY:Embedded Computer Vision Systems for Image Based Motion and Speckle Image Analysis
DESCRIPTION:Date/Time:  Friday\, May 10\, 2013\, 2:00 p.m. – 3: 00p.m.Location:  4011 Donald Bren Hall \nCommittee Members:\nPai H. Chou (Chair)\nBernard Choi\nGlenn Healey\n \nAbstract:  Motion is common in taking images using conventional cameras. If there is motion either on camera or the object or on the both sides during the exposure time\, the image is blurred\, which is called motion blurred image. Motion blurred image is an interesting research subject in several areas including computer vision\, biomedical engineering. In general\, motion is undesirable to acquire clear image. Modern cameras are equipped with the mechanical structure to compensate motion artifact. However\, mechanical structure has limit in compensating huge motion. To compensate huge motion\, computer vision algorithm called motion deblurring is developed. Basically\, it estimates the best latent image from the blurry image using several assumptions (or priors) on the latent image and camera motion. The information included in the motion blur can be useful for biomedical applications. Laser speckle imaging is one good example. When laser light of certain frequency (visible laser is widely used) is illuminated on the skin\, the scattered laser light from the surface has random distribution if there is no motion. With motion\, the speckle pattern is interfered by the motion and no longer random for the region with motion. Since the laser light can penetrate into skin\, it is possible to measure blood perfusion near skin without invasion. Both motion deblurring and laser speckle imaging require huge computation time. That is the reason why they are developed on personal computers or workstations. However\, the physical size\, power consumption\, and cost make them harder to penetrate into wider-range of applications (e.g. A super-fast motion deblurring algorithm that can run on embedded platforms like portable digital cameras or smart phones or portable laser speckle imaging system for an emergency vehicle). Nowadays\, embedded processors become more and more powerful. The CPU clock frequency of those processors have already passed 1Ghz. Some of them use multiple number of cores for processing like x86 processors. However\, even with such high performance processors\, special design considerations are required. In this dissertation\, we suggest embedded hardware and software systems for motion deblurring and laser speckle imaging applications. In the first part of the dissertation\, we will discuss about our motion deblurring systems. We developed an extremely light-weight motion deblurring algorithm to make it fast enough to be suitable for embedded computing platforms. The developed algorithm is up to 100 times faster than the most recent deblurring algorithms. We also developed a hardware/software system for extremely accurate motion deblurring. The hardware system is composed of IMU\, a control board\, and the Microsoft Kinect. Using the hardware system and software algorithm\, our system can reconstruct the relative motion of each pixel during the exposure time with 6-DoF. The second part is about the embedded laser speckle imaging systems that we developed. The mobile LSI (mLSI) system is a battery-powered laser speckle imaging system to meet the portability requirements of special applications (e.g. emergency vehicle\, battle field). We designed the automated power control (APC) circuit based laser diode driver to reduce the power consumption while maintaining the accuracy of the data. We evaluated the pulsed operation of the laser diode with always-on operation using the driver. The mLSI system showed equivalent performance from the evaluation with the clinical LSI system. The small field of view of conventional LSI systems is not adequate to be used for the applications that require fast treatment on large area (e.g. burn wounds). The multi-camera LSI (mcLSI) system was developed to address the requirement. mcLSI shows significant improvement in spatio-temporal resolution over conventional LSI systems. The unit based design enables users to expand the FoV without the sacrifice of the system performance (e.g. average speckle contrast\, spatial/temporal resolution).
URL:https://www.cecs.uci.edu/event/embedded-computer-vision-systems-for-image-based-motion-and-speckle-image-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130508T150000
DTEND;TZID=America/Los_Angeles:20130508T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14399-1368025200-1368028800@www.cecs.uci.edu
SUMMARY:Cooperative Communication for Wireless Physical Layer Security
DESCRIPTION:Date/Time: Friday\, May 10\, 2013\, 11:00 a.m. – 12:00 p.m.Location: 3206 Engineering Hall  \nCommittee Members:Professor A. Lee Swindlehurst (Chair)Professor Ender AyanogluProfessor Ahmed Eltawil \nAbstract:Cooperative communication in relay networks facilitates high spectral efficiency and large wireless transmission coverage. Despite the advances of improved cooperative diversity and flexible node deployment\, the relay network has more transmission nodes exposed in wireless environment than conventional single hop network\, and also extends the area over which the private transmitted signals may be intercepted by unintended receivers or eavesdroppers. Unlike the traditional approach of cryptographic design in the application layer\, in this work we investigate security issues in relay networks from a physical layer perspective. \nWe start with a two-hop multiple-input multiple-output (MIMO) relay network and propose cooperative beamforming and jamming strategies to maximize the secrecy rate. The corresponding power allocation is also optimized via geometric programming. Both cases with known and unknown eavesdropper’s channel state information (ECSI) are considered. Next\, we study a case where the relay is untrusted although it helps with forwarding message to the destination. The exact secrecy outage probability (SOP) is characterized with the impact of the number of antennas at the relay. Antenna selection\, beamforming and node selection schemes are proposed to suppress the wiretapping ability of the untrusted relay. Then we consider utilizing a buffer-aided relay that can dynamically control its receive and transmit phases. A link selection scheme that takes into account both the two-hop transmission efficiency and security constraints is proposed and shown to significantly improve the secrecy throughput. Finally\, we study robust transmit design when the relay acts as a pure cooperative jammer. The ECSI is assumed to be partially known and norm-bounded. The transmit covariance matrices are optimized via semidefinite programming\, based on maximizing the worst-case secrecy rate. Through this work\, we show that by taking advantage of the features of relay networks\, the security performance can be significantly improved in terms of secrecy rate and secrecy outage probability.
URL:https://www.cecs.uci.edu/event/cooperative-communication-for-wireless-physical-layer-security/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130322T150000
DTEND;TZID=America/Los_Angeles:20130322T160000
DTSTAMP:20231011T190322Z
CREATED:20231011T190322Z
LAST-MODIFIED:20231011T190322Z
UID:14398-1363964400-1363968000@www.cecs.uci.edu
SUMMARY:Delft Reconfigurable VLIW Processor
DESCRIPTION:Speaker: Prof. Stephan Wong\, Computer Engineering Laboratory\, Delft University of Technology\, NetherlandsLocation: 2111 Engineering HallDate/Time: Tuesday\, March 26\, 2013\, 2:00pm to 3:00pmView Details 
URL:https://www.cecs.uci.edu/event/delft-reconfigurable-vliw-processor/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130221T150000
DTEND;TZID=America/Los_Angeles:20130221T160000
DTSTAMP:20231011T190321Z
CREATED:20231011T190321Z
LAST-MODIFIED:20231011T190321Z
UID:14396-1361458800-1361462400@www.cecs.uci.edu
SUMMARY:A Thermal Perspective of Dependability in Systems on Chip
DESCRIPTION:Speaker: Prof. Jörg Henkel\, Karlsruhe Institute of Technology\, GermanyLocation: Harut Barsamian Colloquia Room (EH 2430)Date/Time: Monday\, February 25\, 2013\, 11:00am to 12:00pmView Details
URL:https://www.cecs.uci.edu/event/a-thermal-perspective-of-dependability-in-systems-on-chip/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130220T150000
DTEND;TZID=America/Los_Angeles:20130220T160000
DTSTAMP:20231011T192456Z
CREATED:20231011T190320Z
LAST-MODIFIED:20231011T192456Z
UID:14395-1361372400-1361376000@www.cecs.uci.edu
SUMMARY:Introduction to Consumer Computing
DESCRIPTION:Speaker:  Prof. Sinisa SrbljicLocation: Harut Barsamian Colloquia Room (EH 2430)Time/Date: Monday\, February 4\, 2013\, 11:00am-12:00pmView Details
URL:https://www.cecs.uci.edu/event/introduction-to-consumer-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130220T150000
DTEND;TZID=America/Los_Angeles:20130220T160000
DTSTAMP:20231011T193347Z
CREATED:20231011T190319Z
LAST-MODIFIED:20231011T193347Z
UID:14394-1361372400-1361376000@www.cecs.uci.edu
SUMMARY:An Online Methodology For Individualized Education
DESCRIPTION:by Daniel D. Gajski\, Quoc-Viet Dang\, and WenLiang He \nIntroduction\nOnline courses\, the latest hot topic in education\, have been debated by various sources\, including Governor Jerry Brown\, the UC regents\, and numerous college administrators\, faculty\, and students. The motivation behind such discussion is varied. Administrators see offering online courses as a way to increase the number of students despite the shortage of large lecture halls\, while generating some financial savings. Faculty and students are more skeptical\, fearing they will miss the face to face student-lecturer interaction in and out of the classroom. Of course\, with some traditional in-class courses\, having hundreds of students with varying backgrounds and motivation\, the student-lecturer interaction has already been severely diminished from smaller classroom sizes\, which are no longer feasible due to the shrinking educational budget. Since there is no standard in online education\, it has produced erratic results in terms of student performance and costs to students as well as administration. \nHowever\, online tools\, if managed and prepared for properly\, have the opportunity to provide the highly regarded individualized learning experience of the small classroom with the lower costs of large lecture halls while decreasing overall overhead costs. In fact\, the tools used for online courses can be utilized to improve the existing traditional classroom dynamic. Students are trained from high school to prepare for testing by memorizing as many facts and examples as possible in order to answer each question. On the other hand\, college professors tend to follow a top-down approach in teaching where they cover concepts\, some math or algorithms\, and methods or processes of finding proper solutions. These processes\, especially in Engineering\, must be understood and not just memorized because they have many steps involved: specification\, analysis\, design and synthesis\, optimization\, verification\, implementation\, and testing. In a small college classroom of 20-30 students\, lecturers can help students who fall behind individually by expending their out-of-class time. In a larger class of 150 students or more\, the small classroom teaching style doesn’t work as well since the time commitment for both the lecturer and students are dramatically increased for the same duration of time. \nThe tools and methodology presented in this article aid in providing the small classroom experience in a much larger setting while keeping overall costs and time commitment down. Such tools and methodology can be applied to any learning environment\, not just online\, to better prepare students for learning concepts and solving problems. It must cover \n(a)   Lectures \n(b)   Sample problems with solutions \n(c)   Questions and answers \n(d)   Homework \n(e)   Tests \nImproving a Typical In-Class Environment\nWe will compare the typical teaching methodology for a large classroom with a modified methodology that utilizes online tools to provide a richer learning environment for students. Our initial research compares two groups of students (Group A & Group B) taking a Digital Logic Design Engineering course during two separate quarters. Online course material consisted of custom content developed specifically for this Digital Design course as well as existing UCI tools through EEE (Electronic Educational Environment). We compare the students across 3 exams: \nExam 1: Both groups are taught based on a typical teaching methodology (overviewed below). Online lecture videos are available but no special emphasis is given to them. All material is covered in lecture and/or discussion sections. This exam is used to normalize the results for the following two exams. \nExam 2: Group A continues to be taught using the typical teaching methodology. Group B is presented with a typical Online course methodology. All lectures & samples are to be reviewed online via online videos. In-class lecture & discussion sections are now treated like online meetings; the professor and teaching assistants only cover questions asked and do not repeat any lectures. \nExam 3: Group A continues to be taught the typical teaching methodology. Group B is presented with a hybrid methodology based on in-class and online processes. A general lecture is given per topic each classroom session. Students are expected to review specific details and caveats that are covered by online videos & submit questions before the next classroom session. In the following lecture or discussion\, specific questions are answered that are submitted by students\, similar to an online course web meeting. \nA Typical In-Class Learning Environment\nThe in-class teaching environment was originally developed for small classes (20-40 students). However\, enrollment in many college courses has grown to over 100 students per class. Lectures for a couple hundred students in a large lecture hall for 1-2 hours are very difficult because \n(a)   schedulers have problems with room sizes and cannot schedule too many short lectures or discussions. \n(b)   a single presentation needs to cater to the varying skill levels and knowledge of all 100-200 students. \n(c)   many students are not prepared and have no questions\, exacerbating the above situations. Much of the information the students need is presented once in a lecture and/or discussion. If they miss the lecture or get lost on a concept taught\, they fall further and further behind as the class progresses. \nTherefore\, the presentation is general and not helpful to many students with weak backgrounds or insufficient skills while leaving other students bored and non-attentive. To help alleviate some of these issues\, sample problems can be covered in discussion sections with fewer students\, but the above situation still applies\, just on a smaller scale. Weekly homework is assigned to keep students on track; however\, due to learning habits from students’ past educational experiences\, assignments are generally completed to gain points rather than understanding the concept from the material. \nIn the typical in-class environment with ever increasing classroom size and varying student skill levels\, most of the lecture and discussion time available is used to cover examples\, go over homework solutions\, and prepare for testing. There is simply not enough time available to individualize the learning experience for many students with the current teaching methodology. \n  \nFigure A: A Typical In-Class Methodology Work Flow. \n  \nIn the figure above\, a typical in-class methodology is presented. Students are given a 1-2 hour lecture\, which may cover several concepts. During this time\, general questions are covered. Follow-up questions are not typically asked since students need to think about the material\, read more references\, or do some homework before they have additional questions. When they attempt the homework\, they may have initial questions. These are answered during the discussion section\, along with some follow-up questions from the lecture. This method is not efficient since it moves at the rate of the slowest students and much of the time is spent answering general questions since follow-up questions require additional review of the material. \nAdding an Online Methodology\nIn order to have more advanced discussion and cover concepts that help struggling students as well as advanced students in a large class\, the “what\, where\, when\, and how” of information to be presented and consumed must be improved upon. First\, we will address general lectures and sample problems. Traditionally\, they are presented in class\, leading to the problems described previously. By using online tools to “flip the classroom\,” a popular concept that has been around for years but is much better realized with the easy accessibility of the Internet\, we can cater to a much wider audience and more efficiently use our time in the classroom. Flipping the classroom involves moving most of the general lecture material from in-class to at-home. Students now review the general lectures and examples at home in between lectures while lectures are used to answer student questions and provide a more interactive and dynamic learning environment. \nLectures can be succinct and split into individual modules or concepts instead of a weekly 1-2 hour lecture session which usually covers several topics. Students can review the material multiple times\, refer to references at their own pace\, and discuss with classmates\, teaching assistants\, and the professor regarding the material presented. Classroom time can now be utilized for more advanced discussion and better targeted toward student skill levels based on the content they discuss through available online tools\, such as the course mailing lists and message boards. \nFigure B: A Typical Online Methodology Work Flow \n  \nIn the Online methodology work flow\, students begin by reviewing 15-20 minute lecture and/or example modules. Any initial questions regarding the lecture\, example\, or homework can typically be answered by reviewing the module again in more detail\, which is not typically possible with a traditional in-class environment. If there are follow-up questions\, they can be answered using online tools\, such as message boards or mailing lists. \nThe turn-around time per concept is much quicker than a typical in-class work flow and can happen multiple times throughout any given week. An in-class or streaming lecture and discussion can still take place; however\, note that the majority of questions asked now are follow-up questions\, which allows for more efficient use of interaction time and discussion of more advanced topics. The overall amount of time spent in this work flow is similar to the in-class work flow since lectures and discussions can be decreased in favor of using online tools and modules to cover the general concepts. Students can also work at their own pace\, allowing for a more individualized experience. \nPreliminary Results\nThe initial results are encouraging. We compared Group A & Group B as a whole\, as well as in 3 separate groups based on performance (top third\, middle third\, and bottom third). \nAs stated earlier\, we will be using Exam 1 as the normalization factor. Students in Group A & Group B received the same typical in-class teaching methodology for material leading up to Exam 1. On average\, students from Group B score between 4-8% lower than students in Group A. All other factors being equal\, we expect this performance to stay in that range. Since we change the teaching and learning methodology for Exam 2 & 3\, we expect some changes in performance as well. \nFor the material covered in Exam 2\, a typical online methodology was used\, which just moved lectures from in-class to online videos. This can help address in-class problems like scheduling of large lecture halls\, being able to present to students of varying skill levels by allowing them to choose the appropriate videos\, and keep overhead costs down in a general sense. There is a minor improvement in allowing the lecturer to reach out to students of different skill levels through the videos and online message boards; much of this effectiveness depends on the students’ willingness to and frequency of which they use the technology. Since some material is offloaded outside the classroom\, there is more time to spend on individual student questions during the classroom session. Similar to the video and online message board issue\, this also depends on the students’ motivation to take advantage of these opportunities. \nAs a whole\, students in Group B showed a marginal improvement over students in Group A (1.37%). When split into three separate groups based on performance\, the top third of students in Group B outperformed the top third of students in Group A by approximately 4.55% after normalization is considered\, the middle third of Group B did 1.27% better\, and the bottom third did 1.57% worse than Group A. \nIn an attempt to bring learning to a more individual level using online tools\, Group B students were taught using an online hybrid methodology that goes beyond the typical in-class or online methodologies for Exam 3. Students in Group A continued to receive a traditional in-class teaching educational environment. \nIn the hybrid methodology\, we combine the advantages of in-class and online environments. The classroom is still “flipped\,” where much of the learning is done outside of the classroom through online videos\, mailing lists\, and discussion on message boards in between scheduled class sessions. However\, we help guide students with introductory lectures and answer general questions during an early classroom session. Since a significant portion of the material is covered outside of the classroom\, there is more time for individualized help and advanced discussion in the classroom itself. From there\, students are required to go through online lecture and sample videos. Finally\, they must take notes and submit questions on concepts they wish to be discussed in following lectures. \nUsing this method\, students in Group B performed significantly better than students in Group A as a whole and as smaller groups. After the normalization factor\, Group B averaged 7.44% higher on the exam\, with the top third performing 6.24% better in Group B\, middle third 7.14% better\, and bottom third 9.18% better than Group A. \nTable 1: Group A vs Group B \n  \nStudent Feedback\nStudent feedback regarding the traditional\, online\, and hybrid methodologies have shown that online videos and tools are aiding in improving their overall performance. \nFirst\, we review how students ranked each format of instruction in terms of helpfulness in understanding the course content in Table 2. \nTable 2: Helpfulness of Different Formats of Instruction for Students in Group B \n  \nIn general\, online lecture and TA example videos are preferred to in-class lectures and examples. Reading the textbook is the least preferred of the 5 learning formats. As mentioned earlier\, lectures were not formatted as traditional lectures\, but were handled similar to Q&A type sessions; therefore\, the basic knowledge required for the class is presented in the videos. More time is spent discussing deeper concepts in-class\, which was more useful to students who were studying more often or participating more often in-class. TA examples were more popular than concept lectures since they are given similar homework problems and solutions to review. \nNext\, we look at how students are spending their time studying outside of the classroom in Table 3. \nTable 3: Study Habits of Students in Group B after Class \n  \nAgain\, students in our Digital Design Logic course preferred watching online lecture and TA example videos over reading textbooks. The videos were able to better target varying skill levels of students and could be updated throughout or between the quarters. Since students receive a general overview and more detailed example in short concise videos\, they can more efficiently prepare for the next lecture or homework as well as discuss problems rather than reading long chapters in a textbook. \nLastly\, we review how much time is actually spent studying for this course compared to other courses in Table 4. \nTable 4: Study Frequency of Students in Group B Outside of Class \n  \nConsidering 3-4 classes is a typical full-time course load\, students are studying more for this course than any other single course in their curriculum. This is due to the more rigorous studying methodology required for the Digital Design course including studying online videos\, completing homework based on the videos\, and submitting questions for lectures based on each set of online lecture and example videos. However\, they are still studying well under the 40 hours total that is typical of a full-time course load. A typical course requires about 10 hours per week of total studying; with more students studying in the 6-10 hour range\, we would expect the performance of the students to be even higher. \nConclusion\nThis modest sampling of using online teaching methods to improve an existing large in-class environment has been shown to be effective. Overall\, students have varying amounts of motivation to ensure they do well and get the most out of their learning experience. Initial feedback suggests that the online videos are well received once they are presented with our hybrid teaching methodology. By using online tools\, making small changes to how in-class sessions are utilized\, and adjusting how students learn inside and outside the classroom\, student performance can be increased without impacting factors such as cost and quality of education. In fact\, by utilizing new technology and spending time to find effective means of conveying concepts and materials like that of the hybrid online methodology we can provide a more individualized experience for larger student classes in this time of increased enrollment\,  with a small increase in the number of TAs\, and some initial online investment.
URL:https://www.cecs.uci.edu/event/an-online-methodology-for-individualized-education/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20121128T150000
DTEND;TZID=America/Los_Angeles:20121128T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14392-1354114800-1354118400@www.cecs.uci.edu
SUMMARY:Power-Saving Method for DRAM/eDRAM and 3D-DRAM expoliting the process variations\, temperature changes\, device degradation\, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service
DESCRIPTION:Date/Time: Friday\, December 7\, 2012\, 3:30-5:00PM\nLocation: Engineering Hall 3206 \nCommittee Members:\nProfessor Fadi Kurdahi (Chair)\nProfessor Ahmed Eltawil \nAbstract:\nIn this dissertation\, we have devised an innovative approach to dynamically set supply voltages and refresh cycle for Dynamic Random Access Memory (DRAM) and 1T1C embedded Dynamic Random Access Memory (eDRAM). The approach helps us to reduce power consumption. The DRAM/eDRAM is usually designed to sustain the worst operating conditions\, and the chip is very rarely operated under these conditions. We exploit the design slack while operating under more favorable conditions to power consumptions. Simulation results indicate that power consumption can be saved more than 10 times when the chip is normally operated. This keeps the chip cool and the operating temperature will be well under control\, which helps in averting device degradation and ultimate breakdown. In addition\, it is possible to extend the eDRAM data retention time\, which helps to improve the memory availability and system performance. Then a mixed-signal controller that implements our algorithm is presented in detail. Our proposed control circuit dynamically adjusts the supply voltages and the refresh cycle with an awareness of process variations\, temperature changes\, and device degradation to minimize power consumption or maximize memory availability. We use the Predictive Technology Model(PTM) 45nm to design and simulate the controller. The silicon area of the controller is only 0.052 mm2which is equivalent to the area of a 1.5 Megabit memory array. It operates at 100 MHz frequency and consumes about 260µW. Compared to a circuit which is designed to accommodate the worst case scenario\, we can save power consumption or extend the memory availability more than ten times when our chip operates under normal conditions. After that an innovative memory management approach which utilize both 3D-DRAM and external DRAM (ex-DRAM) is presented. Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive\, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads\, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for “latency sensitive”\, “bandwidth sensitive”\, and “insensitive” applications. To improve the performance and satisfy a certain level of QoS\, memory blocks of distinct application types are allocated differently. Compared to the scratchpad memory management mechanism\, the average memory access latency of our approach decreases by 19% and 23%\, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover\, using our approach\, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead\, particularly for applications which have high spatial memory locality. Finally\, we present a power-saving method for 3D-DRAM with an awareness of memory access workload variations. We dynamically and independently adjust supply voltages and refresh cycles of different 3D-DRAM dies to minimize their power consumption in the active and idle states. In fact\, the same power saving method for DRAM/eDRAM\, which exploits the design slack due to process variations and temperature changes\, is applied for 3D-DRAM. In both states\, we can still read/write normally and our method does not cause any performance overhead. The difference between these two states is the mechanism to minimize the power consumption: read/write operations and refresh operations consume the most power in the active and the idle state respectively. In addition\, we implement a memory relocation mechanism so that recently accessed memory blocks are gathered together into common 3D-DRAM dies. That allows the others to be in the idle state to save power consumption. The memory relocation mechanism is also an extension of the proposed heterogeneous memory management approach. The overhead of our memory relocation mechanism is negligible. Our simulation shows that if there is no memory access (all 3D-DRAM dies change into the idle state) our method can save power consumption up to 75%. If the memory access workload is low\, our method can save power consumption by almost 50%.
URL:https://www.cecs.uci.edu/event/power-saving-method-for-dram-edram-and-3d-dram-expoliting-the-process-variations-temperature-changes-device-degradation-and-memory-access-workload-variations-and-innovative-heterogeneous-memory-man/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120924T150000
DTEND;TZID=America/Los_Angeles:20120924T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14390-1348498800-1348502400@www.cecs.uci.edu
SUMMARY:Cyber-Physical Systems at Small and Large Scales
DESCRIPTION:Speaker:  Prof. Marilyn Wolf\, Georgia Institute of TechnologyLocation:  4011 Donal Bren Hall\nDate/Time: Friday\, September 28\, 2012\, 2:00-3:00PM\nView Details
URL:https://www.cecs.uci.edu/event/cyber-physical-systems-at-small-and-large-scales/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120906T150000
DTEND;TZID=America/Los_Angeles:20120906T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14389-1346943600-1346947200@www.cecs.uci.edu
SUMMARY:Flexible Error Handling for Resource-Constrained Embedded Systems
DESCRIPTION:Speaker:  Dr. Michael Engel\, TU Dortmund University\, GermanyLocation:  2430 Engineering Hall\nDate/Time:   Friday\, August 31\, 2012\, 2:30-4:00PM\nView Details
URL:https://www.cecs.uci.edu/event/flexible-error-handling-for-resource-constrained-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14308-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Millimeter-Wave Circuits for W-band Applications
DESCRIPTION:Location:Calit2 3355\nDate and Time: March 8th\, 2012\, 10:00AM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Filippo Capolino\nProfessor A. Lee Swindlehurst \nTitle: Silicon-Based Millimeter-Wave Circuits for W-band Applications \nAbstract:\nHistorically\, monolithic microwave integrated circuits (MMICs) have been designed using III-V semiconductor technologies\, such as GaAs and InP. In recent years\, the number of publications reporting silicon-based millimeter-wave (mm-wave) transmitter\, receivers\, and transceivers has grown steadily. For mm-wave applications including gigabit/s point-to-point links (57-64 GHz)\, automative radar (77-81 GHz) and imaging (94 GHz) to reach mainstream market\, the cost\, size and power consumption of silicon-based solution has to be significantly below what is being achieved today using compound seminconductor technology. This dissertation focuses the effort of designing and implementing silicon-based solutions through circuit- and system-level innovation for applications in the W-band frequency band (750110GHz)\, in particular\, 94GHz passive imaging band. \nA W-band front-end receiver in 65nm CMOS based entirely on slow-wave CPW (SW-CPW) with frequency tripler as the LO is designed and measured. The receiver achieves a total gain of 35-dB\, -3dB-BW of 12 GHz\, a NF of 9-dB\, a P1-dB of -40dBM\, a low power consumption of 108mW under 1.2/0.8V. This front-end receiver chipset in conjuction with an analog back-end can be used to form a radiometer. \nLeveraging the work done in 65nm CMOS\, the first integrated 2×2 focal-plane array (FPA) for passive imaging is implemented in a 0.18um SiGE BiCMOS process (ft/fmax=200/180GHz). The FPA incorporates four Dicke-type receivers. Each receiver employs a direct-conversion architecture consisting of an on-chip slot dipole antenna\, an SPDT switch\, a lower noise amplifier\, a single-balanced mixer\, an injection-locked frequency tripler (ILFT)\, a zero-IF variable gain amplifier\, a power detector\, an active bandpass filter and a synchronous demodulator. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four ILFTx. This work demonstrates the highest level of integration of any silicon-based systems in the 94GHz imaging band. \nFinally\, the main design bottleneck of any wireless transceiver system\, the frequency synthesizer/phase-locked loop is investigated. Two monolithically integrated W-band frequency synthesizer are presented. Implemented in a 0.18um SiGe BiCMOS\, both architectures incorporate the same 30.3-33.8GHz PLL core. One sythesizer uses an injection-locked frequency tripler (ILFT) with locking range of 92.8-98.1GHz and the other employ a harmonic-based frequency tripler (HBFT) with 3-dB bandwidth of 10.5GHz from 90.0-101.4GHz\, respectively. The frequency sythesizer is suitable for integration in mm-wave phased array and multi-pixel systems such as W-band radar/imaging and 120GHz Gb/s communication.
URL:https://www.cecs.uci.edu/event/silicon-based-millimeter-wave-circuits-for-w-band-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14307-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging
DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: March 8th\, 2012\, 2:00-3:30PM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Michael Green\nProfessor Peter Burke \nTitle: Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging \nAbstract:\nSilicon technology\, with its superior integration capability and low cost\, has changed the world dramatically during the past few decades and recently has entered the realm of millimeter-wave (MMW) system design that is used to be dominated by III-V compound semiconductor technologies. Benefiting from the continuous feature size scaling of silicon technology\, passive MMW imagers could be built on chip which paves the way for developing low-cost\, compact wafer-scale imagers. This dissertation focuses on the design of fully integrated W-band passive imager and also covers the design of W-band synthesizer which is one of the most critical and challenging building blocks of the imaging receiver. Two chips for 96GHz frequency generation incorporating the same Ka-band PLL and (1) an injection-locked frequency tripler (ILFT); (2) a harmonic-based frequency tripler (HBFT) in 0.18?m SiGe BiCMOS (fT/fmax=200/180GHz) are presented. The ILFT and HBFT preceded by the same Ka-band PPL achieve measured closed-loop phase noise of -93dBc/Hz and -92dBc/Hz at 1MHz offset\, respectively. Both chips are designed under the same power consumption of 14mW from 1.8V/2.5V supplies. This work presents the first implementation of an injection-locked-based frequency multiplier in SiGe BiCMOS process. W-band transformer-based injection-locked frequency tripler (T-ILFT) is also designed and implemented in 65nm standard CMOS technology using a 0.8V supply voltage. THe use of injection locking topology with on-chip transformer provides several advantages over conventional design. A fully integrated W-band 2×2 focal-plane array (FPA) for passive millimeter-wave imaging is demonstrated in 0.18?m SiGe BiCMOS process. The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture with an on-chip slot folded dipole antenna. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. This imaging receiver (without antenna) achievers a measured average responsivity and noise equivalent power of 285MV/W and 8.1fW/Hz1/2\, respectively\, across the 86-106GHz bandwidth\, which results a calculated NETD of 0.48K with a 30ms integration time. The system NETD increases to 3K with on-chip antenna due to its low efficiency at W-band. This work demonstrates the highest integration level of any silicon-based systems in the 94GHz imaging band.
URL:https://www.cecs.uci.edu/event/silicon-based-integrated-circuits-for-w-band-fully-integrated-passive-imaging/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120627T150000
DTEND;TZID=America/Los_Angeles:20120627T160000
DTSTAMP:20231011T181236Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T181236Z
UID:14257-1340809200-1340812800@www.cecs.uci.edu
SUMMARY:Addressing Supply Chain Security with Split Manufacturing
DESCRIPTION:Addressing Supply Chain Security with Split Manufacturing\n\n\n\n\nSpeaker\n\n\nDr. Ted Huffmire\nNaval Postgraduate School\, Monterey\, California\n\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDBH 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 27\, 2012\nSeminar begins at 11:00am\, Refreshment at 10:45am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nSecurity is an essential design goal in computer architecture\, and security is a concern throughout the entire lifecycle of a system. The process of designing hardware requires trusting intellectual property (IP) cores and computer-aided design (CAD) tools developed by third parties\, as well as the fabrication\, packaging\, assembly\, and delivery of the final system. Valuable IP is vulnerable to theft and modification during tape-out\, even if a perfect design free of security flaws is sent to the foundry. Of course\, no design is ever perfect\, and having a trusted foundry does not solve the problem of flawed designs. Furthermore\, the trusted foundry may not have the capability to deliver the most aggressive technology node\, volume\, yield\, or cost. Even the extraordinary step of building everything from scratch in-house\, including all of the tool chains\, both digital and analog\, is not guaranteed to result in a trustworthy design.  \nThis short\, informal\, seminar-style talk will explore three split manufacturing approaches for addressing hardware supply chain security: reconfigurable hardware\, 2D IC split manufacturing\, and 3D IC split manufacturing. Reconfigurable hardware allows the design to be loaded onto a field-programmable gate array (FPGA) device in a secure facility after fabrication. With 2D IC split manufacturing\, different metal layers of the same wafer are fabricated in different foundries\, one of which is a trusted foundry. With 3D IC split manufacturing\, two or more individual die are fabricated in different foundries\, one of which is a trusted foundry\, and then assembled in a trusted facility. The challenges and opportunities of each of these approaches will be compared and contrasted\, as well as the viability of split manufacturing in general.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nTed Huffmire is an Assistant Professor of Computer Science at the Naval Postgraduate School in Monterey\, California. His research spans both computer security and computer architecture\, focusing on hardware-oriented security and the development of policy enforcement mechanisms for application-specific devices. He has a Ph.D. in computer science from the University of California\, Santa Barbara. He is a member of the IEEE and the ACM. The views presented in this talk are those of the speaker and do not necessarily reflect the views of the United States Department of Defense
URL:https://www.cecs.uci.edu/event/addressing-supply-chain-security-with-split-manufacturing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120612T150000
DTEND;TZID=America/Los_Angeles:20120612T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181235Z
LAST-MODIFIED:20231011T192031Z
UID:14254-1339513200-1339516800@www.cecs.uci.edu
SUMMARY:Architectural Modeling of Embedded Systems - Challenges and Opportunities
DESCRIPTION:Architectural Modeling of Embedded Systems – Challenges and Opportunities\n\n\n\n\nSpeaker\n\n\nDr. Achim Rettberg\nCarl von Osseitzky University Oldenburg\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Rainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall 3216\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 12\, 2012\nColloquium begins at 2:00PM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nToday embedded system design has to cover the increasing complexity and has to fulfil requirements. With traditional design methods the time-to-market is to long. New design methods as model-based design offers the reduction of product development time\, but it requires a different development process. This talk will give an overview of model-based design and show the complexity designers have to cope with. The idea to realize the system based on a virtual platform will also be covered in the talk. The reference technology platform (RTP) proposed and developed at OFFIS Institute (Oldenburg\, Germany) will be presented. The RTP gives the designer an excellent overview of the system and allows requirement coverage and analysis.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nACHIM RETTBERG was born in Einbeck\, Germany. He received his M.S. (Dipl.-Inform.) in computer science and economics in 1997 and his Ph. D. (Dr. rer. nat.) degree in 2006 from the University of Paderborn\, Germany\, where he studied computer science and economics. From 1992 until 1997 he was employed as a working student for the University of Paderborn and C-LAB. From 1997 until 2000 he worked at C-LAB in industrial projects together with dSPACE and Siemens. From 2001 until 2006 he worked as a Ph.D. student and researcher for the C-LAB in the field of embedded system design. Afterwards he worked from 2007 until 2008 as Post-Doc at C-LAB and managed EU-Projects. In 2008 he became professor of complex integrated systems/embedded systems at the Computer Science department at Carl von Ossietzky University Oldenburg. Prof. Rettberg is founder and General Chair of the International Embedded Systems Symposium (IESS). Furthermore\, he is active in several conference/workshop committees and reviewers for journals. Prof. Rettberg is author and co-author of several scientific books\, journal articles and conference papers. His general research interests are model-based design\, real-time systems and HW/SW architectures. He is chairman of the IFIP working group 10.2 for embedded systems.
URL:https://www.cecs.uci.edu/event/architectural-modeling-of-embedded-systems-challenges-and-opportunities/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120531T150000
DTEND;TZID=America/Los_Angeles:20120531T160000
DTSTAMP:20231011T182435Z
CREATED:20231011T182435Z
LAST-MODIFIED:20231011T182435Z
UID:14258-1338476400-1338480000@www.cecs.uci.edu
SUMMARY:Flash Memory Management for Embedded Systems
DESCRIPTION:Prof. Zili Shao\n	Hong Kong Polytechnic University\n	DBH 3011\n	Seminar\, May 31\, 2012\n	Abstract
URL:https://www.cecs.uci.edu/event/flash-memory-management-for-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120514T150000
DTEND;TZID=America/Los_Angeles:20120514T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14306-1337007600-1337011200@www.cecs.uci.edu
SUMMARY:Enhancing Quality of Viewing Experience for Future Mobile Video Applications
DESCRIPTION:by Kiarash Amiri May 14\, 2012 view details
URL:https://www.cecs.uci.edu/event/enhancing-quality-of-viewing-experience-for-future-mobile-video-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120502T150000
DTEND;TZID=America/Los_Angeles:20120502T160000
DTSTAMP:20231011T182435Z
CREATED:20231011T182435Z
LAST-MODIFIED:20231011T182435Z
UID:14259-1335970800-1335974400@www.cecs.uci.edu
SUMMARY:COMS Process Variations: A "Critical Operation Point" Hypothesis"
DESCRIPTION:Dr. Janak H. PatelUniversity of Illinois at Urbana-Champaign\nDBH 3011\nDistinguished Lecture\, May 2\, 2012\nAbstract
URL:https://www.cecs.uci.edu/event/coms-process-variations-a-critical-operation-point-hypothesis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120301T150000
DTEND;TZID=America/Los_Angeles:20120301T160000
DTSTAMP:20231011T182435Z
CREATED:20231011T182435Z
LAST-MODIFIED:20231011T182435Z
UID:14260-1330614000-1330617600@www.cecs.uci.edu
SUMMARY:A Couple of Research Topics for UCI CECS Visit
DESCRIPTION:A Couple of Research Topics for UCI CECS Visit\n\n\n\n\nSpeaker\n\n\nDr. Pyung-Soo Kim\nKorea Polytechnic University\nKorea\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 1\, 2012\nSeminar begins at 2:00 PM\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk\, a couple of research topics for UCI CECS visit are presented.\nFirstly\, the finite memory structure (FMS) filter for state emstimation in state space models and its applications are briefly introduced.\nResearch issues on the application of FMS filter are introduced for mobile tracking system\, wireless sensor network\,\nbattery management system\, etc. Secondly\, as a basic principle of addressing architecture for Future Internet\, the identifer/locator split is briefly introduced. Research issues are also introduced in designing name space and name system for Future Internet based on the identifer/locator split.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nProf. Pyung-Soo Kim received the Ph.D. degree at the School of Electrical Engineering and Computer Science from Seoul National University\, Seoul\, Korea\, in 2001. From 2001 to 2005\, he was a senior researcher at the\nDigital Media R&D Center of Samsung Electronics Co. Ltd. Since 2005\, he has been with the Department of Electronics Engineering at Korea Polytechnic University\, Shiheung\, Korea. His main research interests are in the areas of system software solutions\, statistical signal processing\, wireless mobile networks\, Future Internet architecture design\, and various industrial applications.
URL:https://www.cecs.uci.edu/event/a-couple-of-research-topics-for-uci-cecs-visit/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120223T150000
DTEND;TZID=America/Los_Angeles:20120223T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14309-1330009200-1330012800@www.cecs.uci.edu
SUMMARY:Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures
DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: February 23\, 2012\, 3:30pm – 5:30pm \nCommittee:\nProfessor Ahmed Eltawil (Chair)\nProfessor Ender Ayanoglu\nProfessor Fadi Kurdahi \nTitle: Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures \nAbstract:\nMIMO communication has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. However\, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity. In this thesis\, we present efficient design for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels. We consider that the MIMO detector and the channel decoder are two major blocks and attempt to optimize them in a joint sense. First of all\, we will focus on the design of MIMO detector and propose two approaches. The first design presents a novel algorithm and architecture for K-Best detection. The algorithm examines a much smaller subset of points in the tree structure while still achieving near-optimal performance. The VLSI architecture of the detector is based on a pipelined sorter-free scheme such that high throughput is achieved. The second design demonstrates an algorithm and VLSI architecture of combining the features of classical depth-first and breadth-first methods. Techniques to reduce complexity while providing both hard and soft output detection are also presented. Finally we will present an approach to perform joint detection and decoding for MIMO systems using convolutional codes. The BER performance of this approach is significantly better than that of systems which utilize separate detection and decoding blocks. The proof of concept VLSI architecture is provided and a novel way to reduce memory usage is demonstrated.
URL:https://www.cecs.uci.edu/event/tree-search-based-mimo-detectors-algorithms-and-vlsi-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20111027T150000
DTEND;TZID=America/Los_Angeles:20111027T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14310-1319727600-1319731200@www.cecs.uci.edu
SUMMARY:Energy Harvesting and Power Optimization for Remote Sensing Systems
DESCRIPTION:Energy Harvesting and Power Optimization for Remote Sensing Systems\nby Sehwan Kim \nLocation: Engineering Gateway – CEE Conference Room \nDate and Time: October 27\, 2011 2:00pm \nCommittee:\nProf. Pai Chou (Chair)\nProf. Masanobu Shinozuka\nProf. Maria Feng \nAbstract:\nThe mobile and wireless micro-sensors suffer from short operational lifetimes because they lack space to store the energy that wireless transmission\, signal conditioning\, and monitoring require to operate across time. Energy harvesting capabilities enable totally untethered operation of mobile and wireless micro-sensors for extended periods of time without requiring battery replacement. This paper is to introduce and discuss the design challenges associated with harvesting circuits when harnessing\, conditioning\, and transferring power from ambient energy sources. In addition\, supercapacitors have emerged as an increasingly viable alternative to batteries for micro-solar energy harvesters. To address the problems of high leakage and high unusable residual charge\, previous work proposed multiple supercapacitors with a reconfigurable topology. We propose to optimize such systems by two ways: selection of optimal sizes of the supercapacitors at design time\, and choosing the optimal series or parallel topology at run time. This combination enables the supercapacitor subsystem to maximize the energy storage while minimizing leakage and residual energy\, thereby enabling the maximum utility of the energy storage elements over different operating scenarios.
URL:https://www.cecs.uci.edu/event/energy-harvesting-and-power-optimization-for-remote-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20111027T150000
DTEND;TZID=America/Los_Angeles:20111027T160000
DTSTAMP:20231011T182436Z
CREATED:20231011T182436Z
LAST-MODIFIED:20231011T182436Z
UID:14261-1319727600-1319731200@www.cecs.uci.edu
SUMMARY:Distributed Algorithms for the Self-organization of the Scale-free Network: Statistical Mechanics Inspired Methods
DESCRIPTION:Distributed Algorithms for the Self-organization of the Scale-free Network: Statistical Mechanics Inspired Methods\n\n\n\n\nSpeaker\n\n\nDr. Jae-Hyun Park\nChung-Ang University\,\nKorea\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 3206\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 27\, 2011\nSeminar begins at 11:00 AM\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRecently\, by physicists\, it has been recognized that the scale-free network is made by a simple random process\, if a kind of bias is given to purely random state of nodes in network. Because some biased physical quantities such as the availability of nodes are observed in real networks\, we devise a distributed algorithm for the self-organization of the scale-free network from this discovery. Each node independently tries to connect to the best node which is superior to the node itself and all the nodes that had been connected\, while the node received the request accepts it if the node asked is better than all the nodes that had been connected. Because each node deterministically finds out the candidate nodes in terms of partial order\, a partial order relationship among the nodes exists. Each node working for the related algorithms uses the state information changed over time. But the node working for the proposed algorithm uses the constant observable quantity of node state so it requires only one-time broadcasting to share all the global node state data. The number of broadcast messages is tremendously diminished. We also propose a distributed algorithm for which only local node state data is used. To devise the algorithm\, we analyze the scale-free network formation problem with the Statistical Mechanics\, from which we show the insight that\, if the degree-distribution of network is the power law\, each node is adjacent to symmetric sub-graphs (or indistinguishable links).\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Jae-Hyun Park received the B.S. degree in Computer Science from Chung-Ang University\, Korea\, in 1988\, and the M.S. and Ph.D. degrees in Computer Science from the KAIST\, Taejon\, in 1991 and 1995\, respectively. >From 1991 to 1994\, as a research staff of the Satellite Research Center in KAIST\, He had developed the embedded operating system for the onboard computer of KITSAT (the first Korean satellite). Especially\, he had modified the Nucleus RTX Kernel (real-time operating system kernel) for dynamic process creation in a mission control on-board computer system. This works was published in the Proc. of AIAA/IEEE Digital Avionics Systems Conference. As his Ph.D. research\, he did work on the fault-tolerant high-performance multistage interconnection networks for ATM switching and multiprocessing\, which was published in IEEE/ACM Trans. on Networking. From 1995 to 2000\, he was with the Samsung Electronics Co.\, Korea\, where he had developed the multiprotocol label switching system over the Asynchronous Transfer Mode Switching System\, including the development of the label distribution protocol\, which was published in IEICE Trans. on Comm. He received the 1996 Best Research Paper Award-Golden Prize in 1997 and the 1997 Award of Excellence in Research and Development-Silver Prize in 1998\, all from Samsung Electronics Co. From 2000 to 2002\, he was with the School of EECS\, Yeungnam University\, Korea. Since 2002\, he has been a professor of the School of Computer Science and Engineering\, Chung-Ang University\, Korea. His current research interests include switching architectures\, self-organization\, ad hoc networks\, and scale-free networks. He is a visiting scholar at UC Irvine\, hosted by Professor Pai H. Chou from February 2011 to January 2012.
URL:https://www.cecs.uci.edu/event/distributed-algorithms-for-the-self-organization-of-the-scale-free-network-statistical-mechanics-inspired-methods/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20111018T150000
DTEND;TZID=America/Los_Angeles:20111018T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T192254Z
UID:14255-1318950000-1318953600@www.cecs.uci.edu
SUMMARY:High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement
DESCRIPTION:High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement\n\n\n\n\nSpeaker\n\n\nDr. Yuko Hara-Azumi\nRitsumeikan University\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 18\, 2011\nRefreshments at 2:30PM\, Colloquium begins at 3:00PM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThese years\, there has been a considerable interest in practical techniques to improve the yield of LSIs at little sacrifice of performance and area. Recently\, we presented a new concept device\, called Partially-Programmable Circuit (PPC)\, which consists of conventional gates\, LUTs\, and wires\, and enhances yield only by implicit logic redundancy (by partial reconfiguration of the LUTs) and redundant wires. In this talk\, a novel high-level synthesis (HLS) approach using PPC-realized resources is presented. Considering reconfiguration of the resources after fabrication\, our work aims at maximizing yield expectation.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nYuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. Currently she is a research fellow of the Japan Society for the Promotion of Science at Ritsumeikan University. Her research interests include system-level design methodology for embedded systems\, especially high-level and logic synthesis\, and task mapping technologies for many-core architectures.
URL:https://www.cecs.uci.edu/event/high-level-synthesis-using-partially-programmable-resources-for-yield-improvement/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110928T150000
DTEND;TZID=America/Los_Angeles:20110928T160000
DTSTAMP:20231011T183525Z
CREATED:20231011T183525Z
LAST-MODIFIED:20231011T183525Z
UID:14311-1317222000-1317225600@www.cecs.uci.edu
SUMMARY:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures
DESCRIPTION:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures\nby Amir Hossein Gholamipour \nCommittee:\nProf. Fadi Kurdahi (chair)\nProf. Ahmed Eltawil\nProf. Michael Dillencourt \nAn increasing number of digital systems\, from wireless devices to multi-media terminals\, are characterized by their multi-mode operation. This refers to the ability of a system to modify its characteristics or behavior based on user inputs or changes in the operational environment. FIR filters are frequently used in the operation of multi-mode systems due to their inherent stability and linear phase. In majority of such systems implementing a multi-mode FIR filter is the challenge in realizing the multi-mode behavior. FIR filters used for each mode of operation have different sets of parameters (coefficient sets). To implement multi-mode FIR filters\, General Purpose processors are incompetent in delivering the performance while Application Specific Integrated Circuits (ASICs) do not support the required flexibility. On Partially reconfigurable FPGA platforms we can optimize a filter structure based on the fixed parameters of filter and change the mode of operation by reconfiguring the fabric. However the reconfiguration overhead in this approach is not negligible. \nIn this work we introduce an approach which produces a spectrum of filter designs which trade-off area for reconfiguration overhead. In this thesis I prove that the problem of filter optimization can be solved in polynomial time. Furthermore as filter designs in the sequence of reconfiguration have similarities in their parameter sets\, we propose to jointly optimize their designs to further reduce the reconfiguration overhead. We consider the physical limitations of implementing multi-mode filters on FPGAs and propose a placement-aware approach to account for those limitations. Our placement-aware approach is an additional step called /Mapping/ that is introduced before floorplanning the design. In my work\, I show that mapping is an NP-hard problem and I propose ILP formulation and heuristics to solve it. As the result of my research\, I have developed a tool which gets the description of a sequence of filters as an input and generates the RTL design of the filters in VHDL code. It then gives hints on how to map the modules of the design to physical regions on the FPGA chip. This design approach has been tested on a rich set of applications including “preamble detection” unit of OFDMA receivers\, template matching and matched-filter based spectrum sensors. The results show the importance of this approach and the efficiency of the solutions proposed.
URL:https://www.cecs.uci.edu/event/comprehensive-multi-level-joint-optimization-for-multi-mode-fir-like-structures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110923T150000
DTEND;TZID=America/Los_Angeles:20110923T160000
DTSTAMP:20231011T182436Z
CREATED:20231011T182436Z
LAST-MODIFIED:20231011T182436Z
UID:14262-1316790000-1316793600@www.cecs.uci.edu
SUMMARY:Post-Silicon Patchable Hardware
DESCRIPTION:Post-Silicon Patchable Hardware\n\n\n\n\nSpeaker\n\n\nProf. Masahiro Fujita\nVLSI Design and Education Center (VDEC)\,\nThe University of Tokyo and CREST\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Rainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 3206\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nSeptember 23\, 2011\nSeminar begins at 2:00 PM\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWith the shorter time-to-market and the rising cost in SoC development\, the demand for post-silicon programmability has been increasing. Recently\, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However\, programmable accelerators suffers from 5?10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then\, we propose a patch compilation method from a given pair of an original design and a modified design. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nMasahiro Fujita received his Ph.D. from the University of Tokyo in 1985. He is a professor in VLSI Design and Education Center (VDEC) at the University of Tokyo. Prior to joining the University of Tokyo in 2000\, he was director of CAD for VLSI in Fujitsu Laboratories of America for 6 years. He has done innovative works in the areas of digital design verification\, synthesis\, and testing. He has authored and co-authored 10 books\, and has over 150 publications. He has been given several research awards from Japanese scientific societies. His current research interests include synthesis and verification in higher level design stages\, hardware/sfotware co-designs and also digital/analog co-designs.
URL:https://www.cecs.uci.edu/event/post-silicon-patchable-hardware/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110903T150000
DTEND;TZID=America/Los_Angeles:20110903T160000
DTSTAMP:20231011T183525Z
CREATED:20231011T183525Z
LAST-MODIFIED:20231011T183525Z
UID:14312-1315062000-1315065600@www.cecs.uci.edu
SUMMARY:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story
DESCRIPTION:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story\nby Houman Homayoun \nLocation: Bren Hall 4011 \nDate and Time: September 3\, 2011 2:30pm \nCommittee:\nProfessor Fadi Kurdahi (Chair)\nProfessor Alex Veidenbaum\,\nProfessor Jean-Luc Gaudiot\,\nProfessor Alex Nicolau. \nAbstract:\nLeakage currents in on-chip SRAMs: caches\, branch predictor\, register files and TLBs\, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines\, making remaining SRAM components\, in particular large drivers\, the primary source of leakage. We proposes an integrated circuit and architectural approach to reduce this source of leakage in all major SRAM-based units of the processor\, controlling them in a uniform way\, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Various low-power modes are defined\, from basic to ultra-low power\, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to be significant for all SRAM units. Resulting temperature reduction\, including the effect of positive feedback between temperature and leakage power\, is evaluated. A significant temperature reduction is achieved in each unit.
URL:https://www.cecs.uci.edu/event/beyond-memory-cells-for-leakage-and-temperature-control-in-sram-based-units-the-peripheral-circuits-story/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110712T150000
DTEND;TZID=America/Los_Angeles:20110712T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14263-1310482800-1310486400@www.cecs.uci.edu
SUMMARY:Hybrid Electrical Energy Storage Systems
DESCRIPTION:Hybrid Electrical Energy Storage Systems\n\n\n\n\nSpeaker\n\n\nProf. Naehyuck Chang\nSeoul National University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 2111\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 12 \, 2011\nLecture begins at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nElectrical energy is a high-quality form of energy in the sense that it can be easily and efficiently converted into other forms of energy\, and furthermore it can be used to control other forms of energy. Unfortunately\, electricity supply and demand are typically not balanced with each other. Storage of excessive energy and compensation of the energy shortage can significantly mitigate the over-investment in the generation facilities.  \nLike memory devices\, no single type of electrical energy storage (EES) element can fulfill all the desirable requirements. Despite active research on the new EES technologies\, it is not likely to have an ultimate high-efficiency\, high- power/energy capacity\, low-cost\, and long-cycle life EES element in the near future. We propose an hybrid electrical energy storage (HEES) system that consists of two or more heterogeneous EES elements\, thereby realizing the advantages of each EES element while hiding their weaknesses. \nCompared with the conventional homogeneous EES systems\, HEES systems provide high output power and energy density as well as high power conversion efficiency and low self-discharge at a low capital cost. Cycle efficiency of a HEES system\, which is defined as the ratio of energy which is delivered by the HEES system to the load device to energy which is supplied by the power source to the HEES system\, is one of the most important factors in determining the overall operational cost of the system. \nWe formulate the HEES management problems and project them into computer memory system design and management. We break the HEES management problems into charge allocation into different banks of EES elements\, charge replacement (i.e.\, discharge) from different banks of EES elements\, and charge migration from one bank to another bank of EES elements. Even a hybrid EES system cannot achieve high cycle efficiency if their storage banks have a fixed power and voltage rating because the optimal power capacity and voltage rating varies by the application and the state of charge (SoC) of the storage bank. Bank reconfiguration dynamically changes the array structure of an EES bank and maximizes the efficiency. \nIn this talk\, we start from introduction to the concept of HEES systems including EES element characteristics and power converter characteristics. The main body of this talk is charge allocation\, migration\, optimization\, and bank reconfiguration. The HEES research is recently brought up\, and thus there are a lot of important open problems. We will conclude this talk with remarks on the future work.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nNaehyuck Chang is a Full Professor in Dept. of Electrical Engineering and Computer Science\, Seoul National University\, Korea. He was a Visiting Associate Professor at Arizona State University in 2005\, and a Visiting Professor at University of Southern California in 2009-2010. He serves (and served) as Technical Program Committee of major EDA and embedded systems conferences and symposia including DAC\, ICCAD\, ISLPED\, DATE\, ASP-DAC\, GLS-VLSI\, ISQED\, PATMOS\, ESTIMedia\, ICCD\, and so on.  He served as the TPC Co-Chair of RTCSA in 2007\, ISLPED in 2009\, and ESTIMedia in 2009 and 2010. He was Vice GC of ISLPED 2010 and is General Co-Chair of ISLPED 2011. He is also General Chair of ESTIMedia in 2011. He will serve as a TPC Co-Chair of CODES+ISSS 2012. He is an Associate Editor of IEEE TCAD and ACM TODAES\, and editorial board members of JOLPE and JEC. He is a guest editor of ACM TODAES in 2011 and TECS for low-power design and embedded multi-media systems in 2010 and 2011. He also serves as the Chair of ACM SIGDA Low-Power Technical Committee\, ASP-DAC SIGDA Representative and ACM SIGDA Executive Committee (Technical Activity Chair). He is a Senior Member of ACM and IEEE.
URL:https://www.cecs.uci.edu/event/hybrid-electrical-energy-storage-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110603T150000
DTEND;TZID=America/Los_Angeles:20110603T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T192031Z
UID:14256-1307113200-1307116800@www.cecs.uci.edu
SUMMARY:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund
DESCRIPTION:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund\n\n\n\n\nSpeaker\n\n\nPeter Marwedel\nChair for Embedded Systems\nTU Dortmund/Informatik 12 + ICD\nDortmund\, Germany\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nRainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 3\, 2011\nRefreshments at 9:30 am\, Lecture begins at 10:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe group headed by Dr. Marwedel focuses on the design of efficient embedded systems. The talk will provide an overview of the research performed in this group:  \n\nEmbedded systems connected to the physical environment must meet timing constraints. Typically\, timing verification is performed after software generation\, possibly leading to many design iterations until timing constraints are finally met. In order to avoid such loops\, compilers can be made timing-aware. An approach for such integration will be presented together with some results.\nThe next part of the talk will be about addressing the memory wall problem. In particular\, the use of energy-efficient and timing-predictable scratchpad memories will be presented. Results on the worst-case execution time aware compilation for an automotive application using scratchpad memories will be included.\nThe final part will cover other research projects in the DAES group. These include two projects of the collaborative research project on resource constrained machine learning (SFB 876). In the first project\, resource-efficient image analysis for an advanced real-time virus detector is the subject for design space exploration. The second project aims at speeding up the execution of programs written in R (a language frequently used for statistical analyses) by about two orders of magnitude\, thereby enabling more comprehensive statistical analyses\, particularly in life sciences. Another project addresses the problem of guaranteeing timeliness for systems based on unreliable hardware.
URL:https://www.cecs.uci.edu/event/an-overview-over-research-activities-at-the-design-automation-for-embedded-systems-daes-group-at-tu-dortmund/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR