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DTSTART;TZID=America/Los_Angeles:20100803T150000
DTEND;TZID=America/Los_Angeles:20100803T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14268-1280847600-1280851200@www.cecs.uci.edu
SUMMARY:Towards Practical High-Level Synthesis from Large Behavioral Descriptions
DESCRIPTION:Towards Practical High-Level Synthesis from Large Behavioral Descriptions\n\n\n\n\nSpeaker\n\n\nDr. Yuko Hara-Azumi\nNagoya University\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nAugust 3\, 2010\nLecture begins at 3:00PM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDue to the continuously increasing size and complexity of LSIs\, the traditional Register-Transfer Level (RTL) design with Hardware Design Languages (HDLs) is approaching its limit on design productivity. High-level synthesis\, which automatically synthesizes an RTL circuit from a behavioral description\, is expected as a promising solution to improve design productivity. However\, the LSI design has not been completely shifted from the traditional RTL design with HDLs to high-level synthesis yet since the quality of automatically synthesized RTL circuits through high-level synthesis can be inferior to that of human-designed ones\, which is especially serious for large designs.  \nThe goal of my work is to develop practical technologies of “high-level synthesis from large behavioral descriptions”. In this talk\, first\, one of my thesis works\, which revealed some problems in current technologies of high-level synthesis\, is briefly presented. Then\, previous/ongoing works which tackle with the problems are presented.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nYuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. Currently she is a research fellow of the Japan Society for the Promotion and Science at Nagoya University. Also\, she serves as a visiting researcher at Ritsumeikan University and University of California\, Irvine. Her research interests include high-level synthesis and compiler techniques.
URL:https://www.cecs.uci.edu/event/towards-practical-high-level-synthesis-from-large-behavioral-descriptions/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100720T150000
DTEND;TZID=America/Los_Angeles:20100720T160000
DTSTAMP:20231011T193349Z
CREATED:20231011T185036Z
LAST-MODIFIED:20231011T193349Z
UID:14353-1279638000-1279641600@www.cecs.uci.edu
SUMMARY:Microsoft Ranking places CECS 6th in the World
DESCRIPTION:Microsoft Ranking Places CECS 6th in the World\nJuly 20\, 2010\n\nThe recently published Academic Research Ranking by Microsoft Corp (http://academic.research.microsoft.com/) ranks 20 Computer Science topics from Algorithms and Theory to the World Wide Web including 2.4 million publications. In the specific topic titled Hardware and Architecture\, which is particularly pertinent to the UCI Center for Embedded Computer Systems (CECS)\, it ranks over one-hundred thousand researchers world wide. CECS is very highly ranked by sharing 6th place with MIT\, UCLA\, Princeton and UIUC with 4 faculty in the top 100. First on the list is UCB with 10 in 100\, followed by Stanford with 9\, Michigan with 7 and UCSD and CMU with 5 faculty members in the top 100. \nThis faculty ranking affirms CECS reputation as one of the leading centers for embedded systems research and technology. \n“I heartily extend my congratulations to the Center for Embedded Computer Systems faculty\, students and staff.  It is an honor for the Samueli School faculty to be listed among the world’s top faculty in the field of computer hardware and architecture\,” said Rafael L. Bras\, distinguished professor and dean of The Henry Samueli School of Engineering. \nProf. Gajski\, the CECS Director\, said that he is very happy that the research of CECS faculty has been recognized and appreciated around the world. He is also hoping that such recognition will help improve the ranking of our schools\, the School of ICS and the School of Engineering\, as well as improving the standing of UCI in the ranking of world universities (http://www.arwu.org/).
URL:https://www.cecs.uci.edu/event/microsoft-ranking-places-cecs-6th-in-the-world/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100621T150000
DTEND;TZID=America/Los_Angeles:20100621T160000
DTSTAMP:20231011T193551Z
CREATED:20231011T185037Z
LAST-MODIFIED:20231011T193551Z
UID:14357-1277132400-1277136000@www.cecs.uci.edu
SUMMARY:EcoExec: An Interactive Execution Framework for Ultra Compact Wireless Sensor Nodes
DESCRIPTION:Release Date: June 21\, 2010Download pdf: EcoExec: An Interactive Execution Framework for Ultra Compact Wireless Sensor Nodes  \nEcoExec is a host-assisted interactive execution environment for wireless sensing systems. Users can interact with sensor nodes by viewing attributes and invoking functions via a command-line interface. Functions that are not resident in the node’s firmware are automatically compiled on the host\, packaged up and downloaded to the node\, linked\, and executed\, all seamlessly and transparently to the user. By packaging these features in a dynamically object-oriented programming environment such as Python\, EcoExec enables programmers to experiment with features of the wireless sensor nodes and to rapidly develop application software. Most importantly\, EcoExec empowers resource-constrained wireless sensor platforms with rich functionalities that would otherwise be prohibitive\, thanks to its host-assisted execution feature with code swapping over the network. Experimental results on actual wireless sensor platforms show EcoExec to perform effectively with negligible observed overhead to the user.
URL:https://www.cecs.uci.edu/event/ecoexec-an-interactive-execution-framework-for-ultra-compact-wireless-sensor-nodes/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100617T150000
DTEND;TZID=America/Los_Angeles:20100617T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14269-1276786800-1276790400@www.cecs.uci.edu
SUMMARY:Location and Time in Sensor Networks
DESCRIPTION:Automatic Design Space Exploration for Chip Multi-Processors\n\n\n\n\nSpeaker\n\n\nDr. Cristina Silvano\,\nPolitecnico di Milano\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nAlex Veidenbaum\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 17 \, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nGiven the increasing complexity of Chip Multi-Processors\, a wide range of architecture parameters (number of processors\, processor issue width\, L1 & L2 cache size\, etc.) must be tuned to find the best trade-off in terms of multiple metrics (energy\, delay\, bandwidth\, area\, etc.). Multi-Objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. Automatic Design Space Exploration is necessary to support systematically the exploration and the quantitative comparison in terms of multiple objectives. This talk addresses these problems by presenting MULTICUBE Explorer\, an open-source tool to support an automatic and fast optimization of configurable system-on-chip architectures towards a set of objective functions such as energy and delay. MULTICUBE Explorer provides a set of innovative sampling and optimization techniques to help finding the multi-objective Pareto points. Design of Experiments techniques are used to identify the experimentation plan where the set of tunable design parameters can vary. Response Surface Modeling techniques are used to obtain a response surface of the system behavior based on the set of data generated by DoE. MULTICUBE Explorer can also provide some support for run-time management of system resources.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nShe is an Associate Professor in Computer Engineering at Politecnico di Milano (Italy). Her primary research interests are in the area of Computer Architectures and Electronic Design Automation\, with particular emphasis on design space exploration techniques and low- power design techniques for multi-processor systems-on-chip. She is co-author of more than seventy scientific papers on international journals and conferences\, collecting one best paper award. She was co-author of the book: Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems\, published by Kluwer Academic Publisher (2003). She also holds some international patents. She participated to a number of national and international research projects. She is currently the European Coordinator of the on-going project FP7-MULTICUBE-216693 “Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications” (Jan. 2008 – June 2010). >From 2010\, she is also the Project Coordinator of the project FP7-2PARMA-248716 on “Parallel paradigms and run-time management techniques for many-core architectures.”
URL:https://www.cecs.uci.edu/event/location-and-time-in-sensor-networks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100615T150000
DTEND;TZID=America/Los_Angeles:20100615T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14270-1276614000-1276617600@www.cecs.uci.edu
SUMMARY:Secure VLSI Test Methods
DESCRIPTION:Secure VLSI Test Methods\n\n\n\n\nSpeaker\n\n\nDr. Ramesh Karri\nPolytechnic University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nIan Harris\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 15 \, 2010\nRefreshments at 10:30 am; Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDesign for Test (DFT) techniques improve access to the internal state of hardware either by improving control of internal nodes from the primary inputs or by improving observation of values on internal nodes at the primary outputs or both. On the other hand\, from a security perspective\, hardware should minimize controllability and observability of the internal state to a minimum. In this talk we will discuss our research on secure DFT architectures that reconcile Testability and Security.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nRamesh Karri is an Associate Professor in the Department of Electrical and Computer Engineering. Prof. Karri’s research interests are in the areas of secure hardware design\, computer-aided secure hardware design\, high-speed architectures for network protocols and encryption\, and computer-aided design of fault-tolerant nanoscale systems. \nProf. Karri is the recipient of an NSF CAREER award\, an Alexander Humboldt Fellowship and several grants including from the National Science Foundation\, the Air Force Research Labs and Army. Most recently\, Prof. Karri has been a co-PI with Program Director Nasir Memon on the just-awarded $2.124 million NSF grant from the National Science Foundation research and teaching of security and privacy issues on the Internet and other critical information infrastructure and is a founding member of the Center for Research in Interdisciplinary Studies in Security and Privacy at NYU. \nProfessor Karri received his MS in Computer Engineering at the University of California (1992)\, and his PhD in Computer Science also at the University of California (1993).
URL:https://www.cecs.uci.edu/event/secure-vlsi-test-methods/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100611T150000
DTEND;TZID=America/Los_Angeles:20100611T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14271-1276268400-1276272000@www.cecs.uci.edu
SUMMARY:The Inevitable Use of High Level Synthesis in Complex SoC Designs
DESCRIPTION:The Inevitable Use of High Level Synthesis in Complex SoC Designs\n\n\n\n\nSpeaker\n\n\nDr. Benjamin Schaefer\,\nNEC Research Lab\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 413\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 11 \, 2010\nLecture begins at 11:00 am (Lecture Cancelled)\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nESL is becoming main stream when modeling complete SoCs in order to evaluate different architectural trade-offs and get some early performance estimates. These models are mainly described in SystemC. The central question that remains is if these models can ultimately be synthesized in order to further reduce the development cycle or if these models need to be manually described and integrated at the RT-level. This talk addresses how complete SoCs can be fully designed in C.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nBenjamin received his Ph.D from the University of Birmingham\, UK in 2003 \, where he investigated the acceleration of numerical intensive algorithms on reconfigurable computing platforms. He then moved to UCLA as a postdoctoral researcher working in the area of High Level synthesis and then moved to Seoul National University\, Korea where he worked on thermal estimation and reduction issues in VLSI circuits. Since 2007 he is with NEC’s Central Research Laboratory in Japan\, working on System and High Level Synthesis.
URL:https://www.cecs.uci.edu/event/the-inevitable-use-of-high-level-synthesis-in-complex-soc-designs/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100527T150000
DTEND;TZID=America/Los_Angeles:20100527T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14272-1274972400-1274976000@www.cecs.uci.edu
SUMMARY:Location and Time in Sensor Networks
DESCRIPTION:Location and Time In Sensor Networks\n\n\n\n\nSpeaker\n\n\nDr. Ryo Sugihara\,\nUniversity of California\, San Diego\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 30\, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk I will present two of my projects related to location and time in sensor networks. First is location-based job scheduling. Specifically I will talk about the use of controlled mobility for data collection in sensor networks. As controllable mobile nodes (called “data mules”) travel across the sensor field to bring the data back to the base station\, how the data mules choose their paths\, change speed\, and schedule communication are important problems for minimizing the data collection latency. We formulated the problem as a scheduling problem called data mule scheduling (DMS) problem. This is an interesting extension to traditional job scheduling problem: each job has release and deadline on the location axis instead of the time axis. We have analyzed the complexity for several different mobility models and designed optimal and approximate algorithms. I will also talk about the similarity with dynamic voltage scaling problem.  \nIn the second part\, I will introduce our recent work on clock synchronization protocol in sensor networks. Although clock synchronization has been studied for a long time in sensor networks as well as in distributed systems\, recent synchronization protocols for sensor networks have been mostly focused on achieving good average accuracy. While these protocols achieve microsecond-order accuracy\, many of them do not have any guarantees on the worst case. However\, as sensor networks become used more widely or incorporated into larger systems in the form of CPS (cyber-physical system)\, the notion of guaranteed performance increases importance much more than ever. To deal with this\, our work is focused on providing guaranteed accuracy in clock synchronization. Based on observation of the characteristics of crystal oscillators on sensor nodes\, our synchronization protocol achieves much tighter accuracy guarantee than the classical methods (sometimes called “interval-based clock synchronization algorithms”) can provide.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nRyo Sugihara received the BE and ME degrees in mechanical engineering from the University of Tokyo\, Japan\, in 1997 and 1999\, respectively. He received the PhD degree in computer science in 2009 from the University of California\, San Diego\, where he is currently working as a postdoctoral researcher. Previously\, he worked at the IBM Tokyo Research Laboratory\, where he was engaged in research and development on video digital watermarking and large-scale video streaming. His current research interests include sensor networks and mobile ad hoc networks. He was a recipient of the Best Paper Award of the Systems track at IEEE DCOSS 2008.
URL:https://www.cecs.uci.edu/event/location-and-time-in-sensor-networks-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100519T150000
DTEND;TZID=America/Los_Angeles:20100519T160000
DTSTAMP:20231011T183702Z
CREATED:20231011T183702Z
LAST-MODIFIED:20231011T183702Z
UID:14316-1274281200-1274284800@www.cecs.uci.edu
SUMMARY:Code Layout Optimization for Remote Progressive Code Update for Networked Embedded Systems
DESCRIPTION:Code Layout Optimization for Remote Progressive Code Update for Networked Embedded Systems\nby Jinsik Kim \nLocation: Engineering Hall 2111 \nDate and Time: November 18\, 2009 2:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Tony Givargis\nProf. Rainer Doemer \nAbstract:\nMany embedded systems need to have their firmware updated several times over the lifetime of the system after deployment. While those based on binary differencing suffer from unpredictable code shift\, overwriting the entire firmware image may be too costly for those connected by slow\, unreliable\, or expensive data links. In other words\, firmware update over a network connection is an essential but expensive feature for many embedded systems due to the relatively high power consumption and limited bandwidth. \nTo solve these problems\, we propose a new technique by exploiting high-level knowledge about the source program structure in laying out the binary image. Specifically\, we show that by laying out code in order of the cyclomatic complexity of the routines\, the code will evolve with minimal Hamming distance between successive revisions as the code evolves. This code layout technique has the benefits of minimizing bandwidth and power requirements for remote firmware update while also minimizing the wearing of the non-volatile program memory.For another target physical memory\, our work proposes a page-level\, link-time technique that minimizes not only the size of patching scripts but also perturbation to the firmware memory\, over the entire sequence of updates in the system’s lifetime. Experimental results show our technique to reduce the energy consumption of firmware update by 30–42% over the state-of-the-art.
URL:https://www.cecs.uci.edu/event/code-layout-optimization-for-remote-progressive-code-update-for-networked-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100430T150000
DTEND;TZID=America/Los_Angeles:20100430T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14273-1272639600-1272643200@www.cecs.uci.edu
SUMMARY:Customizable Domain-Specific Computing
DESCRIPTION:Customizable Domain-Specific Computing\n\n\n\n\nSpeaker\n\n\nDr. Jason Cong\,\nCenter for Domain-Specific Computing\,\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 6011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 30\, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n\n \nIn order to meet ever-increasing computing needs and overcome power density limitations\, the computing industry has halted simple processor frequency scaling and entered the era of parallelization\, with tens to hundreds of computing cores integrated in a single processor\, and hundreds to thousands of computing servers connected in a warehouse-scale data center. However\, such highly parallel\, general-purpose computing systems still face serious challenges in terms of performance\, power\, heat dissipation\, space\, and cost. We believe that we need to look beyond parallelization and focus on domain-specific customization as the next opportunity to bring orders-of-magnitude power-performance efficiency improvement to important classes of applications. This challenge requires a great deal of innovation in architecture\, compilation\, and runtime system design\, and offers many exciting and challenging research opportunities. \nI shall talk about the ongoing work at the newly established Center for Domain-Specific Computing supported by the NSF Expeditions in Computing award. Our proposed domain-specific customizable computing platform includes: \n1) a wide range of customizable computing elements\, from heterogeneous fixed cores to coarse-grain customizable cores\, and to fine-grain field-programmable circuit fabrics; \n2) customizable high-performance radio frequency interconnects; \n3) highly automated compilation tools and runtime management software systems for application development; \nand \n4) a general\, reusable methodology for customizable computing applicable across different domains. \nBy combining these critical capabilities\, we aim to provide a supercomputer-in-a-box that is customized to a particular application domain with much higher performance/power efficiency. We choose application domains in healthcare to demonstrate our approach.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nShort biography available at Dr. Jason Cong’s Web Site.
URL:https://www.cecs.uci.edu/event/customizable-domain-specific-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100422T150000
DTEND;TZID=America/Los_Angeles:20100422T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14274-1271948400-1271952000@www.cecs.uci.edu
SUMMARY:Wireless Health Systems
DESCRIPTION:Wireless Health Systems\n\n\n\n\nSpeaker\n\n\nDr. Ani Nehapetian\,\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 22\, 2010\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOne of the most urgent and daunting tasks of our time is providing quality health care in the face of increasing incidence of disease\, aging populations\, and soaring costs. The proliferation of lightweight and heterogeneous embedded systems holds the promise of revolutionizing the accessibility\, quality\, financing\, and delivery of healthcare in much the same way that low-cost cellular phone technology dramatically changed telecommunications worldwide. However\, significant research challenges must be addressed before this wireless health model can reach its full potential.  \nThe talk will include an overview of various devices and systems under development at the UCLA Wireless Health Institute. Additionally\, it will consider important research issues\, including security and and data management.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Ani Nahapetian is currently a researcher with the UCLA Wireless Health Institute and a visiting assistant professor with the UCLA Computer Science department. She received her Ph.D and M.S. in Computer Science\, and B.S. in Computer Science and Engineering\, all from UCLA. Her research interests include embedded systems with health applications\, algorithm design for reconfigurable and low-power embedded systems\, and hardware security.
URL:https://www.cecs.uci.edu/event/wireless-health-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100110T150000
DTEND;TZID=America/Los_Angeles:20100110T160000
DTSTAMP:20231011T193349Z
CREATED:20231011T185036Z
LAST-MODIFIED:20231011T193349Z
UID:14354-1263135600-1263139200@www.cecs.uci.edu
SUMMARY:EDAA Lifetime Achievement Award 2010 goes to Daniel D. Gajski
DESCRIPTION:EDAA Lifetime Achievement Award 2010 goes to Daniel D. Gajski\n\nJanuary 10\, 2010\n\nAdapted from EDAA Press Release:\nThe EDAA Lifetime Achievement Award 2010 goes to Daniel D. Gajski. \nThe Lifetime Achievement Award is given to individuals who made outstanding contributions to the state of the art in electronic design\, automation and testing of electronic systems in their life. In order to be eligible\, candidates must have made innovative contributions which had an impact on the way electronic systems are being designed. \nUCI Vice Chancellor for Research Susan Bryant congratulates Professor Gajski for this outstanding achievement: “His establishment and leadership of the Center for Embedded Computer Systems as a campus Organized Research Unit reflects the world-class research being undertaken at UCI.  We look forward to the continued success and world-wide recognition of Dr. Gajski and the Center for Embedded Computer Systems.“ \nPast recipients have been Kurt Antreich (2003)\, Hugo De Man (2004)\, Jochen Jess (2005)\, Robert Brayton (2006)\, Tom W. Williams (2007)\, Ernest S. Kuh (2008) and Jan M. Rabaey (2009). The Award will be presented at the plenary session of the 2010 DATE Conference\, to be held 8-12 March in Dresden\, Germany. \nDaniel D. Gajski received the Dipl. Ing. and M.S. degrees in Electrical Engineering from the University of Zagreb\, Croatia\, and the Ph.D. degree in Computer and Information Sciences from the University of Pennsylvania\, Philadelphia\, in 1974. After 10 years of industrial experience in digital circuits\, supercomputing\, and VLSI design\, he spent 10 years in academia with the Department of Computer Science at the University of Illinois\, Urbana-Champaign. Presently\, he is a Full Professor in the Department of Electrical Engineering and Computer Science at the University of California\, Irvine. He holds the Henry Samueli Endowed Chair in Computer System Design and is the Director of the Center for Embedded Computer Systems at UCI. \nDaniel Gajski has made many fundamental contributions to areas spanning from electronic design automation to embedded systems. He is considered among the founding fathers of the push in electronic design methods towards higher levels of abstractions and their relationship to system architectures and has been a leader in establishing the fields of Silicon Compilation\, High-Level Synthesis\, and System-Level Design. \nDaniel Gajski has published over 250 journal and conference papers\, has edited\, authored and co-authored a total of seven books and numerous book chapters\, and has received several best-paper awards and nominations. He has been named an IEEE Fellow for contributions to VLSI design\, system-level design methodologies and CAD tools and also has been presented with an honorary doctorate from the University of Oldenburg\, Germany\, in 2006 in recognition of his contributions in the areas of embedded systems and design science. \nMore information and electronic version of this Press Release available at: http://www.edaa.com/
URL:https://www.cecs.uci.edu/event/edaa-lifetime-achievement-award-2010-goes-to-daniel-d-gajski-2/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091214T150000
DTEND;TZID=America/Los_Angeles:20091214T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14246-1260802800-1260806400@www.cecs.uci.edu
SUMMARY:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases
DESCRIPTION:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases\n\n\n\n\nSpeaker\n\n\nDr. Masato Motomura\,\nSystem IP Core Research Laboratories\, NEC Corporation\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 14\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nStream Transpose (STP) Engine is a programmable HW core to accelerate stream processing in modern system LSIs. It is composed of an array of numerous numbers of processing and memory elements as well as an intelligent data streaming HW mechanism. Key differentiation from other many-core type parallel architectures lies in its programming model: i.e.\, a design tool based on high-level HW synthesis technology compiles a C source code into a set of pseudo HW configurations which are spatially and temporally mapped onto the array. The STP engine is productized in 90nm-generation system LSIs\, and is targeted for wider-range use in forthcoming generations beyond 40nm.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Motomura received EE doctorial degree from Kyoto University in 1996. He has been engaged in research of various LSI architectures\, such as functional memories\, parallel processors\, and reconfigurable arrays in NEC research laboratories since 1987. From 2002 to 2009\, he led technology and business development of STP Engine in NEC Electronics. He was also the winner of 1992 IEEE JSSC Best Paper Award.
URL:https://www.cecs.uci.edu/event/stp-engine-a-c-based-programmable-hw-core-featuring-massively-parallel-and-reconfigurable-pe-array-its-architecture-tool-and-real-system-usecases/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091118T150000
DTEND;TZID=America/Los_Angeles:20091118T160000
DTSTAMP:20231011T183702Z
CREATED:20231011T183702Z
LAST-MODIFIED:20231011T183702Z
UID:14317-1258556400-1258560000@www.cecs.uci.edu
SUMMARY:Low-Complexity and High-Throughput Protocols for Wireless Sensor Networks
DESCRIPTION:Low-Complexity and High-Throughput Protocols for Wireless Sensor Networks\nby Chongjing Chen \nLocation: Engineering Hall 2210 \nDate and Time: November 18\, 2009 2:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Stephen Jenks\nProf. Rainer Doemer \nAbstract:\nWireless technologies have enabled mobility and convenience by eliminating cumbersome wires. Wireless sensor nodes must be made small and low power without sacri?cing performance. In addition to task scheduling\, the densely distributed wireless sensor nodes must run communication protocols to achieve better utilization and reliable communication. While many researchers work on wireless sensor networks that are densely distributed\, they assume low duty cycling and trivial data rate. Unfortunately\, this is a great mismatch with many real-world applications that require the high data rate. Furthermore\, most wireless communication protocols are too complicated to be used on compact wireless sensor nodes with limited RAM and ROM. \nTo address these issues\, we propose a lightweight multiple access control protocol to enable relatively high data rate and densely distributed deployment. It can achieve reliable communication on resource-constrained wireless sensor nodes and minimizes the protocol complexity to reduce the memory footprint. The protocol can also work under high utilization of air bandwidth without collision. While civil engineers are concerned about the sampling rate at 100 Hz for structure monitoring\, our system with this protocol can scale up to 50 wireless sensor nodes and stream real-time data in the same frequency channel at 100 Hz sampling rate. We also propose a compact\, multi-channel protocol with high scalability and small memory footprint. This multiple access control protocol enables wireless sensor nodes to transmit sensing data over multiple frequency channels to achieve a higher throughput than a system with only a single frequency channel. We integrate our protocol with a giant tiled display system\, HIPerWall\, to show the real-time sensing data at a high resolution without downsampling. Last\, we perform a thorough evaluation to study the channel characteristics of a wearable wireless sensor node. We vary several di?erent parameters\, the RF transmission power\, distance\, height\, and angle to observe the packet loss rates. These experimental results can be used for constructing a more reliable wireless communication for wireless sensor networks.
URL:https://www.cecs.uci.edu/event/low-complexity-and-high-throughput-protocols-for-wireless-sensor-networks/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091118T150000
DTEND;TZID=America/Los_Angeles:20091118T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14275-1258556400-1258560000@www.cecs.uci.edu
SUMMARY:Concurrency and Communication: Lessons from the SHIM Project
DESCRIPTION:Concurrency and Communication: Lessons from the SHIM Project\n\n\n\n\nSpeaker\n\n\nDr. Stephen A. Edwards\,\nColumbia University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Tony Givargis\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 18\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDescribing parallel hardware and software is difficult\, especially in an embedded setting. Five years ago\, we started the SHIM project to address this challenge by developing a programming language for hardware/software systems. The resulting language describes asynchronously running processes that has the useful property of scheduling-independence: the I/O of a SHIM program is not affected by any scheduling choices. I will present a history of the SHIM project with a focus on the key things we have learned along the way.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nStephen A. Edwards received the B.S. degree in Electrical Engineering from the California Institute of Technology in 1992\, and the M.S. and Ph.D degrees\, also in Electrical Engineering\, from the University of California\, Berkeley in 1994 and 1997 respectively. He is currently an associate professor in the Computer Science Department of Columbia University in New York\, which he joined in 2001 after a three-year stint with Synopsys\, Inc.\, in Mountain View\, California. His research interests include embedded system design\, domain-specific languages\, and compilers.
URL:https://www.cecs.uci.edu/event/concurrency-and-communication-lessons-from-the-shim-project/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091117T150000
DTEND;TZID=America/Los_Angeles:20091117T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14276-1258470000-1258473600@www.cecs.uci.edu
SUMMARY:Advanced SoC Architectures for Multiple DRAMs (Enabled by 3D Die Stacking)
DESCRIPTION:Advanced SoC Architectures for Multiple DRAMs\n(Enabled by 3D Die Stacking)\n\n\n\n\nSpeaker\n\n\nDr. Sungjoo Yoo\nPOSTECH\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 17 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe performance of data-intensive applications is mostly determined by the bandwidth and latency of off-chip DRAM. In order to improve the bandwidth and latency characteristics\, multiple memory-based solutions (enabled by 3D stacking of memory dies on top of LSI dies) are being actively investigated. With multiple DRAMs\, we come to face new architectural problems\, especially\, in memory controllers and on-chip network. In this talk\, we will discuss the architectural problems caused by multiple memories and present our solutions (request parallelizer\, in-network reorder buffer\, etc.) to address the problems. We will summarize this talk with some speculations on future SoC architectures with multiple memories.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Sungjoo Yoo received B.S.\, M.S.\, and Ph.D. at Seoul National University\, Korea\, in 1992\, 1995\, and 2000\, respectively. He worked at TIMA laboratory\, Grenoble\, France from 2000 to 2004 and worked as principal engineer at System LSI Division\, Samsung Electronics from 2004 to 2008. At Samsung\, he led a team which developed AMBA3-based on-chip bus architectures for mobile SoCs\, and low power design solutions such as dynamic voltage and frequency scaling (DVFS) algorithms and performed hardware/software co-optimization of solid state disk products. He joined POSTECH (Pohang university of science and technology) in August 2008. His current research interests include memory hierarchy and network-on-chip for many-core SoC\, low power design based on runtime-distribution and temperature-aware DVFS\, and power efficiency/performance/reliability improvement of solid state disk.
URL:https://www.cecs.uci.edu/event/advanced-soc-architectures-for-multiple-drams-enabled-by-3d-die-stacking/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091116T150000
DTEND;TZID=America/Los_Angeles:20091116T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14277-1258383600-1258387200@www.cecs.uci.edu
SUMMARY:Energy Efficient Computing
DESCRIPTION:Energy Efficient Computing\n\n\n\n\nSpeaker\n\n\nProf. Tajana Simunic Rosing\,\nDepartment of CSE\,\nUC San Diego\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Daniel Gajski\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 16 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk\, we will present the algorithms we have developed at UCSD for lowering the energy consumption in computing systems. We derived optimal power management strategies for stationary workloads that have been implemented both in HW and SW. Run-time adaptation can be done via an online learning algorithm that selects among a set of policies. We generalized the algorithm to include thermal management since we found that minimizing the power consumption does not necessarily reduce the overall energy costs. To reduce the performance costs typically associated with state of the art thermal management techniques\, we also developed a new set of proactive management policies. The experimental results using real datacenter workloads on an actual multicore system show that our proactive technique is able to dramatically reduce the adverse effects of temperature by over 60%. Most recently we have shown that symbiotic scheduling of workloads in virtualized environments can lead to average 15% energy savings with 20% performance benefit in high utilization scenarios.We will also present some of the recent work that address the energy savings in battery powered systems\, as demonstrated in a new kind of “citizen infrastructure”\, an end-to-end health and environmental information system with near real-time data streams and feedback loops from the system to the sensing\, processing\, and actuation infrastructure. We have developed adaptive algorithms to tradeoff accuracy of computation versus the available energy for such systems\, while taking into account the energy harvesting capabilities.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nTajana Simunic Rosing is currently an Assistant Professor in Computer Science Department at UCSD\, a director of System Energy Efficiency Lab at UCSD and a head of the Energy efficient datacenter thrust as a part of the MuSyC center. Her research interests are energy efficient computing\, embedded and wireless systems. She finished her PhD at Stanford University. Prior to pursuing the PhD\, she worked as a Senior Design Engineer at Altera Corporation. She has served at a number of Technical Paper Committees\, and is currently an Associate Editor of IEEE Transactions on Mobile Computing.
URL:https://www.cecs.uci.edu/event/energy-efficient-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091112T150000
DTEND;TZID=America/Los_Angeles:20091112T160000
DTSTAMP:20231011T185436Z
CREATED:20231011T185436Z
LAST-MODIFIED:20231011T185436Z
UID:14365-1258038000-1258041600@www.cecs.uci.edu
SUMMARY:NEC’s Manycore Platforms for Low-Power Embedded System
DESCRIPTION:Naoki NishGeneral Manager\, NEC Central Research Labs\nTokyo\, Japan\nDonald Bren Hall 3011\nNovember 12\, 2009\nAbstract
URL:https://www.cecs.uci.edu/event/necs-manycore-platforms-for-low-power-embedded-system-2/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091112T150000
DTEND;TZID=America/Los_Angeles:20091112T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T180836Z
LAST-MODIFIED:20231011T192457Z
UID:14247-1258038000-1258041600@www.cecs.uci.edu
SUMMARY:NEC's Manycore Platforms for Low-Power Embedded System
DESCRIPTION:NEC’s Manycore Platforms for Low-Power Embedded System\n\n\n\n\nSpeaker\n\n\nNaoki Nishi\nGM\, NEC Central Research Labs\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 12\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAfter short introduction of NEC’s R&D vision related to future ICT system handling real world in real time\, two examples of NEC’s manycore research activities will be presented. First example is an in-vehicle vision processor IMAPCAR-2 which supports SIMD-MIMD morphing\, and the second is a fine grain manycore architecture called STP (Stream TransPoser) engine which is a kind of dynamically reconfigurable hardware with C level language SDK support.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nNaoki Nishi is a general manager at central research labs.\, NEC. He jointed NEC in 1984\, where he worked in research on micro-architectures and LSI development of the NEC SX vector supercomputer\, After the development of CMOS vector supercomputer SX-4 in 1996\, he has been conducting research on high-performance\, low-power multi-/many-cores. Naoki Nishi received his B.E. and M.E. degrees in system engineering from Hiroshima University\, Japan.
URL:https://www.cecs.uci.edu/event/necs-manycore-platforms-for-low-power-embedded-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091110T150000
DTEND;TZID=America/Los_Angeles:20091110T160000
DTSTAMP:20231011T185436Z
CREATED:20231011T183050Z
LAST-MODIFIED:20231011T185436Z
UID:14278-1257865200-1257868800@www.cecs.uci.edu
SUMMARY:Why Circuits Fail
DESCRIPTION:Dr. Sani R. NassifIBM Research Labs\, Austin\, TX\nDonald Bren Hall 3011\nNovember 10\, 2009\nAbstract
URL:https://www.cecs.uci.edu/event/why-circuits-fail/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091022T150000
DTEND;TZID=America/Los_Angeles:20091022T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192031Z
UID:14248-1256223600-1256227200@www.cecs.uci.edu
SUMMARY:A Virtualization-Based Software Architecture for Real-Time Embedded Systems
DESCRIPTION:A Virtualization-Based Software Architecture for Real-Time Embedded Systems\n\n\n\n\nSpeaker\n\n\nDr. Sung-Soo Lim\nAssistant Professor\,\nSchool of Computer Science\,\nKookmin University\,\nSeoul\, Korea\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 22 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThis talk introduces an on-going work in Embedded Systems Laboratory\, Kookmin University to build next generation software architecture for mobile phones cooperating with Samsung Electronics. Future mobile phones need to accommodate both legacy applications and hard real-time communication protocols regardless of the underlying hardware organization. Such support for flexibility and reconfigurability should be accompanied with guarantee of reliability and security.  \nWe design and implement a light-weight hypervisor based on L4 microkernel for real-time embedded systems accommodating both general-purpose and hard real-time operating systems. The virtualization-based software architecture based on our hypervisor could have the reliability with zero-down feature and safety during dynamic software upgrade. We built a prototype smartphone platform running both Linux and uCOS-II on a single ARM11 core using the proposed software architecture. The structure and core techniques used in our software architecture will be introduced in the talk.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nSung-Soo Lim received BS\, MS\, and PhD degrees in Computer Engineering from Seoul National University in 1993\, 1995\, and 2002\, respectively. From 2000 to 2001\, he was a visiting researcher in University of Illinois at Urbana-Champaign. From 2001 to 2004\, he was the CTO of PalmPalm Technology\, Inc. in Korea (a smartphone development company). He is currently an assistant professor in School of Computer Science\, Kookmin University. His research area includes real-time operating systems\, real-time performance analysis\, low-power technology\, and mobile phone architecture.
URL:https://www.cecs.uci.edu/event/a-virtualization-based-software-architecture-for-real-time-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091019T150000
DTEND;TZID=America/Los_Angeles:20091019T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14249-1255964400-1255968000@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 19 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091009T150000
DTEND;TZID=America/Los_Angeles:20091009T160000
DTSTAMP:20231011T192654Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192654Z
UID:14250-1255100400-1255104000@www.cecs.uci.edu
SUMMARY:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA
DESCRIPTION:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA\n\n\n\n\nSpeaker\n\n\nProf. Lei He\nElectrical Engineering Department\,\nUCLA\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Eli Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 9\, 2009\nRefreshments at 10:30am; Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAs devices become smaller\, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired\, especially if no extra area\, power and delay and little change of the existing design flow are introduced. Using FPGA and internet router as a testbed\, this talk first presents fault tolerance techniques applying (1) logic don’t care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both increase MTTF by 2X with little or no overhead. Particularly\, IPR does not change circuit placement and routing\, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. Finally\, I will briefly discuss my ongoing research on cyber-physical systems involving renewal energy storage and environment/water monitoring.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Lei He is an associate professor at electrical engineering department\, UCLA\, and was a faculty member at University of Wisconsin\, Madison between 1999 and 2001. He also held visiting or consulting positions with Intel\, Hewlett-Package\, Cadence and Synopsys\, was a technical advisory board member for Rio Design Automation\, and Apache Design Solutions\, and is a guest professor at Fudan University (China) and China National Laboratory for Optoelectronics.  \nHis research interests include electronic design automation\, VLSI circuits and systems\, and cyber-physical systems. He has published one book and over 200 technical papers and has been a technical program committee member for a number of conferences including Design Automation Conference\, International Conference on Computer-Aided Design\, International Symposium on Low Power Electronics and Design\, International Symposium on Field Programmable Gate Array\, and International Symposium on Physical Design. Dr. He obtained Ph.D. degree in computer science from UCLA in 1999. He was granted National Science Foundation CAREER award in 2000\, UCLA Chancellor’s faculty career development award in 2003\, IBM Faculty Award in 2003\, Northrop Grumman Excellence in Teaching award in 2005\, best paper award at the 2006 International Symposium on Physical Design\, and multiple best paper nominations at Design Automation Conference and International Conference on Computer-Aided Design.
URL:https://www.cecs.uci.edu/event/power-efficient-and-fault-tolerant-circuits-and-systems-using-commodity-fpga/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090901T150000
DTEND;TZID=America/Los_Angeles:20090901T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14318-1251817200-1251820800@www.cecs.uci.edu
SUMMARY:Algorithmic Code Optimization Using Conditional Expression Evaluation
DESCRIPTION:Algorithmic Code Optimization Using Conditional Expression Evaluation\nby Mohammad Ali Ghodrat \nLocation: Bren Hall 3011 \nDate and Time: September 1\, 2009 10:30am \nCommittee:\nProfessor Tony Givargis (Chair)\nProfessor Alex Nicolau\nProfessor Nikil Dutt \nAbstract:\nSoftware is becoming a larger fraction of engineering effort. Aggressive compiler optimization\, in particular those that address loops\, can significantly improve the performance of the software\, thus justifying the additional compilation time requirements. This is in particular true in the embedded system domain where software has become a key element of the design process and performance/energy is of a critical concern. A particular area in software optimization\, where little work has been established\, is control flow performance and energy optimization\, which is the main focus of this thesis. \nArithmetic expressions are the fundamental building blocks of hardware and software systems. In this thesis we first propose a method for solving the arithmetic expression equivalence problem using partial evaluation. In our method\, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Using this technique\, we present three novel control flow optimization techniques to improve performance and energy in software. \nIn the first technique\, we present a short-circuit code transformation method to optimize conditional blocks in high-level programs. Specifically\, the transformation takes advantage of the fact that the Boolean value of the conditional expression\, determining the true/false paths\, can be statically analyzed to determine cases when one or the other of the true/false paths are guaranteed to execute. In such cases\, code is generated to bypass the evaluation of the conditional expression. In instances when the bypass code is faster to evaluate than the conditional expression\, a net performance gain is obtained. \nIn the second technique\, we present a loop transformation method to optimize loops containing nested conditional blocks. Results from conditional expression evaluation combined with loop dependency information are used to partition the iteration space of the nested loop. As a result\, the loop nest is decomposed such as to eliminate the conditional test\, thus substantially reducing the execution time. Our technique completely eliminates the conditional from the loops (unlike previous techniques) thus further facilitating the application of traditional optimizations and improving the overall speedup. \nIn the third technique\, we present a method to lower the software energy consumption using the technique mentioned above for loop transformation. In essence\, each of the smaller loops can be executed at a lower voltage/frequency setting\, yielding overall energy reduction. \nApplying the proposed transformation techniques on kernels taken from different application domains\, we measured a substantial performance and energy improvement.
URL:https://www.cecs.uci.edu/event/algorithmic-code-optimization-using-conditional-expression-evaluation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090805T150000
DTEND;TZID=America/Los_Angeles:20090805T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14279-1249484400-1249488000@www.cecs.uci.edu
SUMMARY:Portable Direct Methanol Fuel Cell System for Green Computing
DESCRIPTION:Portable Direct Methanol Fuel Cell System for Green Computing\n\n\n\n\nSpeaker\n\n\nDr. Naehyuck Chang\nSeoul National University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nCalIT2 Room 3008\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nAugust 5 \, 2009\nRefreshments at 10:00 am\, Lecture begins at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe introduce a hybrid portable direct methanol fuel cell (DMFC) system\nwhich includes a li-ion battery. We demonstrate a hybrid operation of\nthe DMFC stack and the li-ion battery to maintain a constant stack\noutput current regardless of the load current to maximize the\nperformance. We describe the balance of plant (BOP) control system\,\nincluding a 32-bit microprocessor\, and electronics to drive motors\,\nactuators and sensors for reliable operation and protection of a DMFC\nsystem. The dynamics of BOP control is taken into account to design\nmultiple cascaded feedback control loops. We demonstrate robust\noperation of a DMFC system together with introduction of a DMFC system\ndesign. This talk includes a working prototype system demonstration of a\ncomplete DMFC and battery hybrid power source.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nNaehyuck Chang received his BS\, MS and PhD degrees all from Seoul National University\, in 1989\, 1992 and 1996\, respectively. He was a research associate at Dept. of Electrical Engineering and Computer Science at University of Michigan in Ann Arbor in 1997. He joined Seoul National University in Dept. of Computer Science and Engineering in 1997 as a faculty member and now is an Associate Professor in Dept. of Electrical Engineering and Computer Science. He was also a Visiting Associate Professor at Arizona State University in 2005. He has been with Sindoricoh\, Co. Ltd.\, as a Technical Advisor since 2001. He has published more than 70 technical papers in low-power and embedded systems area.
URL:https://www.cecs.uci.edu/event/portable-direct-methanol-fuel-cell-system-for-green-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090724T150000
DTEND;TZID=America/Los_Angeles:20090724T160000
DTSTAMP:20231011T185436Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T185436Z
UID:14280-1248447600-1248451200@www.cecs.uci.edu
SUMMARY:Application Specific Multicore Chips for Medical Services
DESCRIPTION:Dr. Iyad Al Khatib\, Solidux Telecom ABStockholm\, Sweden\nEngineering III 2430\nJuly 24\, 2009\nAbstract
URL:https://www.cecs.uci.edu/event/application-specific-multicore-chips-for-medical-services/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090722T150000
DTEND;TZID=America/Los_Angeles:20090722T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14281-1248274800-1248278400@www.cecs.uci.edu
SUMMARY:Compiler-enabled Power-efficient Register File Protection
DESCRIPTION:Compiler-enabled Power-efficient Register File Protection\n\n\n\n\nSpeaker\n\n\nDr. Jongeun Lee\nEECS\, Ulsan National Institute of Science and Technology\,Korea\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 22\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRegister file (RF) is extremely vulnerable to soft errors\, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor\, but also since it is one of the hottest blocks on the chip\, and therefore adding any extra circuitry to it is not desirable. Software approaches would be ideal in this case\, but previous approaches that are based on program duplication have very significant runtime overheads\, and others based on instruction scheduling are only moderately effective due to local scope.  \nThis talk will be about how compiler alone and in conjunction with microarchitecture can power-efficiently protect the RF. What we have observed is that a significant portion of the RF vulnerability is contributed by long lifetime variables. Protecting only these can result in power-efficient RF protection. Thus the task of the compiler is to identify program variables that have long lifetimes and protect them. Our experiments demonstrate pure compiler techniques can reduce the vulnerability of the RF by 33-37% on average and up to 66%\, with a small (2%) runtime overhead. As compared to hardware protection mechanisms\, compiler analysis can achieve the same level of protection but at up to 75% lesser RF energy consumption.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nJongeun Lee received a BS and an MS in Electrical Engineering and a PhD in Electrical Engineering and Computer Science all from Seoul National University. Previously he was with Samsung SoC R&D Center in Korea\, and is currently a postdoctoral associate at Arizona State University\, working with Dr. Aviral Shrivastava. He is joining Ulsan National Institute of Science and Technology\, Korea\, as an Assistant Professor of EECS. His research interests include configurable/reconfigurable processor architecture design\, compilation for energy and reliability\, and compilation for multicore processors and GPUs.
URL:https://www.cecs.uci.edu/event/compiler-enabled-power-efficient-register-file-protection/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090709T150000
DTEND;TZID=America/Los_Angeles:20090709T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14319-1247151600-1247155200@www.cecs.uci.edu
SUMMARY:Transducer Synthesis for Heterogeneous Multi-processor Systems
DESCRIPTION:Transducer Synthesis for Heterogeneous Multi-processor Systems\nby Hansu Cho \nLocation: EH 2210 \nDate and Time: July 9\, 2009\, 8:30 AM \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nContemporary system design requires more computational power than ever. To overcome this problem\, MPSoC is widely used\, but design complexity have been increased rapidly. Meanwhile\, short time to market forced system designer to reduce development time. Therefore\, designer raised the level of abstraction into the higher level called transaction level. But\, current high level synthesis tools are dedicated to computational components only. To our best knowledge\, there is no synthesis tool for communication components from the transaction level model down to RTL model. In this dissertation\, we present a component called transducer which can handle heterogeneous MPSoC communication with multiple buses. Also\, we presents a tool for automatic synthesis of transducer. The tool captures the communication parameters in the platform at transaction level and generates transducer in RTL. The design and configuration of the transducer depend on several platform components including heterogeneity of the components\, traffic on the bus\, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the transducer can be automatically derived based on these parameters. \nThe advantage of this approach is that the user may modifies transducer parameters to suit specific optimization goals. In contrast to conventional approaches like IP wrappers\, our approach enables the user to generate an application specific interface between any number of buses for any platform configuration. Therefore\, the system designer is not bound to a set of IPs or protocols for their platform definition. Furthermore\, due to automatic generation\, we provide several orders of magnitude savings in interface development cost. We demonstrate the synthesizability and quality of our automatically generated transducers using Xilinx ISE tools and FPGA board. We use industrial strength design drivers such as an MP3 decoder and JPEG encoder to test our automatically generated transducers for a variety of platforms and compare them to manually designed transducers on different quality metrics. Our experimental results show that performance of automatically generated transducers are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 20X of improvement in development time.
URL:https://www.cecs.uci.edu/event/transducer-synthesis-for-heterogeneous-multi-processor-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090618T150000
DTEND;TZID=America/Los_Angeles:20090618T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14320-1245337200-1245340800@www.cecs.uci.edu
SUMMARY:Automatic Generation and Verification of Transaction Level Models
DESCRIPTION:Automatic Generation and Verification of Transaction Level Models\nby Lochi Yu \nLocation: ET 331 \nDate and Time: June 18\, 2009 10:00am \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nThe rising complexity in system designs over the past decades poses great challenges to current designers. One way to cope with this challenge has been to raise the level of abstraction of design\, reducing the number of elements and speeding up design decisions. Transaction Level Models (TLM) have emerged as a new alternative to design Multi-Processor System-on-Chips (MPSoC). TLMs express communication among modules at the transaction level\, without simulating the dozens of individual signals in communication elements such as busses. Nevertheless\, several drawbacks exist: TLMs are fast\, but their accuracy is low\, TLMs are being coded manually\, often by the use of a System Level Design Language (SLDL)\, there is no widely-adopted and tool-supported TLM style\, and there has been little work on verifi cation at the System Level. In this dissertation\, we aimed to contribute in different aspects: We defined a modeling style for SystemC TLMs whose modules have a one-to-one relationship with actual synthesized modules in a FPGA. Then\, we defined a data structure\, complete and flexible enough to describe a complete embedded system\, its hardware platform and application\, and developed generation algorithms that would use it to automatically produce an executable TLM in SystemC. Fourth\, we designed new transformation rules for models in Model Algebra (MA) that allows veri cation on pipelined models in MA. With our approach\, we can have automatic generation and verification of Transaction Level Models\, freeing the designer from error-prone manual coding\, and allows him to focus on higher level design decisions\, speeding up the overall design phase.
URL:https://www.cecs.uci.edu/event/automatic-generation-and-verification-of-transaction-level-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090603T150000
DTEND;TZID=America/Los_Angeles:20090603T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14321-1244041200-1244044800@www.cecs.uci.edu
SUMMARY:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors
DESCRIPTION:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors\nby Ashok Halambi \nLocation: DBH 4013 \nDate and Time: June 3\, 2009 2:00pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Alex Nicolau\nProfessor Alex Viedenbaum \nAbstract:\nEmbedded systems continue to increase in functionality\, complexity and connectivity. Programmable platforms\, consisting of processors programmable in software\, are a popular solution to satisfy the design constraints (such as cost\, performance\, flexibility\, reliability etc.) of such systems. Key challenges in the design of programmable platforms include compiler-in-loop design space exploration (DSE)\, and automatic generation of software toolkit for hardware/software co-design. \nA language-based model of the processor-memory subsystem has several benefits: it serves as a golden reference model for all principals involved in the design; it can be used to drive DSE and automatic software toolkit generation; it can be used to perform top-down (formal) verification and validation; and\, it can be refined down to implementation (register-transfer level). In this dissertation\, we present EXPRESSION\, an architecture description language (ADL) that is designed for DSE of processor-memory sub-system and automatic generation of software toolkit including compiler and cycle-accurate simulator. EXPRESSION has been used to describe various processors from RISC (DLX\, MIPS R4000\, ARM 9)\, VLIW (TI C6x)\, DSP (ST100)\, etc. Our EXPRESSION based DSE methodology permits exploration of a wide range of processor architectures\, and includes compiler-in-loop for accurate analysis of each design configuration. \nTo aid compiler-in-loop DSE\, we developed EXPRESS\, a retargetable\, instruction level parallelizing compiler that accepts programs in “C” and produces assembly code for the target processor described in EXPRESSION. The EXPRESS compiler is capable of handling irregular architectures\, and can adapt to changes in the processor’s instruction-set or micro-architecture. EXPRESS also includes a framework for dynamic customization of the compiler based on the target application and architecture characteristics. These capabilities of EXPRESS make it ideal for use in the DSE of processor-memory subsystems. \nRetargetable compilers suffer from the drawback of poor output code quality as compared to a compiler that is “hand-crafted” for the target processor. Key differences between the two compilers include the presence of target specific optimizations and custom phase ordering of optimization passes in the target specific compiler. In this dissertation\, we propose a framework\, called TransMutations\, that enables dynamic\, run-time customization of a retargetable compiler. It allows for easy integration of optimizations (called mutations) into the compiler and solves the phase ordering problem by applying optimizations in a context-sensitive manner for each region of the application code. The TransMutations framework has been implemented in the EXPRESS compiler and we present results demonstrating the effectiveness of the technique. This framework improves the quality of code generated by retargetable compilers and enables them to be used in accurate compiler-in-loop DSE of programmable embedded systems.
URL:https://www.cecs.uci.edu/event/transmutations-a-framework-for-dynamic-customization-of-retargetable-compilers-for-embedded-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090529T150000
DTEND;TZID=America/Los_Angeles:20090529T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14322-1243609200-1243612800@www.cecs.uci.edu
SUMMARY:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement
DESCRIPTION:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement\nby Aseem Gupta \nLocation: DBH 3011 \nDate and Time: May 29\, 2009 1:30pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Fadi Kurdahi\nProfessor Tony Givargis \nAbstract:\nProcess scaling and shrinking device geometries have resulted in chips with greater performance and complexity levels. However\, these advancements have come at the cost of higher power densities and increased operating temperatures. The inability to control the operating temperatures by existing cooling techniques is the principal reason for discontinuation of an increase in frequencies and introduction of multi-core architectures. Apart from operability\, high temperatures have unfavorable consequences such as: increased leakage power\, reduced interconnect life time\, slowing of interconnects and transistors\, need for expensive package and cooling mechanisms\, and increased manufacturing cost and design effort. Traditionally\, thermal issues have been examined only at the post-synthesis stages of the design flow. This thesis attempts to migrate the “thermal awareness” from the physical level design phase to early stages of the VLSI design flow and utilize it to target various design metrics such as power\, performance\, reliability\, and operability. This thesis advances the procedure of leakage power estimation by coupling it with thermal profile estimation and capturing the positive interdependence between temperature and leakage power. It also advances the traditional role of communication architecture to that of an active thermal manager. The proposed communication architecture based thermal manager delays the execution of chosen components by regulating the flow of data over the on-chip communication fabric. This dissertation demonstrates the need of examining the effects of frequency\, supply voltage\, power dissipation\, and temperature on SRAM reliability in a mutually interrelated manner. Our observation contradicts the conventional belief that increasing supply voltage always reduces the failure rate in SRAMs. Because of thermal effects\, an increase in the supply voltage can also lead to increase in the SRAM failure rate. This thesis also extends the procedure of system level floorplanning to manage the leakage power and reliability of the design. The fundamental contribution of this thesis is that it advances the traditional design flow in the direction of incorporating thermal awareness during various stages of the flow.
URL:https://www.cecs.uci.edu/event/temperature-aware-vlsi-design-for-reduced-power-and-reliability-enhancement/
CATEGORIES:PhD Defenses
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