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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160404T150000
DTEND;TZID=America/Los_Angeles:20160404T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14445-1459782000-1459785600@www.cecs.uci.edu
SUMMARY:Power Optimization for Medical Sensing Systems
DESCRIPTION:Name:  Jun Luan\nLocation:  EH 4106 \nDate: February 24\, 2016 \nTime: 1:00pm \nCommittee: Pai Chou (Chair)\, Mohammad Al Faruque\, Fadi Kurdahi \nAbstract:  \nMedical sensing systems collect and analyze the patients’ physiological data for monitoring\, aid or diagnostic purposes. System designers are faced with stringent requirements on not only correctness and safety but also power. Reference designs and multi-purpose platforms help to significantly shorten the development cycle. \nThis work takes a cross-layer\, system-level\, platform-based approach to addressing the problem of saving power in a class of portable medical system. We propose a low-power medical sensing system that can be used to monitor Electrocardiography (ECG)\, Photo- plethysmogram (PPG)\, and muscle tension. It also includes a hand gesture recognition system to aid mobility-impaired patients. \nWe explore the theory and application of a compressive sensing framework to medical signal processing. A novel compressive sensing-based ECG compression algorithm and a dominant frequency extraction-based PPG heart-rate calculation algorithm are proposed to reduce the system power. The unique combination of hardware structure and software signal-processing algorithms makes low-power design possible. The system test results show that the proposed system is superior to existing works in terms of power consumption and system size.
URL:https://www.cecs.uci.edu/event/power-optimization-for-medical-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160404T150000
DTEND;TZID=America/Los_Angeles:20160404T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14446-1459782000-1459785600@www.cecs.uci.edu
SUMMARY:Frameworks and Algorithms for Wearable Medical Applications
DESCRIPTION:Name:  SeungJae Lee\nDate:  April\, 5\, 2016 \nTime:  3:00p.m. \nLocation:  EH 4106 \nCommittee:  Pai H. Chou (Chair)\, Fadi Kurdahi\, Tony Givargis \nAbstract: \nWearable embedded systems with sensing\, communication\, and computing capabilities have given rise to innovations in e-health and telemedicine in general. The scope of such systems ranges from devices and mobile apps to cloud backend and analysis algorithms\, all of which must be well integrated. To manage the development\, operation\, and evolution of such complex systems\, a framework systematic framework is needed. This dissertation makes contributions in two parts. First is a framework for defining the structure of a wide range of wearable medical applications with modern cloud support. The second part includes several algorithms that can be plugged into this framework for making these systems more efficient in terms of processing performance and data size. We propose a novel QT analysis algorithm that can take advantage of GPU as well as in a server-client environment\, and we show competitive results in terms of both performance and energy consumption with or without parallelization. We also propose ECG compression techniques using trained overcomplete dictionary. After constructing the dictionary through learning process with a given dataset\, the signal can be compressed by sparse estimation using the trained dictionary. We propose reconstructing ECG signal from undersampled data based on compressive sensing framework that can reconstruct the ECG signals precisely from fewer samples so long as the signal is sparse or compressible. Together\, these algorithms operating in the context of our proposed framework validate the effectiveness of our structured approach to the framework for wearable medical application. \n 
URL:https://www.cecs.uci.edu/event/frameworks-and-algorithms-for-wearable-medical-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160218T150000
DTEND;TZID=America/Los_Angeles:20160218T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190554Z
LAST-MODIFIED:20231011T190555Z
UID:14453-1455807600-1455811200@www.cecs.uci.edu
SUMMARY:Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes
DESCRIPTION:Title: “Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes”\nSpeaker: Professor Khaled N. Salama\, King Abdullah\, University of Science and Technology\, Saudi Arabia \nDate and Time: Thursday\, February 18\, 2016 at 11:00 A.M. \nLocation: Engineering Hall 2430 \nHosts: Fadi J. Kurdahi and Ahmed Eltawil \nAbstract: Energy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. However\, the capacitive sensor readout circuit—i.e.\, the capacitance-to-digital converter (CDC) —can be the dominant source of energy consumption in the system. Thus\, the development of energy-efficient CDC architectures is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this talk\, we propose several energy -efficient CDC architectures for low-energy sensor nodes. In the second part\, we study the matching properties of small integrated capacitors\, which are an integral component of energy-efficient CDCs. Despite conventional wisdom\, we experimentally illustrate that the mismatch of small capacitors can be directly measured\, and we report experimental mismatch measurements for sub-femtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors\, and we identify the conditions that make one implementation preferable. \nBio: Dr. Salama received his bachelor’s degree with honors from the Electronics and Communications Department at Cairo University in Egypt in 1997\, and his master’s and doctorate degrees from the Electrical Engineering Department at Stanford University in the United States\, in 2000 and 2005 respectively. He was an assistant professor at RPI between 2005 and 2008. He joined King Abdullah University of science and technology (KAUST) in January 2009 and was the electrical engineering founding program chair till August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford-Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc in 2008. He is the cofounder of ultrawave labs\, a biomedical imaging company that was recently acquired. He is the co-author of 90 papers and 10 patents on low-power mixed-signal circuits for intelligent fully integrated sensors and non linear electronics specially memristor devices. He is a senior member of IEEE. \nView Details Here
URL:https://www.cecs.uci.edu/event/energy-efficient-capacitance-to-digital-converters-for-low-energy-sensor-nodes/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160208T150000
DTEND;TZID=America/Los_Angeles:20160208T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14459-1454943600-1454947200@www.cecs.uci.edu
SUMMARY:Mitigating BTI-induced Device Degradation: A Circuit and System Persepctive
DESCRIPTION:Title: Mitigating BTI-induced Device Degradation: A Circuit and System Persepctive\nSpeaker: Professor Ing-Chao Lin\, National Cheng Kung University\, Taiwan \nDate and Time: Monday\, February 8\, 2016 at 1:30 P.M. \nLocation: Donald Bren Hall 3011 \nHost: Professor Nikil Dutt \nAbstract: Bias temperature instability which causes a shift in the transistor’s threshold voltage and decreases circuit switching speed has become a major reliability concern. In this talk\, I will introduce the techniques to mitigate device degradation at the circuit and system level\, and provide design guidelines to deal with device degradation. The future trend on device degradation will be introduced as well. \nBiography: Prof. Ing‐Chao Lin received his M.S. degree from Dept. of Computer Science and Information Engineering\, National Taiwan University and Ph.D. degree from Dept. of Computer Science and Engineering\, the Pennsylvania State University 2001 and 2007\, respectively. From 2007 to 2009\, he is a staff R&D engineer in Real Intent Inc.\, CA\, USA\, where he is working on Real Intent’s automatic timing exception verifier. His research interest includes reliable power‐aware system\, electronic design automation\, and computer architecture. He has authored or co‐authored more than 50 scientific papers and is a committee member of many technical conferences. He is a senior member of IEEE and he is thechair of IEEE Tainan Young Professional group. He is the recipient of 2015 Excellent Young Researcher Award by Chinese Institute of Electrical Engineering. He is currently a visiting scholar in Dept. of Electrical and Computer Engineering\, University of California\, Santa Barbara. \n  \nView more details here \n 
URL:https://www.cecs.uci.edu/event/mitigating-bti-induced-device-degradation-a-circuit-and-system-persepctive/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20151110T150000
DTEND;TZID=America/Los_Angeles:20151110T160000
DTSTAMP:20231011T190612Z
CREATED:20231011T190612Z
LAST-MODIFIED:20231011T190612Z
UID:14468-1447167600-1447171200@www.cecs.uci.edu
SUMMARY:Mobile Technology Enabling Frictionless HealthCare
DESCRIPTION:Title: “Mobile Technology Enabling Frictionless HealthCare”\nSpeaker: Aiman Abdel-Malek\, Vice President\, Engineering\, Qualcomm Life\, Founder & CEO\, Frictionless Life Analytics \nDate:  Tuesday\, November 10\, 2015 \nTime:  3:00 p.m. \nLocation:  Engineering Hall 2430 \nHost: Prof. Fadi J. Kurdahi \nAbstract: With Smart mobile devices being the fastest growing consumer platform in history\, it is becoming a huge enabler to new business models that reduce friction in daily life. Aiman will introduce how mobile technology is creating solutions to many of the current healthcare issues and enabling moving care from the hospital to the home. \nBio: Aiman joined Qualcomm Life from General Electric’s Healthcare Division in Sept 2012\, where he served as GM and CTO for the Global Services Technology business\, a $5 billion division of GE healthcare. There he led a global engineering team responsible for the development of software and systems platforms for predictive remote service technology and healthcare operational efficiency and quality applications. Aiman served GE for 25 years; 10 years in R&D helping the development of GE’s first digital x-ray mammography system and digital Ultrasound system. He then moved to GE Transportation to start and manage the first Satellite wireless-based Locomotive Remote Predictive Services business\, which currently runs on over 20\,000 locomotives. Afterward\, he took an expat assignment in the United Kingdom\, as technology managing director for the Pipeline Inspection Services\, a $400 million global business unit of GE Oil and Gas. Aiman’s technical expertise is in the development of vision inspired signal processing algorithms for aerospace\, industrial and medical applications. He earned his PhD in Systems & Biomedical engineering from the University of Southern California\, completing post-doctoral research at UCLA in neurology. He is a senior member of the IEEE and holds over 22 US and international patents. He serves as a member of the Scientific Advisory Board for the Qualcomm-Xprize Tricorder competition. Also\, he served on GE’s Corporate Software Board\, and as an executive leader for the Image & Signal Processing Technology Council for GE Healthcare. Aiman recently founded his own company\, which aims at helping guide California startups & ventures move from “concept” to “scale” in most frictionless path. He is also a Board Advisor to few startups. \nView Details Here\n 
URL:https://www.cecs.uci.edu/event/mobile-technology-enabling-frictionless-healthcare/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150924T150000
DTEND;TZID=America/Los_Angeles:20150924T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14460-1443106800-1443110400@www.cecs.uci.edu
SUMMARY:When Lyapunov meets Church\, automated synthesis of complex systems emerges
DESCRIPTION:Title: When Lyapunov meets Church\, automated synthesis of complex systems emerges\nSpeaker: Prof. Majid Zamani\, Technische Universität München\, Germany \nDate: Thursday\, September 24\, 2015 \nTime: 3:30 p.m. \nLocation: Engineering Colloquia Room 2430 \nHost: Faryar Jabbari and Solmaz S. Kia \nAbstract: Software plays a crucial role in many everyday applications. Modern vehicles and\nairplanes\, for instance\, use interacting software and hardware components to control steering\, fuel in\njection\, and airbag deployment. These applications are examples of cyber-­‐physical systems (CPS)\, where software components interact tightly with physical systems. Recent advances in device manufacturing\, computation\, storage\, and networking have made tremendous advances in hardware and systems platforms for CPS. However\, the development of core software controllers that run on these systems is still ad hoc and error-­‐prone. Many CPS applications are safety-­‐critical\, and much of the engineering costs today are consumed with ensuring that software works correctly. In this talk\, I will proposes a transformative design process\, in which the controller code is automatically synthesized from higher-­‐level correctness requirements. Requirements for modern CPS applications go beyond conventional requirements in control theory (stability\, synchronization\, and tracking) and\nbeyond traditional protocol design in computer science. Accordingly\, I will propose unified methodologies for automatic controller synthesis by combining techniques from discrete systems theory from computer science with continuous dynamical systems from control theory. The proposed automated synthesis of correct-­‐by-­‐ construction controllers holds the potential to develop complex yet reliable CPS applications while considerably reducing verification and validation costs.\n\n\nBio: Majid Zamani is an assistant professor in the Department of Electrical and \nComputer Engineering at Technische Universität München where he leads the Hybrid Control Systems Group. He received a Ph.D. degree in Electrical Engineering and an MA degree in Mathematics both from University of California\, Los Angeles in 2012\, an M.Sc. degree in Electrical Engineering from Sharif University of Technology in 2007\, and a B.Sc. degree in Electrical Engineering from Isfahan University of Technology in 2005. From September 2012 to December 2013\, he was a postdoctoral researcher in the Delft Centre for Systems and Control at Delft University of Technology. Between December 2013 and May 2014\, he was an assistant professor at Delft University of Technology.nd RSS). He is the Editor-­‐in-­‐Chief of the Springer journal Autonomous Robots.\n\n\nView Details Here
URL:https://www.cecs.uci.edu/event/when-lyapunov-meets-church-automated-synthesis-of-complex-systems-emerges/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150729T150000
DTEND;TZID=America/Los_Angeles:20150729T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14444-1438182000-1438185600@www.cecs.uci.edu
SUMMARY:A Centralized IoT Middleware System for Devices Working Across Application Domains Using Self-descriptive Capability Profile
DESCRIPTION:Name: Chengjia Huo\nLocation: EH 4404 \nDate: September 30\, 2015 \nTime: 1pm \nCommittee: Pai H. Chou (chair)\, Phillip Sheu\, Rainer Doemer \nAbstract: \nThe Internet of Things (IoT) has been receiving growing attention in recent years as the next wave of computing revolution made possible by all types of networks of things (NoTs)\, where devices powered with low-cost\, miniature low-power systems-on-chip (SoC) with computing and communication capabilities\, and are bridged to the Internet with the assistance of gateways. More and more NoT device are designed to provide more than one functionalities to fulfill different requirements from the application domains. We believe that the true power of IoT is that functionalities of devices can work across application domains. In order to reveal the potential of IoT\, the description of a device’s capability needs to represent the functionalities that the device can provide. We discover the previous solutions on describing a device’s capability focus mainly on hiding the vendor-specific interfaces made by different manufacturers\, but they do not reflect different functionalities that a device provides. In this thesis\, the concept of device capability profile is proposed. Different from the previous solutions\, the device capability profile specified in the firmware of a device allows the device to work across different application domains. Together with device capability profile\, a centralized IoT middleware framework\, called rimware\, is proposed. Rimware tracks every device’s capability and state in a centralized manner and provides different ways for application domains to query against the device’s functionalities. In addition\, rimware utilizes the device capability profile to carry out the enforcement of the security and privacy throughout the communication with the devices. Moreover\, tasks can be scheduled through the rimware which enables functionalities from multiple devices to work together to fulfill the requirements from application domains. Optimization is applied on cases that one device working for multiple task simultaneously. An implementation of rimware that is specifically designed for BLE devices\, called BlueRim\, which takes advantages of BLE’s very long battery life on the device side and the cloud functionality on the centralized side is provided. The fundamental features of rimware have been validated in several real-world applications from different different domains while incurring minimal code size and communication overhead on BLE devices. We believe that our approach represents an important technology in taking IoT closer to realizing the full potentials.
URL:https://www.cecs.uci.edu/event/a-centralized-iot-middleware-system-for-devices-working-across-application-domains-using-self-descriptive-capability-profile/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150729T150000
DTEND;TZID=America/Los_Angeles:20150729T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14438-1438182000-1438185600@www.cecs.uci.edu
SUMMARY:Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems
DESCRIPTION:Speaker:  Prof. Muhammad Mustafa Hussain\, King Abdullah University of Science and Technology (KAUST) \nTitle:  “Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems” \nDate:  Tuesday\, April 21\, 2015 \nTime:  2:00 PM \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost:  Prof. Fadi Kurdahi \nAbstract: Our research is focused on heterogeneous electronic materials and high-performance complementary metal oxide semiconductor (CMOS) based tunable shape-size-conformity wearable interactive electronics and systems for smart living (computation-communication-infotainment) through internet of everything and a sustainable future (healthcare-water-food-environment-security). For scientific exploration\, we make collective use of the materials\, processes and device architecture leveraging multidisciplinary tracks of material science\, bioengineering\, mechanical\, environmental engineering and computer science. As engineering tool\, we use CMOS technology extensively due to its industrial relevance\, maturity and reliability for rapid tech transfer.\nTo bridge between the high-performance state-of-the-art electronics and emerging soft-materials based flexible-stretchable electronics. we have developed various generic batch processes using CMOS technologies to transform any already processed Integrated Circuitry (IC) or arrays of devices to be fabricated on virgin substrates (thin film based\, examples include but not limited to: silicon\, silicon germanium\, indium phosphide\, gallium arsenide\, etc.) into flexible and stretchable one [ACS Nano 2014\, pss-RRL 2014]. These processes are cost effective ($1.25/cm2)\, non-abrasive and retain high-performance\, energy-efficiency\, ultra-large-scale-integration density as obtained in today’s state-of-the-art electronics. Often the transformed fabrics (ultra-thin version of the bulk thin film substrates with pre-fabricated devices) are semi-transparent due to the presence of the process originated vertical channels. As per ITRS 2014 metrics\, the processes are fully scalable down to 2 nm technology node. Using these techniques we have demonstrated high-κ/metal gate based planar and non-planar nano-scale (sub-20 nm) CMOS logic devices [Adv. Mater. 2014 (cover page)\, ACS Nano 2014\, APL 2013\, pss-RRL 2013 (cover pages)\, IEEE TED 2013\, pss-RRL 2013\, Sci. Rep. 2013\, pss-RRL 2013]\, memory [Adv. Electronic Mater. 2015\, Microelect. Engr. 2014]\, micro-scale thermoelectric generators [Small 2013 (frontispiece)]\, micro lithium ion batteries (150 μAh/cm2 normalized capacity)\, MEMS devices [MEMS 2014]\, smart thermal patch using copper stretched up to 800% [Adv. Healthcare Mater. 2015 (frontispiece)]\, mono-crystalline silicon stretched up to 1000% [APL 2014]. Variety of device demonstrations on wide range of inorganic thin films using this technique proves the efficiency and versatility of it. Our research greatly complements the $150M Flexible Hybrid Electronics Manufacturing Initiative (FHEMII) – recently introduced by the US Department of Defense: “Highly tailorable devices on flexible\, stretchable substrates that combined thinned CMOS components with components that are added via printing process”.\n \nView Details
URL:https://www.cecs.uci.edu/event/flexible-stretchable-reconfigurable-cmos-electronics-through-hybrid-integration-of-heterogeneous-materials-for-wearable-interactive-electronic-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150714T150000
DTEND;TZID=America/Los_Angeles:20150714T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14437-1436886000-1436889600@www.cecs.uci.edu
SUMMARY:The Future of Heterogeneous Massive Parallel Systems
DESCRIPTION:Speaker: Prof. Avi Mendelson\, Technion\, Israel Institute of TechnologyTitle: The Future of Heterogeneous Massive Parallel Systems\nDate: Wednesday\, October 8\, 2014\nTime: 3:00PM – 4:30PM\nLocation: Donald Bren Hall 3011 \nHost: Prof. Alex Nicolau \nView Details
URL:https://www.cecs.uci.edu/event/the-future-of-heterogeneous-massive-parallel-systems/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150709T150000
DTEND;TZID=America/Los_Angeles:20150709T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14436-1436454000-1436457600@www.cecs.uci.edu
SUMMARY:Reviving Processing-in-Memory for Large Data Workload on Existing Computer Architecture
DESCRIPTION:Speaker:  Professor Sungjoo Yoo\, Computing and Memory Architecture Lab\, Seoul National University \nTitle:  Reviving Processing-in-Memory for LArge Data Workload on Existing Computer Architecture \nDate:  Tuesday\, July 14\, 2015 \nTime:  11:00 AM \nLocation:  Donald Bren Hall 3011 \nHost:  Nikil Dutt \nAbstract:  Processing-in-memory (PIM) is rebounding from its unsuccessful attempts in 1990s due to two main reasons\, recent advances in 3D stacking technologies and emerging large data workload.  In this talk\, we present two of our recent works\, PIM for large data workload and combining PIM with the existing computer architecture.\nGraph data are becoming more and more popular in many areas such as machine learning\, social network analysis\, etc.  Graph computation is to process a query to the graph database\, e.g.\, finding the most popular personality.  Graph computation is characterized by computation parallelism (per-vertex parallel computation) and significant random memory accesses (to neighbor vertices).  The conventional architecture is not well suited for this type of workload.  We present a programmable PIM accelerator for large-scale graph processing called Tesseract.  Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth\, (2) an efficient method of communication between different memory partitions\, and (3) a programming interface that reflects and exploits the unique hardware design.  It also includes two hardware prefecthers specialized for memory access patterns of graph processing\, which operate base on the hints provided by our programming model.\nIn order to make best use of PIM in more areas\, it is required to integrate the PIM architectures with existing systems in a seamless manner.  The current PIM proposals lack due to two common characteristics: unconventional programming models for in-memory computation units (as programmable co-processors) and lack of ability to utilize large on-chip caches.  We propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data.  The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions\, which we call PIM-enabled instructions\, to invoke in-memory computation.  This allows PIM operations to be interoperable with existing programming models\, cache coherence protocols\, and virtual memory mechanisms with no modification. \nView Details
URL:https://www.cecs.uci.edu/event/reviving-processing-in-memory-for-large-data-workload-on-existing-computer-architecture/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150528T150000
DTEND;TZID=America/Los_Angeles:20150528T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14435-1432825200-1432828800@www.cecs.uci.edu
SUMMARY:Computational Neuroscience for Technology: Event-based Vision Sensors and Information Processing
DESCRIPTION:Speaker:  Prof. Jörg Conradt\nTitle:  Computational Neuroscience for Technology: Event-based Vision Sensors and Information Processing \nDate:  Tuesday\, June 2\, 2015 \nTime:  3:00 p.m. \nLocation:  Donald Bren Hall 4011 \nHost:  Jeff Krichmar and Nikil Dutt \nAbstract:  \nIn recent decades the field of Computer Vision has developed sophisticated algorithms for problems such as object tracking or motion extraction based on sequences of high-resolution camera images. Applying such algorithms in real-time robotics reveals an inherent problem: they typically require high data bandwidth and high processing power\, which results in substantial computing machinery and/or delayed processing of data. As part of an optimized biological solution for vision\, our brain developed retinal receptor cells that largely respond with asynchronous events (“neural spikes”) to temporal changes of brightness. Such encoding of visual information substantially reduces the amount of transmitted data and simultaneously increases temporal precision. \nRecently “silicon retinas” have been developed as specialized vision sensors to provide such neuro-inspired vision input for technical systems. Visual information obtained from these sensors differs substantially from traditional sequences of images\, which requires an “event-based” redesign of computer vision algorithms. This talk introduces the neuro-inspired vision sensors and presents event-based algorithms for applications such as real-time computation of optic flow and visual object tracking at high update rates on minimalistic computing hardware. \nView Details
URL:https://www.cecs.uci.edu/event/computational-neuroscience-for-technology-event-based-vision-sensors-and-information-processing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150521T150000
DTEND;TZID=America/Los_Angeles:20150521T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14434-1432220400-1432224000@www.cecs.uci.edu
SUMMARY:CARL-SJR: A Socially Assistive Neurorobot for Autism Therapy and Research
DESCRIPTION:Name: Ting-Shuo Chou\nDate: May 21\, 2015 \nTime: 3:00pm – 5:00pm \nLocation: Social & Behavioral Sciences Gateway 2200 Conference Room \nCommittee Chair: Jeffrey Krichmar (Chair)\, Nikil Dutt\, Alexandru Nicolau \nAbstract: \nNeurodevelopmental disorders\, such as Attention-Deficit–Hyperactivity\nDisorder (ADHD) and Autism Spectrum Disorder (ASD)\, have core clinical\nsymptoms of inattention\, hyperactivity\, and impulsivity (often hyper-\nand hypo- responsiveness. These symptoms are often accompanied by\nreduced motor coordination and impaired sensory processing. We introduce\na Socially Assistive Robot (SAR) with the goal of automating therapy for\nchildren with neurodevelopmental disorders. The novel robot\, which is\ncalled Cognitive Anteater Robotics Laboratory – Spiking Judgment Robot\n(CARL-SJR)\, is designed for therapy and diagnosis. CARL-SJR is\nautonomous and capable of tactile sensing and interaction. A spiking\nneural network model and neurally inspired algorithms controls\nCARL-SJR’s behavior. By providing a large tactile sensing surface that\nencourages touching with hand movements\, CARL-SJR especially addresses\nimpairments in tactile sensitivity and social interaction observed in\nchildren with neurodevelopmental disorders. Using CARL-SJR\, we conducted\na pilot study where children with different neurodevelopment disorders\nshow different behavioral metrics and tactile movements. The results\nsuggest CARL-SJR might serve as a diagnose tool for developmental\ndisorders. Second\, we showed that the information carried by temporal\ncoding is higher than the traditional rate coding when decoding spike\ntrains in response to tactile movements. Third\, we implemented online\nlearning capabilities on CARL-SJR\, where the robot could associate a\nuser’s preferred color pattern displayed on the robot with the user’s\nhand sweep across the robot’s body. The emerged behaviors and neural\nactivities in the SNN are consistent with biological recordings. The\nunderlying neural mechanism in the SNN also serves as an alternative\nexplanation of how brains encode timing and associate (or learning) two\ntemporal separated events.
URL:https://www.cecs.uci.edu/event/carl-sjr-a-socially-assistive-neurorobot-for-autism-therapy-and-research/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150521T150000
DTEND;TZID=America/Los_Angeles:20150521T160000
DTSTAMP:20231011T190511Z
CREATED:20231011T190511Z
LAST-MODIFIED:20231011T190511Z
UID:14433-1432220400-1432224000@www.cecs.uci.edu
SUMMARY:Ensuring Reliability and Fault-Tolerance for the Cyber-Physical System Design
DESCRIPTION:Name: Volkan Gunes\nDate: May 27\, 2015 \nTime: 11:00AM – 12:00PM \nLocation: Donald Bren Hall 3013 Conference Room \nCommittee: Tony Givargis (Chair)\, Alexandru Nicolau\, Ian Harris\, Steffen Peter \nAbstract: \nThe cyber-physical system (CPS) is a term describing a broad range of\ncomplex\, multi-disciplinary\, physically-aware next generation engineered\nsystems that integrate embedded computing technologies (cyber part) into\nthe physical world. Sensors play an important role in this integration\nbecause they provide the data extracted from the physical world for the\ncyber systems to fulfill the decision making process. However\, this\nprocess is likely to be misled by incorrect data due to sensor fault\noccurrences. \nIn this dissertation\, the main focus is on sensor fault mitigation and\nachieving high reliability in CPS operations. One of the challenges we\nponder is timely event (e.g.\, motion as a phenomenon) detection in CPS\nunder possible faulty sensor conditions. In this regard\, our\ndemonstrative example of CPS is the falling ball example (FBE) using\nbinary event detectors (i.e.\, motion sensors)\, a controller\, and a\ncamera for timely motion detection of a falling ball. Another challenge\nwe ponder is satisfying thermal comfort and energy efficiency under\ncertain faulty sensor conditions in a multi-room building incorporating\ntemperature sensors\, controllers\, and heating\, ventilation\, and air\nconditioning (HVAC) systems as a CPS application. For both cases\, we\nadopt a model-based design (MBD) methodology to analyze the effect of\nsensor faults on the desired system outcome. We specify well-defined\nfault semantics for the event detectors and temperature sensors to make\nthe problem definition more clear. We provide a MATLAB/Simulink\nsimulation framework for our CPS examples. Besides having the\ntraditional CPS model that comprises the cyber\, interface (e.g. sensors\nand actuators) and physical models\, we develop fault models and a system\nevaluation model in Simulink and incorporate them into the CPS model. \nWe explore various techniques for fault mitigation in a holistic design\nperspective. Therefore\, the approaches presented in this study\ncontributes to the design of fault-tolerant CPSs. Furthermore\,\nconsidering compute demands of large scale CPSs\, we introduce the XGRID\nembedded many-core system-on-chip architecture. XGRID makes use of a\nnovel\, FPGA-like\, programmable interconnect infrastructure\, offering\nscalability and deterministic communication using hardware supported\nmessage passing among cores. We provide a conceptual mapping of control\nalgorithms for the automation of a multi-room building onto target XGRID\narchitecture. \nOur findings regarding reliable CPS design show that the physical system\nattributes (e.g.\, sensor placement and environmental effects) can be a\nmore dominant factor than the cyber system attributes on the system\noutcome. In addition\, sensor faults may lead to unsatisfactory system\noutcome in CPSs since CPSs heavily rely on sensor readings for decision\nmaking. Therefore\, the analysis of temporal and spatial correlations\nbetween sensor readings helps mitigate certain types of sensor faults\nand enable CPSs to utilize sensors’ data more efficiently for decision\nmaking.
URL:https://www.cecs.uci.edu/event/ensuring-reliability-and-fault-tolerance-for-the-cyber-physical-system-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150515T150000
DTEND;TZID=America/Los_Angeles:20150515T160000
DTSTAMP:20231011T190511Z
CREATED:20231011T190511Z
LAST-MODIFIED:20231011T190511Z
UID:14432-1431702000-1431705600@www.cecs.uci.edu
SUMMARY:Temperature-Aware Design for SoCs using Thermal Gradient Analysis
DESCRIPTION:Name: Jun Yong Shin\nDate: May 18th\, 2015 \nTime: 2:00PM \nLocation: EH2430\, Harut colloquia room \nCommittee Chair: Nikil Dutt \nAbstract: \nOver the last few decades\, chip performance has increased steadily due to continuous and aggressive technology scaling. However\, it leaves chips quite vulnerable to several issues at the same time; high power densities in some particular areas spread across a chip might result in hotspots and thermal gradients\, and these can lead to permanent damage to the chip and also can reduce the reliability of the entire system using the chip. As a result\, a large number of dynamic thermal management solutions have been proposed in recent years for use in multi-core architectures\, and the accurate temperature information over the entire chip area has become indispensable especially for fine-grain dynamic thermal management solutions. Naturally\, on-chip thermal sensors came to play an important role in providing the accurate information on the temperature distribution of a chip\, but there still remain some issues regarding the allocation of on-chip thermal sensors; due to power\, area and routing issues\, it is preferable to limit the number of on-chip thermal sensors on a die\, and their placement needs to be considered carefully in order to increase the accuracy of full-chip thermal profile reconstruction especially when just a small number of sensors can be implemented; due to the limited reading accuracy of low-power\, small-sized on-chip thermal sensors\, it would be better to have some way to improve their reading accuracy. \nIn this work\, an issue will be firstly addressed regarding how to improve the reading accuracy of a low-power\, small-sized on-chip thermal sensor such as Ring-Oscillator (RO) based sensors at runtime on a software level. Secondly\, a question of how to allocate a proper number of sensors on a die in order to get the accurate full-chip scale thermal information on the run is addressed. Additionally\, a temperature-aware routing for global interconnects to minimize the delay and also to reduce the probability of chip failure due to electromigration is presented at the end.
URL:https://www.cecs.uci.edu/event/temperature-aware-design-for-socs-using-thermal-gradient-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150512T150000
DTEND;TZID=America/Los_Angeles:20150512T160000
DTSTAMP:20231011T190510Z
CREATED:20231011T190510Z
LAST-MODIFIED:20231011T190510Z
UID:14431-1431442800-1431446400@www.cecs.uci.edu
SUMMARY:Design Technologies for Embedded Multiprocessor Systems-on-Chip
DESCRIPTION:Speaker:  Prof. Rainer Leupers \nTitle: Design Technologies for Embedded Multiprocessor Systems-on-Chip \nDate: Thursday\, April 9\, 2015 \nTime: 11:00am \nLocation: Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Mohammad Al Faruque \nAbstract:  \nThe trend towards Multicore and even Manycore architectures affects virtually all areas of computing today. Especially in the mobiles and consumer domains\, an extremely high architectural efficiency (MIPS/Watt) is required. In order to manage the complexity of multi-billion transistor IC designs with dozens of heterogeneous processing engines\, advanced Electronic System Level (ESL) tools are required. ESL can be roughly subdivided into four categories: architecture modeling and optimization\, application SW mapping\, simulation and verification\, and efficient IP block design. After a general introduction to embedded MPSoC (Multiprocessor Systems-on-Chip) architectures and ESL technologies\, this seminar talk will cover selected aspects from the above four domains\, in particular ESL power estimation\, embedded multicore SW development\, fast virtual platforms\, and application-specific processor design. \nFor more information\, click here.
URL:https://www.cecs.uci.edu/event/design-technologies-for-embedded-multiprocessor-systems-on-chip/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150507T150000
DTEND;TZID=America/Los_Angeles:20150507T160000
DTSTAMP:20231011T190510Z
CREATED:20231011T190510Z
LAST-MODIFIED:20231011T190510Z
UID:14430-1431010800-1431014400@www.cecs.uci.edu
SUMMARY:Resilient On-Chip Memory Design in the Nano Era
DESCRIPTION:Final Defense – Abbas Banaiyanmofrad\n\nMay 20\, 2015\n3pm – 5pm\nDonald Bren Hall 3011 Conference Room \nCommittee:\nNikil Dutt (Chair)\, Alex Nicolau\, Alex Veidenbaum \nTitle:\nResilient On-Chip Memory Design in the Nano Era \nAbstract:\nAggressive technology scaling in the nano-scale regime makes chips more susceptible to failures. This causes multiple reliability challenges in the design of modern chips\, including manufacturing defects\, wear-out\, and parametric variations. By increasing the number\, amount\, and hierarchy of on-chip memory blocks in emerging computing systems\, the reliability of the memory sub-system becomes an increasingly challenging design issue. Existing resilient memory design schemes are unable to effectively address the key features of scalability\, interconnect-awareness\, and cost-effectiveness for these platforms. In this thesis\, we propose different approaches to address resilient on-chip memory design in computing systems ranging from traditional single-core processors to emerging many-core platforms. We classify our proposed approaches in five main categories: 1) Flexible and low-cost approaches to protect cache memories in single-core processors against permanent faults and transient errors\, 2) Scalable fault-tolerant approaches to protect last-level caches with non-uniform cache access in chip multiprocessors\, 3) Interconnect-aware cache protection schemes in network-on-chip architectures\, 4) Application-aware memory resiliency for approximate computing era\, and 5) System-level design space exploration\, analysis\, and optimization for redundancy-aware on-chip memory resiliency in many-core platforms. ​  \n In summary\, the premise of this thesis is to provide multiple solutions in different layers of system hierarchy targeting a verity of architectures from embedded single-core microprocessors to emerging large many-core platforms to address cost-efficient error-resiliency of on-chip memory components. \n 
URL:https://www.cecs.uci.edu/event/resilient-on-chip-memory-design-in-the-nano-era/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150416T150000
DTEND;TZID=America/Los_Angeles:20150416T160000
DTSTAMP:20231011T190322Z
CREATED:20231011T190322Z
LAST-MODIFIED:20231011T190322Z
UID:14397-1429196400-1429200000@www.cecs.uci.edu
SUMMARY:Self-stabilizing Java: Tool Support for Building Robust Software
DESCRIPTION:Name: Yong hun EomDate: April 15\, 2015\nTime: 10:00am\nLocation: EH 2430\nCommittee Chair: Professor Demsky\nCommittee members: Prof. Pai Chou and Prof. Rainer Doemer \nTitle: Self-stabilizing Java: Tool Support for Building Robust Software \nAbstract:\nDeveloping robust software systems remains an open research problem. The\ncurrent approaches for improving software reliability mainly focus on\nminimizing the number of software bugs through formal verification or\nextensive testing. Despite such efforts\, it is common that unexpected\nsoftware bugs corrupt a program’s state and cause systems to fail. \nThe motivation for this research is to embrace the fact that it is\ndifficult to guarantee that software is error-free. We present\nSelf-stabilizing Java (SJava) that instead checks that a program\nself-stabilizes. Self-stabilizing programs automatically recover to the\ncorrect state from the corrupted state caused by software bugs and other\nsources. A number of applications are inherently self-stabilizing—such\nprograms typically overwrite all non-constant data with new input data. \nWe have developed a type system and static analyses that together check\nwhether program executions eventually transition from incorrect states\nto the correct state. We combine this with a code-generation strategy\nthat ensures that a program continues executing long enough to\nself-stabilize. Furthermore\, in order to lower the burden of type\nannotations\, we present an annotation inference algorithm that\nautomatically derives an initial set of annotations. \nOur experience using SJava indicates that our system successfully\nchecked that several benchmarks were self-stabilizing and effectively\ninferred annotations for our benchmarks.
URL:https://www.cecs.uci.edu/event/self-stabilizing-java-tool-support-for-building-robust-software/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150304T150000
DTEND;TZID=America/Los_Angeles:20150304T160000
DTSTAMP:20231011T190510Z
CREATED:20231011T190510Z
LAST-MODIFIED:20231011T190510Z
UID:14429-1425481200-1425484800@www.cecs.uci.edu
SUMMARY:Architectural Support for Security in Emerging Platforms
DESCRIPTION:Speaker: Nael Abu-Ghazaleh \nTitle: Architectural Support for Security in Emerging Platforms \nDate: Wednesday\, March 4\, 2015 \nTime: 10:00am \nLocation: Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Fadi Kurdahi \nAbstract:  \nComputer systems are facing a growing threat from increasingly motivated\, organized and sophisticated attackers.  The problem is complicated by the rapid evolution that computing platforms are experiencing towards mobile and embedded devices\, as well as many-core systems\, distributed systems\, virtualization and clouds.  These emerging platforms offer new system and use models and therefore are subject to new vulnerabilities and threat models.  This talk motivates the role that computer architecture must play in securing current and emerging systems.  I will define this role spanning three primary directions: (1) new security models for protecting not only systems but also applications; (2) architecture support for monitoring to improve resilience to attacks\, but also to rapidly detect and contain successful attacks; and (3) Security for emerging architectures.  I will animate each of these directions with examples from our recent work.
URL:https://www.cecs.uci.edu/event/architectural-support-for-security-in-emerging-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150304T150000
DTEND;TZID=America/Los_Angeles:20150304T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14423-1425481200-1425484800@www.cecs.uci.edu
SUMMARY:Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks
DESCRIPTION:Speaker: Francesco Regazzoni \nTitle: Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks \nDate: Tuesday\, March 3\, 2015 \nTime: 2:00pm \nLocation: Donald Bren Hall 3011 \nHost: Nikil Dutt & Rosario Cammarota \nAbstract:  \nPhysical attacks exploit the physical weaknesses of cryptographic devices to reveal the secret information stored on them. Countermeasures against these attacks are often considered only in the later stages of the full design flow\, and applied manually by designers with strong security expertise. This approach\, however\, negatively affects the robustness\, the cost\, and the production time of secure devices. \nIn view of this increasingly relevant problem\, it is crucial to address the design challenges associated with the proliferation of physical attacks\, developing a methodology to automate the design and the verification of secure embedded systems. \nThis talk focuses on one type of physical attacks\, the differential power analysis (DPA)\, and presents the design and the implementation of the infrastructure needed to enable the automatic application and verification of DPA countermeasures.
URL:https://www.cecs.uci.edu/event/towards-the-automatic-application-and-verification-of-countermeasures-against-physical-attacks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150212T150000
DTEND;TZID=America/Los_Angeles:20150212T160000
DTSTAMP:20231011T190458Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190458Z
UID:14419-1423753200-1423756800@www.cecs.uci.edu
SUMMARY:Inertial and Bio-potential-based Wearable Computers: Algorithms and Applications
DESCRIPTION:Title: Inertial and Bio-potential-based Wearable Computers: Algorithms and Applications\nSpeaker:  Professor Roozbeh Jafari \nDate/Time:  Thursday\, February 12\, 2015\, 11:00am to 12:00pm \nLocation:  Donald Bren Hall 4011 \nHost: Eli Bozorgzadeh \nAbstract:  \nWearable computers bring to fruition many new opportunities to continuously monitor human body with sensors placed on body; whether they are intended to detect an early onset of a disease\, assess human performance or determine the effectiveness of a treatment. In the past few years\, the community has observed a large number of applications leveraging wearable computers. There are\, however\, a number of fundamental challenges that need to be addressed before realizing the true ubiquitous use of the wearable computing systems. \nIn the first half of the talk\, we highlight several inertial-based wearable applications including systems capable of monitoring activities of daily living (ADLs) and home exercises for senior citizen. We focus on a class of signal processing algorithms that provide extreme robustness leveraging accelerometers and gyroscopes. We present our results on ADLs and highlight our efforts in line with data dissemination for the scientific community. In the second half of the presentation\, we focus on dry-contact electroencephalography (EEG). We present our brain-computer interface (BCI) system developed for intensive care units leveraging dry-contact EEG. We outline several components of EEG systems and focus on skin-electrode contact noise. \nWe provide techniques for noise reduction including contact reconfiguration along with experimental verifications. We provide concluding remarks on the trends of wearable computing technology development and future directions.
URL:https://www.cecs.uci.edu/event/inertial-and-bio-potential-based-wearable-computers-algorithms-and-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150210T150000
DTEND;TZID=America/Los_Angeles:20150210T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14422-1423580400-1423584000@www.cecs.uci.edu
SUMMARY:Connected Context Computing for Smart IoT
DESCRIPTION:Speaker: Jane Yung-jen Hsu \nTitle: Connected Context Computing for Smart IoT \nDate: Tuesday\, February 10\, 2015 \nTime: 3:30pm \nLocation: Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Professor Kwei-Jay Lin \nAbstract:  \nWe are witnessing the explosion of connected devices\, or the so-called Internet of Things\, in our everyday lives. This new trend has created new opportunities to monitor human activities and to configure environments for comfort\, security\, or energy savings. In the US\, buildings account for roughly 40% of total energy usage\, with major contributions from the cooling demands. While most people have no intention of wasting energy\, they are often unaware of the energy footprint of their daily routines. Activity recognition is a key capability for a smart environment to offer timely services and intelligent interactions with people. \nIn this talk\, I will introduce connected context computing and its significance in enabling our vision of smart IoT. In particular\, I will share our experience on monitoring the Computer Science building on NTU campus to improve its air conditioning and space utilization. First\, an agent-based HVAC service is designed to analyze cooling demands and wastes. Second\, experiments on SweetFeedback are conducted to encourage energy-saving behaviors. Third\, crowd sourcing cyber-physical agents are deployed to acquire status labels for activity recognition from people situated in the environment. Â Our experiments showed that context computing\, predictive analytics\, and proactive control are the fundamental building blocks for a smart IoT framework that can SCALE (Sense\, Communicate\, Analyze\, Learn\, Expect and Effect). \n 
URL:https://www.cecs.uci.edu/event/connected-context-computing-for-smart-iot/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150210T150000
DTEND;TZID=America/Los_Angeles:20150210T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14420-1423580400-1423584000@www.cecs.uci.edu
SUMMARY:Design Automation of Things: Power Consumption Characterization\, Modeling and Estimation of Electric Vehicles
DESCRIPTION:Title: Design Automation of Things: Power Consumption Characterization\, Modeling and Estimation of Electric Vehicles\nSpeaker:  Professor Naehyuck Chang \nDate/Time:  Tuesday\, February 10\, 2015\, 2:00pm to 3:00pm \nLocation:  Harut Barsamian Colloquia Room (EH 2430) \nHost: Nikil Dutt \nAbstract:  \nRapid electric vehicle (EV) penetration gives a threatening challenge in electric energy generation. An 1\,814 kg curb weight full electric vehicle driving 18\,129 km/year consumes electricity energy equivalent to 74% of the total residential electricity use per person in the US. This implies that 27% more nationwide electricity generation is needed when 70% of passenger vehicles are replaced with EVs. \nThis talk introduces the first step toward systematic EV design-time and runtime optimization. We develop instantaneous power consumption modeling of an EV by the curb weights\, speed\, acceleration\, road slope\, passenger and cargo weights\, motor capacity\, and so on\, as a battery discharge model. The model also considers the onboard charger\, regenerative braking and so on\, as a battery charge model. To insure model fidelity\, we fabricate a lightweight custom EV\, perform extensive measurement\, and derive model coefficients using multivariable regression analysis. We estimate the EV instantaneous power consumption of a given speed and route profiles and verify the estimation fidelity with a real test run data. This talk will also cover the on-going project for the next version electric vehicle with four-wheel drive capability. \n 
URL:https://www.cecs.uci.edu/event/design-automation-of-things-power-consumption-characterization-modeling-and-estimation-of-electric-vehicles/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150202T150000
DTEND;TZID=America/Los_Angeles:20150202T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14421-1422889200-1422892800@www.cecs.uci.edu
SUMMARY:Formal Analysis of Electronic System Level Models using Satisfiability Modulo Theories and Automata Checking
DESCRIPTION:Name:  Che-Wei Chang\nDate/Time:  Wednesday\, January 28\,2015\, 9:00am \nLocation:  EH 3404 \nCommittee Chair: Rainer Doemer \nCommittee Member: Daniel Gajski \nCommittee Member: Pai Chou \nAbstract:  \nFor a system-level design which may be composed of multiple processing elements running\n        in parallel\, various kinds of unwanted consequences may happen if the system\n        is constructed carelessly. For example\, deadlock may happen if improper execution\n        order and communication between processing elements is used in the system. Another\n        problem which may be caused by the concurrent execution is race condition\, as\n        shared variables in the system-level model could be accessed by multiple concurrent\n        threads in parallel. Those unwanted behaviors definitely have negative influence on\n        the functionality of the system. Furthermore\, the functionality is not the only concern\n        in system design as timing constraints are critical as well. If the system cannot\n        finish the job within timing constraints\, it is still considered an unwanted design. To\n        address this issue\, we propose two formal analysis approaches in this dissertation to\n        analyze three types of properties we discussed above\, which are\n        1). liveness\,\n        2). satisfiability of timing constraint\, and\n        3). May-Happen-in-Parallel access.\n        These two approaches are based on Satisfiability Modulo Theories (SMT) and UPPAAL\n        automaton model respectively. We run these two approaches on our in-house\n        system models\, including a JPEG encoder\, MP3 decoder\, AMBA AHB and CAN\n        bus protocol models. The experimental results show our approaches are capable of\n        analyzing those properties meeting our expectation within reasonable analysis time.
URL:https://www.cecs.uci.edu/event/formal-analysis-of-electronic-system-level-models-using-satisfiability-modulo-theories-and-automata-checking/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140923T150000
DTEND;TZID=America/Los_Angeles:20140923T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14418-1411484400-1411488000@www.cecs.uci.edu
SUMMARY:Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture
DESCRIPTION:Title:� Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture\nSpeaker:� Francis Caster II \nLocation/Time:� September 23\, 2014\, 3PM\nCommittee Members:\nPayam Heydari\nFilippo Capolino\nH. Kumar Wickramasinghe\nAbstract: Multi-pixel passive imaging arrays are presently fabricated in expensive processes with low integration levels. Imaging arrays designed in inexpensive processes with higher levels of integration would result in cheaper larger arrays. The objective of this work is twofold: 1) to develop a highly integrated silicon-based passive imaging receiver integrating the entire receiver frontend from antenna to detector; and 2) to develop a highly scalable architecture for use in focal plane arrays of arbitrary dimensions\, incorporating new features to address large-array issues while retaining the pixel density of conventional focal plane arrays. A new area-efficient beam-steerable imaging array receiver architecture suitable to integrated circuit realization up to sub-THz frequencies is presented. A direct-detection-based receiver array utilizing the proposed architecture is designed and implemented in an advanced 0.18�m BiCMOS process. The receiver chip achieves a peak measured coherent responsivity of 1\,150MV/W\, a measured incoherent responsivity of 1\,000MV/W\, a minimum NEP of 0.28fW/sqrtHz and a front-end 3-dB bandwidth from 87-108GHz\, while consuming 225mW per receiver element. The measured NETD of the SiGe receiver chip is 0.45K with a 20ms integration time. The proposed architecture uses a new concept of spatial-overlapping super-pixels which results in (1) improved SNR at the pixel level through a reduction of spillover losses\, (2) partially correlated adjacent super-pixels\, (3) a 2�2 window averaging function in the RF domain\, (4) the ability to compensate for the systematic time delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point\, and (5) the ability to compensate for mutual coupling effects among the array elements.
URL:https://www.cecs.uci.edu/event/design-analysis-and-implementation-of-an-area-efficient-beam-steerable-sub-terahertz-imaging-receiver-array-architecture/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140910T150000
DTEND;TZID=America/Los_Angeles:20140910T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14416-1410361200-1410364800@www.cecs.uci.edu
SUMMARY:Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor Platforms
DESCRIPTION:Title:  Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor  Platforms \nSpeaker:  Kyoungwon Kim \nDate/Time:  August 28\, 2014\, 2:oopm \nLocation:  Engineering Hall 3206 \nCommittee Members:Daniel Gajski (Chair)Tony Givargis Rainer Doemer \nAbstract:  Embedded system designers continuously face a twofold challenge handling the ever-increasing complexity of design and meeting the ever-shrinking time-to-market timeline. To meet such a challenge\, the system design paradigm has shifted to platform-based design characterized by intensive use of software and aggressive reuse of verified components. More and more designs are turning to heterogeneous platforms to meet design constraints in multiple criteria. However the use of such and heterogeneity generates more challenges for platform-based design. To address the challenges\, system designers must utilize system-level methodologies for specification and design. Here the designers begin the design process by coming up with a computation model that captures the behavior of the system. The computation model is successively refined down to the structural model in the system level. In each refinement\, the designers explore the design space. The design space comprises a set of alternatives concerning hardware/software partitioning\, platform selection\, and mapping. The design space is huge\, however\, necessitating the automation of its exploration. The platform is very often fixed regarding either availability or legacy reasons\, making mapping crucial. This dissertation focuses on the automatic mapping of the computation model for the given heterogeneous platform. This dissertation presents a new automatic mapping technique based on the input computation model. The proposed technique consists of two separate phases: initial mapping and improvement driven by cycle-approximate estimation. Existing mapping techniques depend on early estimation so a dilemma arises from the fact that cycle-approximate estimation cannot precede mapping. The dilemma can be gotten around by our performing initial mapping based on rough estimation and then making iterative improvements based on cycle-approximate estimation. While earlier work has been domain specific\, the mapping techniques in the proposed work are driven by a general computation model that includes hierarchy\, state transitions\, dynamic data-oriented behaviour\, and imperative languages\, while previous work is domain specific.The proposed work also addresses mapping with an awareness of general hierarchy in pipelined applications. The size of the design space explored is limited by the speed of cycle-approximate estimation. Orders of magnitude faster than Simulation-based cycle-approximate estimation\, the new trace-driven estimation presented in this disseration is cycle-approximate and applicable to both software and hardware. The new trace-driven estimation assumes that the execution path of each task depends on data only. As the trace-driven estimation handles a portion of applications\, it complements the existing simulation-based cycle-approximate estimation. We have applied the proposed mapping techniques to multiple multimedia applications and the techniques outperformed in terms of execution time the competitors by proportions ranging from 23.3% through 36.3%.
URL:https://www.cecs.uci.edu/event/computation-model-based-automatic-design-space-exploration-for-heterogeneous-multiprocessor-platforms/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140910T150000
DTEND;TZID=America/Los_Angeles:20140910T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14417-1410361200-1410364800@www.cecs.uci.edu
SUMMARY:Self-interference Cancellation in Full-duplex Wireless Systems
DESCRIPTION:Title:  Self-Interference Cancellation in Full-duplex Wireless Systems \nSpeaker:  Elsayed Ahmed \nDate/Time:  August 28\, 2014\, 10:00AM \nLocation:  Engineering Hall 4106 \nCommittee Members:Ahmed Eltawil (Chair)Ender AyanogluA. Lee Wsindlehurst \nAbstract: Due to the tremendous increase in wireless data traffic\, one of the major challenges for future wireless systems is the utilization of the available spectrum to achieve better data rates over limited spectrum. Currently\, systems operate in what is termed “Half Duplex Mode\,” where they are either transmitting or receiving\, but never both using the same temporal and spectral resources. Full-duplex transmission promises to double the spectral efficiency where bidirectional communications is carried out over the same temporal and spectral resources. The main limitation impacting full-duplex transmission is managing the strong self-interference signal imposed by the transmit antenna on the receive antenna within the same transceiver. Several recent publications have demonstrated that the key challenge in practical full-duplex systems is un-cancelled self-interference power caused by a combination of hardware imperfections\, especially Radio Frequency (RF) circuits’ impairments. In this thesis\, we consider the problem of self-interference cancellation in full-duplex systems. The ultimate goal of this work is to design and build a complete\, real-time\, full-duplex system that is capable of achieving wireless full-duplex transmission using practical hardware platforms. Since RF circuits’ impairments are shown to have significant impact on the self-interference cancellation performance\, first\, we present a thorough analysis of the effect of RF impairments on the cancellation performance\, with the aim of identifying the main performance limiting factors and bottlenecks. Second\, the thesis proposes several impairments mitigation techniques to improve the overall self-interference cancellation capability by mitigating most of the transceiver RF impairments. In addition to impairments mitigation\, two novel full-duplex transceiver architectures that achieve significant self-interference cancellation performance are proposed. The performance of the proposed techniques is analytically and experimentally investigated in practical wireless environments. Finally\, the proposed self-interference cancellation techniques are used to build a complete full-duplex system with a 90% experimentally proven full-duplex rate improvement compared to half-duplex systems.
URL:https://www.cecs.uci.edu/event/self-interference-cancellation-in-full-duplex-wireless-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140723T150000
DTEND;TZID=America/Los_Angeles:20140723T160000
DTSTAMP:20231011T190437Z
CREATED:20231011T190437Z
LAST-MODIFIED:20231011T190437Z
UID:14414-1406127600-1406131200@www.cecs.uci.edu
SUMMARY:New Circuit Techniques Enabling Millimeter-Wave and Terahertz Transceivers in Nonoscale Silicon
DESCRIPTION:Title:  New Circuit Techniques Enabling Millimeter-Wave and Terahertz Transceivers in Nonoscale Silicon \nSpeaker:  Zheng Wang \nDate/Time:  Monday\, June 2\, 2014\, 2:00PM \nLocation:  Engineering Hall 2111 \nCommittee Members:Payam Heydari (Chair)Michael GreenEnder Ayaloglu \nAbstract: The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device _fT_/_fmax_\, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. This dissertation mainly focuses on the design of a 210GHz fundamental transceiver and also covers the design of a W-band fully integrated imaging system utilizing a novel concept of spatial-overlapping super pixels.Firstly\, a 210GHz transceiver with OOK modulation in a 32nm SOI CMOS process is presented. The transmitter (TX) employs a 2´2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillator (VCO) at 210GHz with an on-off-keying (OOK) modulator\, a power amplifier (PA) driver\, a novel balun-based differential power distribution network\, four PAs and an on-chip 2´2 dipole antenna array. The non-coherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna\, a low noise amplifier (LNA)\, and a power detector. The VCO generates measured -13.5dBm output power; and the PA shows a measured 15dB gain and 4.6dBm Psat. The LNA exhibits a measured in-band gain of 18dB and minimum in-band noise figure (NF) of 11dB. The TX achieves an EIRP of 5.13dBm at 10dB back-off from saturated power. It achieves an estimated EIRP of 15.2dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200GHz frequency range. \nSecondly\, a W-band direct-detection-based receiver array in an advanced 0.18µm BiCMOS process is presented\, which incorporates a new concept of spatial-overlapping super-pixels for millimeter-wave imaging\napplications. The use of spatial-overlapping super-pixels results in (1) improved SNR at the pixel level through a reduction of spillover losses\, (2) partially correlated adjacent super-pixels\, (3) a 2×2 window\naveraging function in the RF domain\, (4) the ability to compensate for the systematic phase delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point\, and (5)\nthe ability to compensate for mutual coupling effects among the array elements. The receiver chip achieves a measured peak coherent responsivity of 1\,150MV/W\, an incoherent responsivity of 1\,000MV/W\, a\nminimum noise-equivalent power (NEP) of 0.28fW/√Hz and a front-end 3-dB bandwidth from 87-108GHz\, while consuming 225mW per receiver element. The measured noise-equivalent temperature difference (NETD) of the SiGe\nreceiver chip is 0.45K with a 20ms integration time.\n\n 
URL:https://www.cecs.uci.edu/event/new-circuit-techniques-enabling-millimeter-wave-and-terahertz-transceivers-in-nonoscale-silicon/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140723T150000
DTEND;TZID=America/Los_Angeles:20140723T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14413-1406127600-1406131200@www.cecs.uci.edu
SUMMARY:Performance-Optimized Terahertz Signal Sources in Silicon
DESCRIPTION:Title:  Performance-Optimized Terahertz Signal Sources in Silicon \nSpeaker:  Pei-Yuan Chiang \nDate/Time:  Monday\, June 2\, 2014\, 10:00AM \nLocation: Engineering Hall 2111 \nCommittee Members:Payam Heydari (Chair)Michael GreenOzdal Boyraz \nAbstract: Terahertz (THz) and sub-millimeter wave band are known to provide unique applications in spectroscopy\, imaging and high-data-rate wireless communication. An imaging system operating in this frequency region exhibits non-invasive and high-resolution characteristics due to the non-ionized and short-wavelength radiation waves\, which makes it attracting for security surveillance. On the other hand\, the THz wireless transceiver operating in the license-free spectrum is capable of achieving tens of gigabits-per-second by utilizing a simple modulation scheme. All the benefits mentioned above make THz a promising research topic. Towards realization of a high-performance THz system\, one of the most challenging steps is to design a frequency synthesizer. \nA voltage-controlled oscillator (VCO) is one of the important building blocks within a synthesizer. Due to the server performance degradation of varactors and transistors at high frequencies\, new ways of designing VCOs need to be investigated. Here\, two different ideas are proposed. First\, an inductive-tuning mechanism with high quality-factor and wide tuning-range is introduced. This tuning technique is based on a variable inductor seen at the emitter terminal of a base-degenerated transistor. By adding a series RL at the base terminal\, the variable inductor\, exhibiting low loss and high tunability\, improves the VCO output power and phase noise while achieving a wide tuning range. The second idea\, double-stacked cross-coupled VCO\, is to design a strong negative resistance cell to compensate for the server loss of the varactor at THz frequencies. By implementing a source-degenerated negative resistor of a conventional cross-coupled pair\, the overall negative resistance is enhanced. It also reduces the parasitic capacitance\, making it an attracting approach for THz applications. \nFinally\, a novel THz frequency synthesizer is proposed. A 300GHz phase-locked-based synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a three-phase injection locked divider is introduced. The CAV is used to tune the oscillation frequency\, enhance output power\, and buffer the VCO’s fundamental signal. The divider’s locking-range is vastly increased attribute to the three-phase injection. This work demonstrates the highest-frequency synthesizer in silicon.
URL:https://www.cecs.uci.edu/event/performance-optimized-terahertz-signal-sources-in-silicon/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140712T150000
DTEND;TZID=America/Los_Angeles:20140712T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14415-1405177200-1405180800@www.cecs.uci.edu
SUMMARY:New Perspectives on Designing An Effective Management Policy for Multi-level Cache Hierarchy
DESCRIPTION:Date/Time:  February 25\, 2014\, 3:00PM \nLocation:  DBH 3011 \nCommittee Members:Alexander V. Veidenbaum (Chair)Alexandru NicolauTony GivargisRainer Doemer \nAbstract: Designing an effective cache management policy for a multi-level cache hierarchy has been a hot research topic to bridge the gap between the fast microprocessor and the long memory latency. It is becoming critically important in modern microprocessors due to the emerge of new hardware architectures\, new technologies and new applications. However\, it has been shown that this is not an easy task due to the complexity of the inputs that computer architects must take into account. \nThe bottom-up approach has been used in designing such a policy. Rather than tackling the problem with all the possible inputs\, a management policy is broken down into smaller problems\, each targeting a smaller number of inputs. Sub-policies\, such as replacement\, bypass\, migration and partitioning\, are studied for a specific event or configuration. Solutions have been proposed for these individual policies or their combinations. In either case\, the new policies must be shown to work well with existing baseline policies. \nIn this dissertation\, using the bottom-up approach\, we propose new management policies for a multi-level cache hierarchy. Using new ideas about an effective policy or improving existing methods for new hardware architectures\, we further optimize the current state-of-the-art policies. Specifically\, we propose three new sets of management policies. First\, new migration policies are proposed for an L0/L1 cache hierarchy for embedded processors. We propose two new cache designs to enhance operations of the L1 caches. Second\, we propose a new combined replacement\, bypass and partitioning policy for a last-level cache by achieving the balance between cache reuse and pollution. The new policy is shown to reduce pollution due to keeping cache lines too long in the cache\, a problem which was not addressed by prior work. And third\, we propose a new coordinated bypass policy for a multi-level cache hierarchy using the new classifications of cache lines and their reuse probabilities. This policy works well with any existing policies and architectures which allow bypass. \nThe new cache management policies are shown to improve existing policies or optimize the design with an acceptable performance loss. They are shown to work well with the baseline policies. We also present hardware architectures and application classes that each new policy will be applied to. Hardware design is also described and is shown to be feasible and have low overhead.
URL:https://www.cecs.uci.edu/event/new-perspectives-on-designing-an-effective-management-policy-for-multi-level-cache-hierarchy/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130827T150000
DTEND;TZID=America/Los_Angeles:20130827T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14412-1377615600-1377619200@www.cecs.uci.edu
SUMMARY:Cognitive Power Management and Error Resilient Algorithms for Memory Dominated Wireless Communication Systems
DESCRIPTION:Date/Time:  Friday\, August 23\, 2013 \nLocation:  Engineering Hall 4106 \nCommittee Members:Ahmed Eltawil (Chair)Fadi KurdahiA. Lee Swindlehurst \nAbstract: \nAdvanced CMOS technology exhibits increasing variations in performance\, power consumption and reliability parameters. These variations led to extensive overdesigning and increased power consumption to guarantee 100% reliable operation. However\, with the continuous shrinking of device parameters\, future semiconductor industry needs to shift from the assumption of 100% reliable computation to a fault-tolerant approach. Fortunately\, many important application domains such as communication and multimedia are inherently error-aware\, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. Specifically\, embedded memories in communication systems are perfect candidates for exploring error-aware designs\, since the share of the System-on-Chips (SoCs) that is dedicated to memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoCs for wireless standards such as Long-Term Evolution (LTE)\, Digital Video Broadcasting (DVB)\,  and Worldwide Interoperability for Microwave Access (WiMAX). Furthermore\, a large portion of the memory is typically used for buffering data that already has a high level of redundancy (e.g. buffering memories in wireless chips). In the context of wireless communication systems\, given that the incoming buffered data is already corrupted by time varying noise and interference\, there is no need to store the data samples in memories that are error free\, 100% of the time. Rather\, Voltage over-scaling (VoS) techniques can be adopted as an efficient means to achieve energy efficient systems via trading off reliability versus power.  However\, reducing the supply voltage of buffering memory through VoS results in spatially uniform random errors which in turn corrupt the stored data in the buffering memories and increase the noise floor. \nIn this thesis\, the predominance of embedded memories in current and emerging wireless transceivers is utilized as a means to save power via channel state aware voltage scaling. While the wireless channel is a stochastic channel where the designer has little control on its variables\, embedded memories are considered as an extension of the channel where the designer can control its quality via VoS. The thesis presents a unified statistical model that captures both errors in embedded memories due to voltage over-scaling and wireless channel impairments into a single Gaussian distribution model that represents a combination of communication channel noise and hardware noise. The proposed model is used to investigate different cognitive power management policies that capture the performance of the system as a function of both channel and hardware dynamics\, thus creating a much richer design space of power\, performance and reliability. Furthermore\, based on that model\, error-resilient algorithm for Viterbi decoder\, multiple input multiple output (MIMO) detector and memory-based computation are presented.
URL:https://www.cecs.uci.edu/event/cognitive-power-management-and-error-resilient-algorithms-for-memory-dominated-wireless-communication-systems/
CATEGORIES:PhD Defenses
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