BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CECS
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20140309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20141102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20150308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20151101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20160313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20161106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161114T150000
DTEND;TZID=America/Los_Angeles:20161114T160000
DTSTAMP:20231011T190617Z
CREATED:20231011T190617Z
LAST-MODIFIED:20231011T190617Z
UID:14475-1479135600-1479139200@www.cecs.uci.edu
SUMMARY:Resource Aggregation for Collaborative Projected Video from Multiple Mobile Devices
DESCRIPTION:Name: Hung Nguyen\nDate: November 17\, 2016 \nTime: 1:30 P.M. \nLocation: EH 3206 \nCommittee: Fadi Kurdahi (Chair)\, Aditi Majumder (Co-Chair) \nAbstract:  \nWe explore and develop an embedded real time system and associated algorithms that enable an aggregation of limited resource\, low-quality\, projection-enabled mobile devices to collaboratively produce a higher quality video stream for a superior viewing experience. Such a resource aggregation across multiple projector enabled devices can lead to a per unit resource savings while moving the cost to the aggregate. \nThe pico-projectors that are embedded in mobile devices such as cell phones have a much lower resolution and brightness than standard projectors. Tiling (putting the projection area of multiple projectors in a rectangular array overlapping them slightly around the boundary) and superimposing (putting the projection area of multiple projectors right on top of each other) multiples of such projectors\, registered via automated registration through the cameras residing within those mobile devices\, result in different ways of aggregating resources across these multiple devices. Evaluation of our proof-of-concept system shows significant improvement for each mobile device in two primary factors of bandwidth usage and power consumption when using a collaborative federation of projection-embedded mobile devices. \nThe portable\, low-power\, light weight\, small size pico-projectors are key components of projection-enabled mobile devices for the future. Due to the reduction of weight and dimension and the portability nature of the projector-enabled mobile devices\, the calibrated integrated systems are prone to physical un-stabilizing of the projected image during the presentation. Thus the auto re-calibration and projected video stabilization features during the presentation time becomes essential requirements to enhance user experience. The design\, algorithm\, and implementation methods for these features will be presented in the second part of the dissertation.
URL:https://www.cecs.uci.edu/event/resource-aggregation-for-collaborative-projected-video-from-multiple-mobile-devices/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161107T150000
DTEND;TZID=America/Los_Angeles:20161107T160000
DTSTAMP:20231011T190616Z
CREATED:20231011T190616Z
LAST-MODIFIED:20231011T190616Z
UID:14472-1478530800-1478534400@www.cecs.uci.edu
SUMMARY:Low Energy\, a New Trend for Lightweight Cryptography
DESCRIPTION:Title: “Low Energy\, a New Trend for Lightweight Cryptography”\nSpeaker: Dr. Francesco Regazzoni\, ALaRI Institute of Università della Svizzera italiana\, Lugano\, Switzerland \nDate and Time:  Wednesday\, February 1\, 2017 at 11:00 a.m. \nLocation: DBH 4011 \nHost: Prof. Nikil Dutt \nAbstract: In the last decade\, several lightweight block ciphers and hash functions have been proposed. One of the metrics\, so far largely unexplored\, which has to be used to identify a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers\, this operation is the encryption of one plaintext. \nThis talk will address several approaches for reducing the energy consumption of existing block ciphers\, touching the design space of the AES algorithm\, to which few algorithmic optimizations are applied. \nThe gained experience lead to the design of Midori\, the first block cipher designed to optimize the energy consumed per bit in encryption or decryption operation. Each component of the circuit\, as well as its entire architecture of the cipher\, have been optimized for energy\, and design choices leading to low energy consumption in an electrical circuit were taken. Achieved results demonstrate that the energy consumption of Midori64 and Midori128 is much lower that current stateof the art.\n \nBiography: Dr. Francesco Regazzoni is a senior researcher at the the ALaRI Institute of Universita’ della Svizzera italiana (Lugano\, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at the ALaRI Institute of Universita’ della Svizzera italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft\, and visiting researcher at several institutions\, including NEC Labs America\, Ruhr University of Bochum\, EPFL\, and NTU Singapore. His research interests are mainly focused on embedded systems security\, covering in particular side channel attacks\, electronic design automation for security\, hardware Trojans\, low energy cryptography\, and post quantum security. He has published more than 70 journal and conference papers in the area of security and design automation\, and has been in the technical program committed of top conferences of the area. Francesco is the principal investigator and project leader at Universita’ della Svizzera italiana of the projects (SAFECrypto\, exploring lattice-based constructions as building blocks for quantum resistant cryptography)\, and CERBERO (design tools for Cyber-Physical Systems). \nView Details Here
URL:https://www.cecs.uci.edu/event/low-energy-a-new-trend-for-lightweight-cryptography/
CATEGORIES:Seminars at CECS
ATTACH;FMTTYPE=image/png:https://cecs.uci.edu/files/2023/10/francescoreg-seminar-YBo8Ni.tmp_.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161107T150000
DTEND;TZID=America/Los_Angeles:20161107T160000
DTSTAMP:20231011T190615Z
CREATED:20231011T190615Z
LAST-MODIFIED:20231011T190615Z
UID:14470-1478530800-1478534400@www.cecs.uci.edu
SUMMARY:Prof. Mohammad A. Al Faruque receives Thomas Edison Patent Award 2016
DESCRIPTION:The Edison Patent Awards at Liberty Science Center in Jersey City. 11/3/16 Photo by John O’Boyle \nEach year the Research & Development Council of New Jersey honors the winners of the Thomas Edison Patent Awards at its annual Edison Patent Awards Ceremony & Reception in the IMAX Theater of the Liberty Science Center. Professor Al Faruque was selected as the recipient for this prestigious award for his patent in energy management in Electric Vehicle (EV) charging stations. \nThe patent\, “Network as automation platform for collaborative E-car charging at the residential premises” has provided a novel solution to solve this challenge through a  collaborative energy management strategy for the Electric Vehicle (EV) charging stations located in a residential neighborhood. The amount of energy that can be provided to the EVs connected to a single  neighboring step down transformer is limited by the connected circuit breaker at a certain point of time.  This energy management strategy will collaborate among all the EVs\, maximize the number of charged EVs and preferably reduce the local energy peaks  to the medium and low voltage electric infrastructure. \n 
URL:https://www.cecs.uci.edu/event/prof-mohammad-a-al-faruque-receives-thomas-edison-patent-award-2016/
CATEGORIES:Awards
ATTACH;FMTTYPE=image/jpeg:https://cecs.uci.edu/files/2023/10/AlFaruqueEdisonAwards-129-ZY2dba.tmp_.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161105T150000
DTEND;TZID=America/Los_Angeles:20161105T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14480-1478358000-1478361600@www.cecs.uci.edu
SUMMARY:High Level Synthesis - Some Challenging Problems
DESCRIPTION:Title: “High Level Synthesis – Some Challenging Problems”\nSpeaker: George A. Constantinides\, Imperial College London\, UK \nDate and Time: Wednesday\, November 16\, 2016 at 11:00 A.M. \nLocation: Engineering Hall 2430 \nHost: Professor Nikil Dutt \nAbstract: High Level Synthesis – synthesis of circuits from behavioral descriptions – is a long-standing problem\, but one that appears to now have come to age. Both the demand for\, and the supply of\, quality HLS tools is now in place. However\, there are still some hard problems to be overcome in order to make HLS fully general. My research focuses on two of these: customization of memory systems to algorithms\, and customization of number representation to algorithms. After briefly introducing the work at Imperial – and encouraging PhD and postdoc applications (!) – I will spend a little time on each of these problems. In particular\, I will look at the problem of customization of memory for heap manipulating programs\, the potential of parametric analysis for synthesis of lightweight run-time scheduling changes\, and automates code refactoring for rigorously controlled accuracy / latency / area optimization. I hope to inspire the audience to consider how you may be able to contribute to these problems. \nBiography: Prof George A. Constantinides holds the Royal Academy of Engineering / Imagination Technologies Chair in Digital Computation at Imperial College London\, where he leads the Circuits and Systems research group. He has been a member of staff at Imperial since 2001. Over this time he has been the proud supervisor of 25 graduated PhD students and chaired the FPGA\, FPT\, and FPL conferences. He enjoys hard problems and espresso. \nView more here
URL:https://www.cecs.uci.edu/event/high-level-synthesis-some-challenging-problems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161105T150000
DTEND;TZID=America/Los_Angeles:20161105T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14478-1478358000-1478361600@www.cecs.uci.edu
SUMMARY:Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow
DESCRIPTION:Title:  “Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow”\nSpeaker: Christian Krieg\, Vienna University of Technology\, Vienna\, Austria \nDate and Time: Thursday\, November 17\, 2016 at 2:00 PM \nLocation: Donald Bren Hall 3011 \nHost:  Professor Nikil Dutt \nAbstract: We present a novel type of Trojan trigger targeted at the field-programmable gate array (FPGA) design flow. Traditional triggers base on rare events\, such as rare values or sequences. While in most cases these trigger circuits are able to hide a Trojan attack\, exhaustive functional simulation and testing will reveal the Trojan due to violation of the specification. Our trigger behaves functionally and formally equivalent to the hardware description language (HDL) specification throughout the entire FPGA design flow\, until the design is written by the place-and-route tool as bitstream configuration file. From then\, Trojan payload is always on. We implement the trigger signal using a 4-input lookup table (LUT)\, each of the inputs connecting to the same signal. This lets us directly address the least significant bit (LSB) and most significant bit (MSB) of the LUT. With the remaining 14 bits\, we realize a “magic” unary operation. This way\, we are able to implement 16 different Triggers. We demonstrate the attack with a simple example and discuss the effectiveness of the recent detection techniques unused circuit identification (UCI)\, functional analysis for nearly-unused circuit identification (FANCI) and VeriTrust in order to reveal our trigger. \nBiography: Christian Krieg received the bachelor’s and master’s degree in electrical engineering from TU Wien and is now pursuing his PhD studies on hardware security at TU Wien. His research focuses on design-level hardware Trojan design and detection. He also works on reasonable threat models for hardware Trojan attacks. Christian recently received the William McCalla best paper award for a novel hardware Trojan implementation. At a wider scope\, Christian’s research interests include cyber-physical systems security and IoT security. \nView Details
URL:https://www.cecs.uci.edu/event/malicious-lut-a-stealthy-fpga-trojan-injected-and-triggered-by-the-design-flow/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161104T150000
DTEND;TZID=America/Los_Angeles:20161104T160000
DTSTAMP:20231011T190622Z
CREATED:20231011T190622Z
LAST-MODIFIED:20231011T190622Z
UID:14477-1478271600-1478275200@www.cecs.uci.edu
SUMMARY:Adaptive Design: Tackling Variability Challenges in VLSI Circuits
DESCRIPTION:Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”\nSpeaker: Professor Mingoo Seok\, Columbia University\, New York \nDate:  Friday\, April 22\, 2016 \nTime:  3:00PM \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Prof. Payam Heydari \nAbstract: In this talk\, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage\, chip temperature\, manufacturing process\, and transistor aging have imposed a large amount of pessimistic margins in clock frequency\, voltage\, and device size\, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead\, in-situ\, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage\, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing\, (3) self-testing circuits and frameworks for in-field & in-situ aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented. \nBio: \nMingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University\, South Korea\, in 2005\, and the MS and PhD degree from University of Michigan in 2007 and 2011\, respectively\, all in electrical engineering. He was a member of technical staff in Texas Instruments\, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems\, including ultra-low-power computing systems\, computing systems for machine learning\, adaptive circuits and architecture\, and non-conventional computing systems. \nHe received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies\, 2005 Doctoral Fellowship from the same organization\, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013\, and IEEE Transactions on VLSI Systems since 2015.
URL:https://www.cecs.uci.edu/event/adaptive-design-tackling-variability-challenges-in-vlsi-circuits/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161004T150000
DTEND;TZID=America/Los_Angeles:20161004T160000
DTSTAMP:20231011T190615Z
CREATED:20231011T190615Z
LAST-MODIFIED:20231011T190615Z
UID:14469-1475593200-1475596800@www.cecs.uci.edu
SUMMARY:Specification and Runtime Verification of Distributed Multiprocessor Systems: Languages\, Tools and Architectures
DESCRIPTION:Name: Ahmed Nassar\nDate: September 2\, 2016 \nTime: 12:00 P.M. \nLocation: EH 3403 \nCommittee: Fadi Kurdahi (Chair)\, Rainer Doemer\, Ahmed Eltawil \nAbstract: Post-Deployment runtime verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification and testing methods. This thesis is an attempt to tackle three major barriers that need to be surmounted before RV technologies become in widespread use:\nBarrier-1: Lack of an expressive\, yet efficiently monitorable\, specification language. Distributed software behavior is projected onto an observation interface consisting of data-carrying (or parameterized) events\, such as Linux system calls including argument values\, and self-replicating deterministic finite automata (SR-DFAs) are introduced for RV purposes as well as anomaly-based intrusion detection in embedded and general-purpose software systems based on these parametric traces.\nBarrier-2: The substantial performance and power overhead of pure software RV frameworks. NUVA\, which stands for nonuniform verification architecture\, a distributed automata-based RV architecture for software specifications in the form of SR-DFAs. NUVA has been implemented over a cache-coherent nonuniform-memory-access (ccNUMA) multiprocessor and can be deployed on the FPGA fabric that will reside on all next-generation processor chips. The core of NUVA is a coherent distributed automata transactional memory (ATM) that efficiently maintains states of a dynamic population of automata checkers organized into a rooted dynamic directed acyclic graph (DAG) concurrently shared among all processor nodes.\nBarrier-3: Formal specifications are hard to formulate and maintain for evolving complex embedded and general-purpose software systems. Therefore\, specification mining has long ago been envisioned to play a key role in software verification\, modification and documentation. However\, in order to scale beyond simple\, library/API-level properties having short temporal spans\, specification mining tools need to support more expressive specification languages that can capture complex\, application-level properties. This thesis introduces a bio-inspired complete specification mining methodology for SR-DFAs using an iterative and interactive mining tool\, called ParaMiner. ParaMiner relies on novel mining algorithms invoking multiple-sequence alignment (MSA) techniques to enable learning specifications from temporal slices of software behavior while overcoming the initial-state uncertainty problem.\nSR-DFAs and ParaMiner have been leveraged in a new specification-based intrusion detection (ID) framework that protects distributed\, reactive computing systems against cyberattacks having very sparse signatures\, arbitrarily long time spans and wide attack fronts. Such attacks lie outside the scope of conventional anomaly-based ID methods which typically work with short event windows and ignore manipulated data objects\, such as files and sockets. We demonstrate the effectiveness of the constructed SR-DFAs at classifying as well as resolving subtle behaviors typical of cyberattacks with varying evasion parameter values.
URL:https://www.cecs.uci.edu/event/specification-and-runtime-verification-of-distributed-multiprocessor-systems-languages-tools-and-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190612Z
CREATED:20231011T190612Z
LAST-MODIFIED:20231011T190612Z
UID:14466-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Resilience is a Critical Issue for Large-scale Platform
DESCRIPTION:Speaker:  Prof. Yves Robert\, Ecole Normale Supérieure de Lyon\, France \nTitle:  Resilience is a Critical Issue for Large-scale Platform \nDate:  Monday\, May 18\, 2015 \nTime:  11:00 a.m. – 12:00 p.m. \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost:  Prof. Jean-Luc Gaudiot \nAbstract: Resilience is a critical issue for large-scale platforms. This talk will survey fault-tolerant techniques for high-performance computing:\n– Overview of failure types and typical probability distributions\n– Brief discussion of application-specific techniques\, such as ABFT\n– The standard general-purpose technique\, checkpoint and     rollback recovery\n– Recent extensions with replication\, prediction and silent error detection\n– Relevant execution scenarios\, evaluated and compared through quantitative models.\nThe talk includes several illustrative examples and targets a general audience. \nBio: Yves Robert received his PhD degree from Institut National Polytechnique de Grenoble. He is currently a full professor in the Computer Science Laboratory LIP at ENS Lyon. He is the author of 7 books\, 130+ papers published in international journals\, and 200+ papers published in international conferences.  He is the editor of 11 book proceedings and 13 journal special issues.  He is the advisor of 28 PhD theses.  His main research interests are scheduling techniques and resilient algorithms for large-scale platforms. Yves Robert served on many editorial boards\, including IEEE TPDS.  He was the program chair of HiPC’2006 in Bangalore\, IPDPS’2008 in Miami\, ISPDC’2009 in Lisbon\, ICPP’2013 in Lyon and HiPC’2013 in Bangalore. He is a Fellow of the IEEE. He has been elected a Senior Member of Institut Universitaire de France in 2007 and renewed in 2012.  He has been awarded the 2014 IEEE TCSC Award for Excellence in Scalable Computing.  He holds a Visiting Scientist position at the University of Tennessee\, Knoxville since 2011. \n  \n 
URL:https://www.cecs.uci.edu/event/resilience-is-a-critical-issue-for-large-scale-platform/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190612Z
CREATED:20231011T190612Z
LAST-MODIFIED:20231011T190612Z
UID:14467-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Hardware Security in the Zynq All-Programmable Soc
DESCRIPTION:Title: “Hardware Security in the Zynq All-Programmable Soc”\nSpeaker: Dr. Steve Trimberger\, Xilinx \nDate:  Friday\, October 2\, 2015 \nTime:  2:00 p.m. \nLocation:  Donald Bren Hall 4011 \nHost: Prof. Fadi J. Kurdahi \nAbstract: FPGAs have grown from a simple logic replacement to fully-programmable SoC\, with multi-core CPU subsystems\, a broad spectrum of peripherals\, hundreds of thousands of gates of programmable logic and high-speed multi-gigabit transceivers. As the complexity of the underlying hardware has grown\, so has the value of the applications built in them and the data handled by them. Traditional FPGA bitstream security has been enhanced to address these greater security requirements. This talk presents an overview of hardware security issues and the security features of the Zynq All- Programmable SoC. The secure boot process includes asymmetric and symmetric authentication as well as symmetric encryption to protect software and programmable hardware during programming.During operation the hardware can disable test ports\, monitor on-chip power and temperature and detect tampering with configuration data. ARM Trust Zone is integrated through the AXI busses into both the processor and the programmable logic subsystems. \nBio: Dr. Stephen Trimberger holds a M.S. degree in ICS from UCI and a Ph.D. degree from California Institute of Technology. Since 1988\, he has been employed at Xilinx\, where he is currently Xilinx Fellow heading the Circuits and Architectures Group in Xilinx Research Labs in San Jose\, California. He was the technical leader for the XC4000 design automation software\, developed a dynamically -reconfigurable multi-context FPGA\, led the architecture definition group for the Xilinx XC4000X device families and designed the Xilinx bitstream security functions in the Virtex families of FPGAs. He led the group that developed the first die- stacked 3D FPGA prototype at Xilinx. He has served as Design Methods Chair for the Design Automation Conference\, Program Chair and General Chair for the ACM/SIGDA FPGA Symposium and on the technical programs of numerous Workshops and Symposia. He has authored five books and dozens of papers on design automation\, FPGA architectures and hardware security. He has more than 220 patents in IC design\, FPGA and ASIC architecture\, CAE\, hardware security and cryptography. His innovations appear today in nearly all commercial FPGA devices. He is a Fellow of the ACM and a Fellow of the IEEE. \nView Details Here \n 
URL:https://www.cecs.uci.edu/event/hardware-security-in-the-zynq-all-programmable-soc/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190611Z
CREATED:20231011T190611Z
LAST-MODIFIED:20231011T190611Z
UID:14464-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:CMOS Process Variations: A “Critical Operation Point” Hypothesis
DESCRIPTION:Title: CMOS Process Variations: A “Critical Operation Point” Hypothesis\nSpeaker: Dr. Janak H. Patel \nDate: May 2\, 2012 \nTime: 3:30-4:30 P.M. \nLocation: DBH 3011 \nHost: Professor Nikil Dutt \n 
URL:https://www.cecs.uci.edu/event/cmos-process-variations-a-critical-operation-point-hypothesis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190611Z
CREATED:20231011T190611Z
LAST-MODIFIED:20231011T190611Z
UID:14465-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:IEEE Solid-State Circuits Society Webinar
DESCRIPTION:“Fundamentals of Millimeter-Wave Frequency Generation and Synthesis in Silicon”\, Presented by Payam Heydari \nThis webinar is free and open to all SSCS members. \nTue\, May 31\, 2016 9:00 AM – 10:30 AM PDT \n 
URL:https://www.cecs.uci.edu/event/ieee-solid-state-circuits-society-webinar/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14461-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Addressing Supply Chain Security with Split Manufacturing
DESCRIPTION:Speaker: Dr. Ted Huffmire\, Naval Postgraduate School\, Monterey\, CATitle: Addressing Supply Chain Security with Split Manufacturing\nDate: July 27\, 2012\nTime:11:00am\nLocation: Donald Bren Hall 3011\nCECS Host: Prof. Nikil Dutt \nAbstract: Security is an essential design goal in computer architecture\, and security is a concern throughout the entire lifecycle of a system. The process of designing hardware requires trusting intellectual property (IP) cores and computer-aided design (CAD) tools developed by third parties\, as well as the fabrication\, packaging\, assembly\, and delivery of the final system. Valuable IP is vulnerable to theft and modification during tape-out\, even if a perfect design free of security flaws is sent to the foundry. Of course\, no design is ever perfect\, and having a trusted foundry does not solve the problem of flawed designs. Furthermore\, the trusted foundry may not have the capability to deliver the most aggressive technology node\, volume\, yield\, or cost. Even the extraordinary step of building everything from scratch in-house\, including all of the tool chains\, both digital and analog\, is not guaranteed to result in a trustworthy design. \nBio: Ted Huffmire is an Assistant Professor of Computer Science at the Naval Postgraduate School in Monterey\, California. His research spans both computer security and computer architecture\, focusing on hardware-oriented security and the development of policy enforcement mechanisms for application-specific devices. He has a Ph.D. in computer science from the University of California\, Santa Barbara. He is a member of the IEEE and the ACM. The views presented in this talk are those of the speaker and do not necessarily reflect the views of the United States Department of Defense. \nView Details Here
URL:https://www.cecs.uci.edu/event/addressing-supply-chain-security-with-split-manufacturing-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14462-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:The Confluence of Communications\, Sensing and Control in Large Scale Wireless Networks
DESCRIPTION:Speaker:  Prof. Urbashi Mitra\, Electrical Engineering\, University of Southern California\nTitle:  The Confluence of Communications\, Sensing and Control in Large Scale Wireless Networks \nDate:  Friday\, November 8\, 2013 \nTime:  11:00am – 12:00pm\n \nLocation:  Donald Bren Hall 6011 \nAbstract: Modern wireless technology enables the vision of future large scale systems such as the SmartGrid\, a network of ubiquitous and heterogeneous devices wirelessly connected to the Internet\, and wireless health monitoring and health modifying sensor networks over communities and not just individuals.  All of these applications necessitate methods that simultaneously consider scale\, communication\, sensing and control. In this talk\, key elements of realizing this vision are examined.  We shall focus on novel active control methods for networks described by partially observable Markov decision processes.  Such models are very general and can encompass sensing networks\, as well as communication networks.  Following an innovations approach\, a Kalman-like filter is derived to estimate the underlying system state.  As a case-study\, numerical results are provided for physical activity detection in a heterogeneous wireless body area network.  We further examine distributed estimation in large scale networks with time-correlated behavior and explore how modern statistical methods such as compressed sensing can be applied to both the distributed estimation problem as well as the network control problem. \nBio: Urbashi Mitra received the B.S. and the M.S. degrees from the University of California at Berkeley and her Ph.D. from Princeton University.   She is currently a Professor in the Ming Hsieh Department of Electrical Engineering at the University of Southern California.  She is a member of the IEEE Information Theory Society’s Board of Governors (2002-2007\, 2012-2014) and the IEEE Signal Processing Society’s Technical Committee on Signal Processing for Communications and Networks (2012-2014). She is the recipient of:  2012 Globecom Signal Processing for Communications Symposium Best Paper Award\, 2012 NAE Lillian Gilbreth Lectureship\, USC Center for Excellence in Research Fellowship (2010-2013)\, the 2009 DCOSS Applications & Systems Best Paper Award\, IEEE Fellow (2007)\, Texas Instruments Visiting Professor (Fall 2002\, Rice University)\, 2001 Okawa Foundation Award\, 2000 OSU College of Engineering Lumley Award for Research\, and a 1996 NSF CAREER Award.  Dr. Mitra has been/is an Associate Editor for the following IEEE publications: Transactions on Signal Processing (2012–)\, Transactions on Information Theory (2007-2011)\, Journal of Oceanic Engineering (2006-2011)\, and Transactions on Communications (1996-2001).  Dr. Mitra has held visiting appointments at: the Delft University of Technology\, Stanford University\, Rice University\, and the Eurecom Institute. She served as co-Director of the Communication Sciences Institute at the University of Southern California from 2004-2007.  Her research interests are in: wireless communications\, communication and sensor networks\, detection and estimation and the interface of communication\, sensing and control.
URL:https://www.cecs.uci.edu/event/the-confluence-of-communications-sensing-and-control-in-large-scale-wireless-networks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14463-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:A Client-centric Approach to Interoperable Clouds
DESCRIPTION:Speaker: Mukesh Singhal\, Department of Computer Science\, University of California\, Merced\nTitle: A Client-centric Approach to Interoperable Clouds \nDate: Friday\, December 6\, 2013 \nTime: 11:00am – 12:00pm \nLocation: Donald Bren Hall 6011 \nAbstract: Cloud computing offers several benefits in terms of scalability\, cost and performance. These benefits have contributed to the wide-scale acceptance of the cloud computing paradigm and growing adoption by the industry. With this growth\, limitations of this paradigm are beginning to surface. One such limitation is that contemporary clouds are not interoperable. This limitation arises due to proprietary technologies\, heterogeneous interfaces and the tight tethering of service offerings to the host cloud. Current research solutions for enabling cloud interoperability are predominantly provider-centric\, requiring cloud providers to adopt and implement the changes that facilitate interoperation. This approach faces several hurdles and can take a long time to hit the market. In the meantime\, a client-centric approach to interoperation is necessary for providing its benefits to consumers in the current cloud ecosystem. To this end\, a novel framework for cloud interoperation called collaborative cloud computing is proposed. The proposed framework provides dynamic\, on-the-fly collaborations and resource sharing among cloud-based services\, without pre-established collaboration agreements or standardized interfaces\, through use of client-controlled mediating agents called proxies. \nBio: Mukesh Singhal is a Chancellor’s Professor in the Computer Science and Engineering program at the University of California\, Merced. He received a PhD degree in Computer Science from the University of Maryland\, College Park\, in May 1986. From 1986 to 2001\, he was a faculty in the department of Computer and Information Science at The Ohio State University. From 1998 to 2001\, he served as the program director of the Operating Systems and Compilers program at the National Science Foundation. From 2001 to 2012\, he was a Professor and Gartner Group endowed chair in Network Engineering in the Department of Computer Science at The University of Kentucky. His current research interests include distributed and cloud computing\, cyber-security\, and computer networks. He has published over 240 refereed articles in these areas. He is a Fellow of IEEE and he was a recipient of 2003 IEEE Technical Achievement Award. He has coauthored four books titled “Advanced Concepts in Operating Systems”\, McGraw-Hill\, New York\, 1994\, “Distributed Computing Systems”\, Cambridge University Press 2007\, “Data and Computer Communications: Networking and Internetworking”\, CRC Press\, 2001\, and “Readings in Distributed Computing Systems”\, IEEE Computer Society Press\, 1993. He has served in the editorial board of “IEEE Trans. on Dependable and Secure Computing”\, “IEEE Trans. on Parallel and Distributed Systems”\, “IEEE Trans. on Data and Knowledge Engineering”\, and “”IEEE Trans. on Computers”. \n 
URL:https://www.cecs.uci.edu/event/a-client-centric-approach-to-interoperable-clouds/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190554Z
LAST-MODIFIED:20231011T190555Z
UID:14451-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Circuits and Systems Seminar Series
DESCRIPTION:Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”\nSpeaker: Prof Mingoo Seok\, Columbia University\, New York\, NY \nDate and Time: Friday\, April 22\, 2016 at 3:00 P.M. – 4:00 P.M. \nLocation: Engineering Hall 2430 \nHosts: Professor Payam Heydari \nAbstract: In this talk\, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage\, chip temperature\, manufacturing process\, and transistor aging have imposed a large amount of pessimistic margins in clock frequency\, voltage\, and device size\, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead\, in-sit\, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage\, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing\, (3) self-testing circuits and frameworks for in-field & in-sit aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented. \nBio: Mingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University\, South Korea\, in 2005\, and the MS and PhD degree from University of Michigan in 2007 and 2011\, respectively\, all in electrical engineering. He was a member of technical staff in Texas Instruments\, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems\, including ultra-low-power computing systems\, computing systems for machine learning\, adaptive circuits and architecture\, and non-conventional computing systems. He received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies\, 2005 Doctoral Fellowship from the same organization\, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013\, and IEEE Transactions on VLSI Systems since 2015. \nView Details Here
URL:https://www.cecs.uci.edu/event/circuits-and-systems-seminar-series/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190553Z
LAST-MODIFIED:20231011T190555Z
UID:14450-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:CECS Hosts IWCR 2016
DESCRIPTION:View details here
URL:https://www.cecs.uci.edu/event/cecs-hosts-iwcr-2016/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160929T150000
DTEND;TZID=America/Los_Angeles:20160929T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14391-1475161200-1475164800@www.cecs.uci.edu
SUMMARY:Building Fake Body Parts: Real-Time Digital Mockups of Physiological Systems
DESCRIPTION:Title:  Building Fake Body Parts: Real-Time Digital Mockups of Physiological SystemsSpeaker: Prof. Frank Vahid\, University of California\, Riverside\nLocation: 6011 Donald Bren Hall\nDate/Time: Friday\, October 26\, 2012\, 11:00am – 12:00pm\nHost: Prof. Eli Bozorgzadeh \nAbstract: Designing computer-based medical devices like pacemakers or ventilators is hard\, in part because testing can’t be done on real humans. PC-based simulations are slow and inaccurate. Using physical mockups\, like connecting a ventilator device to a balloon acting as a lung\, can’t support sufficiently diverse scenarios\, like fluid in the lungs. This talk describes joint UCR/UCI work on developing “digital mockups” — models of physiological systems that execute in real-time\, supporting thorough testing of device software. We show that FPGAs (field-programmable gate arrays) — widely-available programmable chips having a unique execution approach that we’ll describe — are an excellent match for executing physiological models\, yielding order-of-magnitude speedups over PCs\, GPUs\, and other computing approaches. The talk describes the synthesis approach to automatically converting models\, consisting of thousands of differential equations\, into networks of processing elements on FPGAs. Real-time execution of physiological models can also be useful in building complete human simulators\, used today medical and nursing schools. More broadly\, real-time execution of physical systems (chemical\, biological\, mechanical\, physiological\, etc.) can be useful in the design of a wide variety of what today are called cyber-physical systems– systems where computers interact closely with the physical world – including automobiles\, aircraft\, medical equipment\, military equipment\, manufacturing systems\, and much more. \nBio: Frank Vahid is a Professor of Computer Science and Engineering at the University of California\, Riverside (B.S. 1988 Univ. of Illinois in 1988\, M.S./Ph.D. 1990/1994 Univ.of California\, Irvine. He is author of several textbooks on embedded systems and digital design. His current research interests include creating technologies for cyber-physical systems (http://www.cs.ucr.edu/~vahid/digitalmockups/)\, developing customizable assistive monitoring systems for home-alone aging/disabled persons and their caretakers http://www.cs.ucr.edu/~vahid/assistivemonitoring/\, and creating the next generation of online interactive animated learning material (http://pcpp.zyante.com).\nView Details Here
URL:https://www.cecs.uci.edu/event/building-fake-body-parts-real-time-digital-mockups-of-physiological-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160928T150000
DTEND;TZID=America/Los_Angeles:20160928T160000
DTSTAMP:20231011T190616Z
CREATED:20231011T190616Z
LAST-MODIFIED:20231011T190616Z
UID:14471-1475074800-1475078400@www.cecs.uci.edu
SUMMARY:Distinguished Lecture at CECS
DESCRIPTION:Speaker: Prof. Massimo Poncino\, Polytechnic University of Turin\, Italy\nTitle: Towards Computer-Aided Design of Electrical Energy Systems:Challenges and Solutions\nDate: Friday\, April 22\, 2016\nTime: 11:00am – 12:00pm\nLocation: Engineering Hall 2430 \nHost: Prof. Mohammad Al Faruque \n\nView Details Here
URL:https://www.cecs.uci.edu/event/distinguished-lecture-at-cecs-2/
CATEGORIES:Other Events
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160818T150000
DTEND;TZID=America/Los_Angeles:20160818T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190553Z
LAST-MODIFIED:20231011T190555Z
UID:14449-1471532400-1471536000@www.cecs.uci.edu
SUMMARY:PhD Defense:
DESCRIPTION:Name:  Aras Pirbadian\nDate: August 29\, 2016 \nTime: 3:30pm \nLocation:  EH 3403 \nCommittee: Ahmed Eltawil (Chair)\, Fadi Kurdahi\, Rainer Doemer \nWith the continued scaling of chip manufacturing technologies\, the significance of process variation in performance of the systems is increasing. Specifically\, process variation results in growing voltage and frequency overhead margins required to ensure error free operation of circuits. However\, the traditional practice of overdesigning the systems to cover process variation is no longer an efficient design methodology in an age with high demands for processing power and limited energy supplies. In this dissertation\, a novel analytical model is proposed to predict the required margin accurately in the early stages of design space exploration. The model can be used to optimize the system overhead in error free calculations or to release the bound by full correctness in error tolerant parts of systems and optimize the energy vs. performance trade-off. Additionally\, this model also considers the statistics of the inputs of the circuit as compared to other existing efforts enabling it to achieve close predictions of full circuit simulation results in a short time. This model is finally used in an adaptive carry select/ripple carry adder configuration to demonstrate the potential achievable power savings. \nGrowing variation in newer technology nodes is not always a negative side effect. The increased inherent randomness in the process manufacturing technology can be utilized to develop unique physically unclonable functions (PUFs). These functions are irreproducible hardware-based authenticating systems\, which do not require memory-based storage. A low overhead delay-based PUF using the variation of the silicon manufacturing is also proposed in the second part of this work. The proposed PUF uses a simple and efficient structure to convert the randomness of the manufacturing process into random responses to fixed challenges in identically designed circuits.
URL:https://www.cecs.uci.edu/event/phd-defense/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160804T150000
DTEND;TZID=America/Los_Angeles:20160804T160000
DTSTAMP:20231011T190537Z
CREATED:20231011T190537Z
LAST-MODIFIED:20231011T190537Z
UID:14448-1470322800-1470326400@www.cecs.uci.edu
SUMMARY:Progression and Edge Intelligence Framework for IoT Systems
DESCRIPTION:Name:  Zhenqiu Huang\nDate: July 29\, 2016 \nTime: 10:00am \nLocation:  EH 4106 \nCommittee: Kwei-Jay Lin (Chair)\, Fadi Kurdahi\, Mohammad Al Faruque \nAbstract: This thesis studies the issues on building and managing future Internet of Things (IoT)\nsystems. IoT systems consist of distributed components with services for sensing\, processing\,\nand controlling through devices deployed in our living environment as part of the global\ncyber-physical ecosystem. \nSystems with perpetually running IoT devices may use a lot of energy. One challenge is to\nimplement good management policies for energy saving. In addition\, a large scale of devices\nmay be deployed in wide geographical areas through low bandwidth wireless communication\nnetworks. This brings the challenge of con
URL:https://www.cecs.uci.edu/event/progression-and-edge-intelligence-framework-for-iot-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160715T150000
DTEND;TZID=America/Los_Angeles:20160715T160000
DTSTAMP:20231011T190537Z
CREATED:20231011T190537Z
LAST-MODIFIED:20231011T190537Z
UID:14447-1468594800-1468598400@www.cecs.uci.edu
SUMMARY:Area/speed tradeoffs in a retargetable FPGA-optimized processor core
DESCRIPTION:Speaker:  Marco Zec\, University of Zagreb \nTitle:  “Area/speed tradeoffs in a retargetable FPGA-optimized processor core” \nDate:  Friday\, July 15\, 2016 \nTime:  11:00 AM \nLocation:  CECS Conference Room (Engineering Hall 3206) \nHost:  Prof. Daniel Gajski \nAbstract: Can portable yet efficient\, FPGA-optimized processor cores be constructed using generic HDL\, without depending on any vendor-specific primitives?  In this talk we will discuss the techniques applied for achieving a balance between instruction throughput and FPGA resource utilization in a synthesizable scalar core which outperforms its proprietary counterparts (MicroBlaze\, Nios\, Cortex-M3) by 20% to 40% in industry-standard integer benchmarks (CoreMark\, Dhrystone per MHz) while\noccupying less than 1000 6-input LUTs\, and less than 650 LUTs in an area-optimized configuration.  The core can be retargeted to execute subsets of either the emerging RISC-V or the traditional MIPS instruction sets\, and is supported by contemporary GNU-based software toolchains.\n \nBio: Marko Zec received a BSc in electrical engineering from the University of Zagreb\, where since 2005. he has been working as a project scientist on various computer networks projects with funding from ICSI Berkeley\, the FreeBSD foundation\, Boeing Integrated Defense Systems\, and Ericsson. His research interests include operating systems\, computer networks\, software-based packet processing datapaths\, and programmable logic. \nView Details
URL:https://www.cecs.uci.edu/event/area-speed-tradeoffs-in-a-retargetable-fpga-optimized-processor-core/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160422T150000
DTEND;TZID=America/Los_Angeles:20160422T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190554Z
LAST-MODIFIED:20231011T190555Z
UID:14452-1461337200-1461340800@www.cecs.uci.edu
SUMMARY:"Towards Computer-Aided Design of Electrical Energy Systems: Challenges and Solutions"
DESCRIPTION:Title: “Towards Computer-Aided Design of Electrical Energy Systems: Challenges and Solutions”\nSpeaker: Professor Massimo Poncino\, Polytechnic University of Turin\, Italy \nDate and Time: Friday\, April 22\, 2016 at 11:00 A.M. – 12:00 P.M. \nLocation: Engineering Hall 2430 \nHosts: Professor Mohammad Al Faruque \nAbstract: Electrical energy systems (EESs) include energy generation\, distribution\, storage\, and consumption\, and involve many diverse components and sub-systems to implement these tasks. In this talk we discuss fundamental concepts towards a first attempt in applying EDA design methodologies that are widely used for electronics systems design to the case of the design of EESs. CAD for EESs encompasses modeling\, simulation\, design and optimization and is a challenging task that mandates a multidisciplinary and heterogeneous approach. We identify similarities and differences between electrical energy systems and electronics systems in order to inherit as much as possible the profound legacy resources of EDA. The talk analyzes in deeper details the issue of representation\, modeling\, and simulation of EESs\, tasks that naturally precede synthesis and optimization in a typical design flow.\n\n\n\n\n\nBio: Massimo Poncino is Full Professor of Computing Systems at Politecnico di Torino. Prior to that\,\nhe was an Associate Professor (from 2004 to 2006) at Politecnico di Torino\, Associate Professor (from 2001 to 2004) at Università di Verona\, and Assistant Professor (from 1995 to 2001) at Politecnico di Torino. From 1993 to 1994 he was a Visiting Scientist at the Department of Electrical and Computer Engineering of the University of Colorado\, Boulder\, USA. He holds a Dr. Eng. degree in Electrical Engineering (1989) and a PhD degree in Computer Engineering\, both from Politecnico di Torino (1993).His research interests include the design automation of digital systems\, with emphasis on low\n-power embedded systems\, modeling and the simulation of systems -on- chip\, and automatic synthesis of digital systems. He has coauthored more than 300 publications in the above areas\, including one book on energy -efficient memory design. Massimo Poncino has served as member of Technical Program Committee of more than 50 IEEE and ACM conferences. He was the Technical Program Chair of the 2011 IEEE/ACM Symposium on Low-Power Electronics and Design and General co-Chair for the same conference in 2012. He has served in the Editorial Board of the IEEE Transactions on CAD from 2006 to 2011\, and is currently serving in the Editorial Board of IEEE Design & Test and ACM Transactions on Design Automation of Electronic Systems (TODAES). Prof. Poncino is a Senior Member of IEEE\, member of the ACM SIGDA Low -Power Technical Committee\, and a Member the Circuit and Systems Society.\n\nView Details Here
URL:https://www.cecs.uci.edu/event/towards-computer-aided-design-of-electrical-energy-systems-challenges-and-solutions/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160404T150000
DTEND;TZID=America/Los_Angeles:20160404T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14446-1459782000-1459785600@www.cecs.uci.edu
SUMMARY:Frameworks and Algorithms for Wearable Medical Applications
DESCRIPTION:Name:  SeungJae Lee\nDate:  April\, 5\, 2016 \nTime:  3:00p.m. \nLocation:  EH 4106 \nCommittee:  Pai H. Chou (Chair)\, Fadi Kurdahi\, Tony Givargis \nAbstract: \nWearable embedded systems with sensing\, communication\, and computing capabilities have given rise to innovations in e-health and telemedicine in general. The scope of such systems ranges from devices and mobile apps to cloud backend and analysis algorithms\, all of which must be well integrated. To manage the development\, operation\, and evolution of such complex systems\, a framework systematic framework is needed. This dissertation makes contributions in two parts. First is a framework for defining the structure of a wide range of wearable medical applications with modern cloud support. The second part includes several algorithms that can be plugged into this framework for making these systems more efficient in terms of processing performance and data size. We propose a novel QT analysis algorithm that can take advantage of GPU as well as in a server-client environment\, and we show competitive results in terms of both performance and energy consumption with or without parallelization. We also propose ECG compression techniques using trained overcomplete dictionary. After constructing the dictionary through learning process with a given dataset\, the signal can be compressed by sparse estimation using the trained dictionary. We propose reconstructing ECG signal from undersampled data based on compressive sensing framework that can reconstruct the ECG signals precisely from fewer samples so long as the signal is sparse or compressible. Together\, these algorithms operating in the context of our proposed framework validate the effectiveness of our structured approach to the framework for wearable medical application. \n 
URL:https://www.cecs.uci.edu/event/frameworks-and-algorithms-for-wearable-medical-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160404T150000
DTEND;TZID=America/Los_Angeles:20160404T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14445-1459782000-1459785600@www.cecs.uci.edu
SUMMARY:Power Optimization for Medical Sensing Systems
DESCRIPTION:Name:  Jun Luan\nLocation:  EH 4106 \nDate: February 24\, 2016 \nTime: 1:00pm \nCommittee: Pai Chou (Chair)\, Mohammad Al Faruque\, Fadi Kurdahi \nAbstract:  \nMedical sensing systems collect and analyze the patients’ physiological data for monitoring\, aid or diagnostic purposes. System designers are faced with stringent requirements on not only correctness and safety but also power. Reference designs and multi-purpose platforms help to significantly shorten the development cycle. \nThis work takes a cross-layer\, system-level\, platform-based approach to addressing the problem of saving power in a class of portable medical system. We propose a low-power medical sensing system that can be used to monitor Electrocardiography (ECG)\, Photo- plethysmogram (PPG)\, and muscle tension. It also includes a hand gesture recognition system to aid mobility-impaired patients. \nWe explore the theory and application of a compressive sensing framework to medical signal processing. A novel compressive sensing-based ECG compression algorithm and a dominant frequency extraction-based PPG heart-rate calculation algorithm are proposed to reduce the system power. The unique combination of hardware structure and software signal-processing algorithms makes low-power design possible. The system test results show that the proposed system is superior to existing works in terms of power consumption and system size.
URL:https://www.cecs.uci.edu/event/power-optimization-for-medical-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160218T150000
DTEND;TZID=America/Los_Angeles:20160218T160000
DTSTAMP:20231011T190555Z
CREATED:20231011T190554Z
LAST-MODIFIED:20231011T190555Z
UID:14453-1455807600-1455811200@www.cecs.uci.edu
SUMMARY:Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes
DESCRIPTION:Title: “Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes”\nSpeaker: Professor Khaled N. Salama\, King Abdullah\, University of Science and Technology\, Saudi Arabia \nDate and Time: Thursday\, February 18\, 2016 at 11:00 A.M. \nLocation: Engineering Hall 2430 \nHosts: Fadi J. Kurdahi and Ahmed Eltawil \nAbstract: Energy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. However\, the capacitive sensor readout circuit—i.e.\, the capacitance-to-digital converter (CDC) —can be the dominant source of energy consumption in the system. Thus\, the development of energy-efficient CDC architectures is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this talk\, we propose several energy -efficient CDC architectures for low-energy sensor nodes. In the second part\, we study the matching properties of small integrated capacitors\, which are an integral component of energy-efficient CDCs. Despite conventional wisdom\, we experimentally illustrate that the mismatch of small capacitors can be directly measured\, and we report experimental mismatch measurements for sub-femtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors\, and we identify the conditions that make one implementation preferable. \nBio: Dr. Salama received his bachelor’s degree with honors from the Electronics and Communications Department at Cairo University in Egypt in 1997\, and his master’s and doctorate degrees from the Electrical Engineering Department at Stanford University in the United States\, in 2000 and 2005 respectively. He was an assistant professor at RPI between 2005 and 2008. He joined King Abdullah University of science and technology (KAUST) in January 2009 and was the electrical engineering founding program chair till August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford-Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc in 2008. He is the cofounder of ultrawave labs\, a biomedical imaging company that was recently acquired. He is the co-author of 90 papers and 10 patents on low-power mixed-signal circuits for intelligent fully integrated sensors and non linear electronics specially memristor devices. He is a senior member of IEEE. \nView Details Here
URL:https://www.cecs.uci.edu/event/energy-efficient-capacitance-to-digital-converters-for-low-energy-sensor-nodes/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20160208T150000
DTEND;TZID=America/Los_Angeles:20160208T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14459-1454943600-1454947200@www.cecs.uci.edu
SUMMARY:Mitigating BTI-induced Device Degradation: A Circuit and System Persepctive
DESCRIPTION:Title: Mitigating BTI-induced Device Degradation: A Circuit and System Persepctive\nSpeaker: Professor Ing-Chao Lin\, National Cheng Kung University\, Taiwan \nDate and Time: Monday\, February 8\, 2016 at 1:30 P.M. \nLocation: Donald Bren Hall 3011 \nHost: Professor Nikil Dutt \nAbstract: Bias temperature instability which causes a shift in the transistor’s threshold voltage and decreases circuit switching speed has become a major reliability concern. In this talk\, I will introduce the techniques to mitigate device degradation at the circuit and system level\, and provide design guidelines to deal with device degradation. The future trend on device degradation will be introduced as well. \nBiography: Prof. Ing‐Chao Lin received his M.S. degree from Dept. of Computer Science and Information Engineering\, National Taiwan University and Ph.D. degree from Dept. of Computer Science and Engineering\, the Pennsylvania State University 2001 and 2007\, respectively. From 2007 to 2009\, he is a staff R&D engineer in Real Intent Inc.\, CA\, USA\, where he is working on Real Intent’s automatic timing exception verifier. His research interest includes reliable power‐aware system\, electronic design automation\, and computer architecture. He has authored or co‐authored more than 50 scientific papers and is a committee member of many technical conferences. He is a senior member of IEEE and he is thechair of IEEE Tainan Young Professional group. He is the recipient of 2015 Excellent Young Researcher Award by Chinese Institute of Electrical Engineering. He is currently a visiting scholar in Dept. of Electrical and Computer Engineering\, University of California\, Santa Barbara. \n  \nView more details here \n 
URL:https://www.cecs.uci.edu/event/mitigating-bti-induced-device-degradation-a-circuit-and-system-persepctive/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20151110T150000
DTEND;TZID=America/Los_Angeles:20151110T160000
DTSTAMP:20231011T190612Z
CREATED:20231011T190612Z
LAST-MODIFIED:20231011T190612Z
UID:14468-1447167600-1447171200@www.cecs.uci.edu
SUMMARY:Mobile Technology Enabling Frictionless HealthCare
DESCRIPTION:Title: “Mobile Technology Enabling Frictionless HealthCare”\nSpeaker: Aiman Abdel-Malek\, Vice President\, Engineering\, Qualcomm Life\, Founder & CEO\, Frictionless Life Analytics \nDate:  Tuesday\, November 10\, 2015 \nTime:  3:00 p.m. \nLocation:  Engineering Hall 2430 \nHost: Prof. Fadi J. Kurdahi \nAbstract: With Smart mobile devices being the fastest growing consumer platform in history\, it is becoming a huge enabler to new business models that reduce friction in daily life. Aiman will introduce how mobile technology is creating solutions to many of the current healthcare issues and enabling moving care from the hospital to the home. \nBio: Aiman joined Qualcomm Life from General Electric’s Healthcare Division in Sept 2012\, where he served as GM and CTO for the Global Services Technology business\, a $5 billion division of GE healthcare. There he led a global engineering team responsible for the development of software and systems platforms for predictive remote service technology and healthcare operational efficiency and quality applications. Aiman served GE for 25 years; 10 years in R&D helping the development of GE’s first digital x-ray mammography system and digital Ultrasound system. He then moved to GE Transportation to start and manage the first Satellite wireless-based Locomotive Remote Predictive Services business\, which currently runs on over 20\,000 locomotives. Afterward\, he took an expat assignment in the United Kingdom\, as technology managing director for the Pipeline Inspection Services\, a $400 million global business unit of GE Oil and Gas. Aiman’s technical expertise is in the development of vision inspired signal processing algorithms for aerospace\, industrial and medical applications. He earned his PhD in Systems & Biomedical engineering from the University of Southern California\, completing post-doctoral research at UCLA in neurology. He is a senior member of the IEEE and holds over 22 US and international patents. He serves as a member of the Scientific Advisory Board for the Qualcomm-Xprize Tricorder competition. Also\, he served on GE’s Corporate Software Board\, and as an executive leader for the Image & Signal Processing Technology Council for GE Healthcare. Aiman recently founded his own company\, which aims at helping guide California startups & ventures move from “concept” to “scale” in most frictionless path. He is also a Board Advisor to few startups. \nView Details Here\n 
URL:https://www.cecs.uci.edu/event/mobile-technology-enabling-frictionless-healthcare/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150924T150000
DTEND;TZID=America/Los_Angeles:20150924T160000
DTSTAMP:20231011T190600Z
CREATED:20231011T190600Z
LAST-MODIFIED:20231011T190600Z
UID:14460-1443106800-1443110400@www.cecs.uci.edu
SUMMARY:When Lyapunov meets Church\, automated synthesis of complex systems emerges
DESCRIPTION:Title: When Lyapunov meets Church\, automated synthesis of complex systems emerges\nSpeaker: Prof. Majid Zamani\, Technische Universität München\, Germany \nDate: Thursday\, September 24\, 2015 \nTime: 3:30 p.m. \nLocation: Engineering Colloquia Room 2430 \nHost: Faryar Jabbari and Solmaz S. Kia \nAbstract: Software plays a crucial role in many everyday applications. Modern vehicles and\nairplanes\, for instance\, use interacting software and hardware components to control steering\, fuel in\njection\, and airbag deployment. These applications are examples of cyber-­‐physical systems (CPS)\, where software components interact tightly with physical systems. Recent advances in device manufacturing\, computation\, storage\, and networking have made tremendous advances in hardware and systems platforms for CPS. However\, the development of core software controllers that run on these systems is still ad hoc and error-­‐prone. Many CPS applications are safety-­‐critical\, and much of the engineering costs today are consumed with ensuring that software works correctly. In this talk\, I will proposes a transformative design process\, in which the controller code is automatically synthesized from higher-­‐level correctness requirements. Requirements for modern CPS applications go beyond conventional requirements in control theory (stability\, synchronization\, and tracking) and\nbeyond traditional protocol design in computer science. Accordingly\, I will propose unified methodologies for automatic controller synthesis by combining techniques from discrete systems theory from computer science with continuous dynamical systems from control theory. The proposed automated synthesis of correct-­‐by-­‐ construction controllers holds the potential to develop complex yet reliable CPS applications while considerably reducing verification and validation costs.\n\n\nBio: Majid Zamani is an assistant professor in the Department of Electrical and \nComputer Engineering at Technische Universität München where he leads the Hybrid Control Systems Group. He received a Ph.D. degree in Electrical Engineering and an MA degree in Mathematics both from University of California\, Los Angeles in 2012\, an M.Sc. degree in Electrical Engineering from Sharif University of Technology in 2007\, and a B.Sc. degree in Electrical Engineering from Isfahan University of Technology in 2005. From September 2012 to December 2013\, he was a postdoctoral researcher in the Delft Centre for Systems and Control at Delft University of Technology. Between December 2013 and May 2014\, he was an assistant professor at Delft University of Technology.nd RSS). He is the Editor-­‐in-­‐Chief of the Springer journal Autonomous Robots.\n\n\nView Details Here
URL:https://www.cecs.uci.edu/event/when-lyapunov-meets-church-automated-synthesis-of-complex-systems-emerges/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150729T150000
DTEND;TZID=America/Los_Angeles:20150729T160000
DTSTAMP:20231011T190536Z
CREATED:20231011T190536Z
LAST-MODIFIED:20231011T190536Z
UID:14444-1438182000-1438185600@www.cecs.uci.edu
SUMMARY:A Centralized IoT Middleware System for Devices Working Across Application Domains Using Self-descriptive Capability Profile
DESCRIPTION:Name: Chengjia Huo\nLocation: EH 4404 \nDate: September 30\, 2015 \nTime: 1pm \nCommittee: Pai H. Chou (chair)\, Phillip Sheu\, Rainer Doemer \nAbstract: \nThe Internet of Things (IoT) has been receiving growing attention in recent years as the next wave of computing revolution made possible by all types of networks of things (NoTs)\, where devices powered with low-cost\, miniature low-power systems-on-chip (SoC) with computing and communication capabilities\, and are bridged to the Internet with the assistance of gateways. More and more NoT device are designed to provide more than one functionalities to fulfill different requirements from the application domains. We believe that the true power of IoT is that functionalities of devices can work across application domains. In order to reveal the potential of IoT\, the description of a device’s capability needs to represent the functionalities that the device can provide. We discover the previous solutions on describing a device’s capability focus mainly on hiding the vendor-specific interfaces made by different manufacturers\, but they do not reflect different functionalities that a device provides. In this thesis\, the concept of device capability profile is proposed. Different from the previous solutions\, the device capability profile specified in the firmware of a device allows the device to work across different application domains. Together with device capability profile\, a centralized IoT middleware framework\, called rimware\, is proposed. Rimware tracks every device’s capability and state in a centralized manner and provides different ways for application domains to query against the device’s functionalities. In addition\, rimware utilizes the device capability profile to carry out the enforcement of the security and privacy throughout the communication with the devices. Moreover\, tasks can be scheduled through the rimware which enables functionalities from multiple devices to work together to fulfill the requirements from application domains. Optimization is applied on cases that one device working for multiple task simultaneously. An implementation of rimware that is specifically designed for BLE devices\, called BlueRim\, which takes advantages of BLE’s very long battery life on the device side and the cloud functionality on the centralized side is provided. The fundamental features of rimware have been validated in several real-world applications from different different domains while incurring minimal code size and communication overhead on BLE devices. We believe that our approach represents an important technology in taking IoT closer to realizing the full potentials.
URL:https://www.cecs.uci.edu/event/a-centralized-iot-middleware-system-for-devices-working-across-application-domains-using-self-descriptive-capability-profile/
CATEGORIES:PhD Defenses
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150729T150000
DTEND;TZID=America/Los_Angeles:20150729T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14438-1438182000-1438185600@www.cecs.uci.edu
SUMMARY:Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems
DESCRIPTION:Speaker:  Prof. Muhammad Mustafa Hussain\, King Abdullah University of Science and Technology (KAUST) \nTitle:  “Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems” \nDate:  Tuesday\, April 21\, 2015 \nTime:  2:00 PM \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost:  Prof. Fadi Kurdahi \nAbstract: Our research is focused on heterogeneous electronic materials and high-performance complementary metal oxide semiconductor (CMOS) based tunable shape-size-conformity wearable interactive electronics and systems for smart living (computation-communication-infotainment) through internet of everything and a sustainable future (healthcare-water-food-environment-security). For scientific exploration\, we make collective use of the materials\, processes and device architecture leveraging multidisciplinary tracks of material science\, bioengineering\, mechanical\, environmental engineering and computer science. As engineering tool\, we use CMOS technology extensively due to its industrial relevance\, maturity and reliability for rapid tech transfer.\nTo bridge between the high-performance state-of-the-art electronics and emerging soft-materials based flexible-stretchable electronics. we have developed various generic batch processes using CMOS technologies to transform any already processed Integrated Circuitry (IC) or arrays of devices to be fabricated on virgin substrates (thin film based\, examples include but not limited to: silicon\, silicon germanium\, indium phosphide\, gallium arsenide\, etc.) into flexible and stretchable one [ACS Nano 2014\, pss-RRL 2014]. These processes are cost effective ($1.25/cm2)\, non-abrasive and retain high-performance\, energy-efficiency\, ultra-large-scale-integration density as obtained in today’s state-of-the-art electronics. Often the transformed fabrics (ultra-thin version of the bulk thin film substrates with pre-fabricated devices) are semi-transparent due to the presence of the process originated vertical channels. As per ITRS 2014 metrics\, the processes are fully scalable down to 2 nm technology node. Using these techniques we have demonstrated high-κ/metal gate based planar and non-planar nano-scale (sub-20 nm) CMOS logic devices [Adv. Mater. 2014 (cover page)\, ACS Nano 2014\, APL 2013\, pss-RRL 2013 (cover pages)\, IEEE TED 2013\, pss-RRL 2013\, Sci. Rep. 2013\, pss-RRL 2013]\, memory [Adv. Electronic Mater. 2015\, Microelect. Engr. 2014]\, micro-scale thermoelectric generators [Small 2013 (frontispiece)]\, micro lithium ion batteries (150 μAh/cm2 normalized capacity)\, MEMS devices [MEMS 2014]\, smart thermal patch using copper stretched up to 800% [Adv. Healthcare Mater. 2015 (frontispiece)]\, mono-crystalline silicon stretched up to 1000% [APL 2014]. Variety of device demonstrations on wide range of inorganic thin films using this technique proves the efficiency and versatility of it. Our research greatly complements the $150M Flexible Hybrid Electronics Manufacturing Initiative (FHEMII) – recently introduced by the US Department of Defense: “Highly tailorable devices on flexible\, stretchable substrates that combined thinned CMOS components with components that are added via printing process”.\n \nView Details
URL:https://www.cecs.uci.edu/event/flexible-stretchable-reconfigurable-cmos-electronics-through-hybrid-integration-of-heterogeneous-materials-for-wearable-interactive-electronic-systems/
CATEGORIES:Seminars at CECS
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