BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CECS
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20160313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20161106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20190310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20191103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180719T150000
DTEND;TZID=America/Los_Angeles:20180719T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190806Z
LAST-MODIFIED:20231011T190813Z
UID:14535-1532012400-1532016000@www.cecs.uci.edu
SUMMARY:"Efficient Processing when Intelligence Moves to the Edge"
DESCRIPTION:Name: Tinoosh Mohsenin\nDate and Time: Friday\, July 20 at 10:00 a.m. – 11:00 a.m. \nLocation: Donald Bren Hall 4011 \nAbstract:  \n\nContinuous collection and processing of vast amounts of data is becoming more common with the advancement of wearable sensors\, Internet of Things (IoT) devices and cyber physical systems. Despite their potential significant impact\, intelligent mobile technologies face a number of challenges for use in daily life. These devices usually stream raw data to cloud computers for computation which leads to massive storage\, significant transmission power consumption\, real time constraints and privacy/security issues\, thus processing at the edge of sensors is becoming increasingly preferred. Processing these sensor-level data requires a variety of signal processing and machine learning tasks that come at the cost of high computational complexity and memory storage which is overwhelming for these light weight and battery constrained platforms. \nIn this talk I will present research solutions that enable efficient processing of machine learning tasks to improve energy efficiency and throughout without sacrificing application accuracy for wide deployment of embedded/edge processing. First\, I present DeepMatter a scalable framework across algorithms\, architectures and hardware to design an embedded Deep Neural Net (DNN) accelerator. DeepMatter takes any number of raw sensor data for variety of applications and classifies the events within 92% accuracy and consumes very low power. Next I present two programmable domain-specific manycore accelerators namely PENC and BinMACthat achieve energy and speed efficiencies comparable to application-specific custom hardware through data-level and task level parallelization as well as customization of instruction-sets per-core and near-memory computing. I will show the efficiency of DeepMatter as well as PENC and BinMAC solutions for several application domains including multi-physiological processing for seizure and stress monitoring\, tongue drive assistive device\, air quality monitoring andvision-based situational awareness. The solutions derived at the intersection of algorithms\, architectures and implementation allow designers to rapidly prototype and deploy the next generation of sophisticated and intelligent systems for efficient edge processing in extreme environments. \n\nBiography: \nTinoosh Mohsenin is an Assistant Professor in the Department of Computer Science and Electrical Engineering at University of Maryland Baltimore County\, where she directs Energy Efficient High Performance Computing (EEHPC) Lab. She received her PhD from University of California\, Davis in 2010 and M.S. degree from Rice University in 2004\, both in Electrical and Computer Engineering. Prof. Mohsenin’s research focus is on designing highly accurate and energy efficient embedded processors for machine learning\, signal processing and knowledge extraction techniques for autonomous systems\, wearable smart health monitoring\, and embedded big data computing. She has over 80 peer-reviewed journal and conference publications and is the recipient of NSF CAREER award in 2017\, the best paper award in the GLSVLSI conference in 2016\, and the best paper honorable award in ISCAS 2017 for developing domain-specific accelerators for biomedical\, deep learning and cognitive computing. She currently leads 8 research projects in her lab which are all funded by National Science Foundation (NSF)\, Army Research Lab (ARL)\, Northrop Grumman\, Boeing\, Nvidia and Xilinx. She has served as associate editor in IEEE Transactions on Circuits and Systems-I (TCAS-I) and IEEE Transactions on Biomedical Circuits and Systems (TBioCAS). She was the local arrangement co-chair for the 50th IEEE\nInternational Symposium on Circuits and Systems (ISCAS) in Baltimore. She has also served as technical program committee member of the IEEE International Solid-State Circuits Conference Student Research (ISSCC-SRP)\, IEEE Biomedical Circuits and Systems (BioCAS)\, IEEE International Symposium on Circuits and Systems (ISCAS)\, ACM Great Lakes Symposium on VLSI (GLSVLSI and IEEE International Symposium on Quality Electronic Design (ISQED) conferences. She also serves as secretary of IEEE P1890 on Error Correction Coding for Non-Volatile Memories.
URL:https://www.cecs.uci.edu/event/efficient-processing-when-intelligence-moves-to-the-edge/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190808Z
LAST-MODIFIED:20231011T190813Z
UID:14539-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Sensors" Innovation at Intersections"
DESCRIPTION:Name: Khaled Salama\nDate and Time: Friday\, August 3 at 10:00 a.m. – 11:00 a.m. \nLocation: Engineering Hall 2430 \nAbstract:  \n\nEnergy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. We will provide a summary of various sensors developed under the KAUST sensors initiative a consortium of 9 universities (KAUST\, MIT\, UCLA\, GATECH\, MIT\, UCLA\, Brown University\, Georgia Tech\, TU Delft\, Swansea University\, the University of Regensburg and the Australian Institute of Marine Science (AIMS). \n\nBiography: \nKhaled N. Salama received the B.S. degree from the Department Electronics and Communications\, Cairo University\, Cairo\, Egypt\, in 1997\, and the M.S. and Ph.D. degrees from the Department of Electrical Engineering\, Stanford University\, Stanford\, CA\, USA\, in 2000 and 2005\, respectively. He was an Assistant Professor at Rensselaer Polytechnic Institute\, NY\, USA\, between 2005 and 2009. He joined King Abdullah University of Science and Technology (KAUST) in January 2009\, where he is now a professor\, and was the founding Program Chair until August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford–Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc. He is the author of 200 papers and 14 US patents on low-power mixed-signal circuits for intelligent fully integrated sensors and neuromorphic circuits using memristor devices.
URL:https://www.cecs.uci.edu/event/sensors-innovation-at-intersections-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190805Z
CREATED:20231011T190805Z
LAST-MODIFIED:20231011T190805Z
UID:14534-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Sensors" Innovation at Intersections"
DESCRIPTION:Name: Khaled Salama\nDate and Time: Friday\, August 3 at 10:00 a.m. – 11:00 a.m. \nLocation: Engineering Hall 2430 \nAbstract:  \n\nEnergy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. We will provide a summary of various sensors developed under the KAUST sensors initiative a consortium of 9 universities (KAUST\, MIT\, UCLA\, GATECH\, MIT\, UCLA\, Brown University\, Georgia Tech\, TU Delft\, Swansea University\, the University of Regensburg and the Australian Institute of Marine Science (AIMS). \n\nBiography: \nKhaled N. Salama received the B.S. degree from the Department Electronics and Communications\, Cairo University\, Cairo\, Egypt\, in 1997\, and the M.S. and Ph.D. degrees from the Department of Electrical Engineering\, Stanford University\, Stanford\, CA\, USA\, in 2000 and 2005\, respectively. He was an Assistant Professor at Rensselaer Polytechnic Institute\, NY\, USA\, between 2005 and 2009. He joined King Abdullah University of Science and Technology (KAUST) in January 2009\, where he is now a professor\, and was the founding Program Chair until August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford–Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc. He is the author of 200 papers and 14 US patents on low-power mixed-signal circuits for intelligent fully integrated sensors and neuromorphic circuits using memristor devices.
URL:https://www.cecs.uci.edu/event/sensors-innovation-at-intersections/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14532-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:“Regional Coherence and Near Memory Acceleration in Distributed-Shared-Memory Architectures”
DESCRIPTION:Name: Andreas Herkersdorf\nDate and Time: Thursday\, July 26 at 11:00 a.m. – 12:00 p.m. \nLocation: Donald Bren Hall 3011 \nAbstract:  \nData access latencies and bandwidth bottlenecks frequently represent major limiting factors for the computational effectiveness of many-core processor architectures. This presentation introduces two\nconceptually complementary approaches to reduce the synchronization overheads for coherence\nmaintenance and to improve the locality between computing resources and data: Region-based cache\ncoherence and near memory acceleration. \nA 2D array of compute tiles with multiple\, heterogeneous RISC cores\, two levels of caches and a tile-local\nSRAM memory serves as reference processing platform. These compute tiles\, various I/O tiles and a globally shared DDR SDRAM memory tile are interconnected by a meshed Network on Chip (NoC) with support for multiple quality of service levels. Overall\, this processing architecture follows a distributed-\nshared-memory model. The limited degree of parallelism in many embedded computing applications\nalso bounds the number of compute tiles possibly sharing associated data structures. Therefore\, we favor region-based cache coherence (RBCC) among a limited number of compute tiles over global coherence approaches. Coherence regions are dynamically configured at runtime and comprise a number of arbitrary (adjacent or non-adjacent) compute tiles which are interconnected through regular NoC channels for the exchange of coherency protocol messages. We will show that region-based coherence allows maintaining substantially smaller coherence directories (e.g.\, by approx. 40% reduced in size for 16 tiles systems with up to 4 tiles per region) and shorter sharer checking latencies than global coherence. RBCC increases the locally usable intra-tile shared SRAM memories and may reduce execution times of sample video processing applications by 30% in comparison to message passing based parallelization. However\, the benefits of RBCC may strongly depend on the task and data placement among tiles in the coherency region which can affect performance by up to an order of magnitude. Near memory processing using near memory accelerators (NMA) positions processing resources for specific data manipulations as close as possible to the data memory for the benefit of shortening access latencies and increasing compute efficiency. \nBiography: \nAndreas Herkersdorf is a professor in the Department of Electrical and Computer Engineering and also\naffiliated to the Department of Informatics at Technical University of Munich (TUM). He received a Dr.\ndegree from ETH Zurich\, Switzerland\, in 1991. Between 1988 and 2003\, he has been in technical and\nmanagement positions with the IBM Research Laboratory in Rüschlikon\, Switzerland.\nSince 2003\, Dr. Herkersdorf leads the Chair of Integrated Systems at TUM. He is a senior member of the\nIEEE\, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer and De Gruyter journals for design automation and information technology. His research interests include application-specific multi-processor architectures\, IP network processing\, Network on Chip and self-adaptive fault-tolerant computing.
URL:https://www.cecs.uci.edu/event/regional-coherence-and-near-memory-acceleration-in-distributed-shared-memory-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14533-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Accurate and Stable CPU Power Modelling and Run-Time System Management"
DESCRIPTION:Name: Matthew Walker\nDate and Time: Friday\, July 27 at 11:00 a.m. – 12:00 p.m. \nLocation: Donald Bren Hall 4011 \nAbstract:  \nModern processors must provide an ever-increasing level of performance and are therefore including\nhigher numbers of Heterogeneous Multi-Processing (HMP) units. Intelligent run-time control of performance and power consumption is required to extend battery-life in mobile systems\, reduce energy and cooling costs in data centres\, and increase peak performance while respecting thermal and power constraints. Accurate online power estimation is essential in guiding run-time power management mechanisms and energy-aware scheduling decisions.\n\nIn this talk Matt will share his experience with CPU modelling and run-time management\, and present three open-source software tools for developing power models on mobile devices (http://www.powmon.ecs.soton.ac.uk)\, calibrating performance and energy models in the gem5 simulation framework (http://gemstone.ecs.soton.ac.uk)\, and developing run-time management algorithms (https://github.com/PRiME-project/PRiME-Framework/).\nBiography: \nMatthew J. Walker received his M.Eng. degree in Electronic Engineering (Hons) from the University of Southampton\, UK\, in 2013. In 2016 he worked on implementing non-volatile memory technologies in mobile systems at Intel Labs\, CA\, and has also completed two internships at Arm\, UK\, in 2015 and 2018. He is currently in his fourth year of his PhD at the University of Southampton researching CPU modelling techniques and run-time management approaches.
URL:https://www.cecs.uci.edu/event/accurate-and-stable-cpu-power-modelling-and-run-time-system-management/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180702T150000
DTEND;TZID=America/Los_Angeles:20180702T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14531-1530543600-1530547200@www.cecs.uci.edu
SUMMARY:Kasra Moazzemi receives 2nd place at SIGDA PhD Forum
DESCRIPTION:The Ph.D. Forum at the Design Automation Conference is a poster session co-sponsored by both ACM SIGDA and IEEE CEDA for Ph.D. students to present and discuss their dissertation research with people in the EDA community. It has become one of the premier forums for Ph.D. students in design automation to get feedback on their research and for industry to see academic work in progress: hundreds of people attend the forums. Participation in the forum is competitive with the acceptance rate around 30%.\nKasra Moazzemi is a PhD candidate in CECS and ICS and is advised by Prof. Nikil Dutt. The title of his presentation was “Dynamic Resource Management for Many-core Systems using Supervisory Control.” Congratulations\, Kasra! \nhttps://cecs.uci.edu/files/2018/07/Kasra.pdf\nhttps://cecs.uci.edu/files/2018/07/KasraCrop.pdf\nhttps://cecs.uci.edu/files/2018/07/KasraCrop-1.pdf
URL:https://www.cecs.uci.edu/event/kasra-moazzemi-receives-2nd-place-at-sigda-phd-forum/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180607T150000
DTEND;TZID=America/Los_Angeles:20180607T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14530-1528383600-1528387200@www.cecs.uci.edu
SUMMARY:Modeling and Co-Design of Multi-domain Cyber-Physical Systems
DESCRIPTION:Name: Jiang Wan \nDate: Friday\, June 1 \nTime: 3:00 — 5:00 PM \nLocation: EH 3206 \nCommittee: Fadi Kurdahi (Chair)\, Mohammad Al Faruque\, Rainer Doemer \nAbstract: \nCyber-Physical Systems (CPS) are integration of computation and physical processes connected through networks. The high complexity of cross-domain engineering in combination with the pressure for system innovation\, higher quality\, time-to-market\, and budget constraints make it imperative for engineers to use integrated engineering methods and tools for CPS design. However\, existing computer-based engineering tools are mainly focused on a particular domain and therefore it is challenging to perform system-level analysis for CPS due to the difficulty of knowledge integration from different domains. This thesis studies the problem in the modeling of cross-domain CPS. Problems in the modeling of both functional and non-functional requirements during CPS design are explored and a functional model-based approach is proposed for high level CPS modeling. Moreover\, targeting the security requirement in CPS\, which is one of the key non-functional requirements in CPS\, physics-based models and solutions are proposed in this thesis. \n 
URL:https://www.cecs.uci.edu/event/modeling-and-co-design-of-multi-domain-cyber-physical-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180606T150000
DTEND;TZID=America/Los_Angeles:20180606T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14529-1528297200-1528300800@www.cecs.uci.edu
SUMMARY:Reliable and Energy Efficient Battery-Powered Cyber-Physical Systems
DESCRIPTION:Name: Korosh Vatanparvar\nDate: Wednesday\, May 30th \nTime: 3:00 — 5:00 PM \nLocation: Calit2 3008 \nCommittee: Professor Prof. Mohammad Al Faruque (Chair) \nAbstract: \nCyber-Physical Systems (CPS) were presented as a solution to multidisciplinary integration and control in embedded systems. They provide seamless interactions between cyber and physical domains\, enabling more intelligent and complicated control applications. However\, CPS face the challenges of reliability and energy efficiency since they mainly rely on batteries for power supply. \nWe investigate these issues with Electric Vehicles (EV) which are common battery-powered CPS. EV were introduced as a mean of transportation to address environmental problems like air and noise pollution. However\, their stringent design constraints\, especially on battery packs\, create challenges of limited driving range and battery lifetime for daily drivers and manufacturers. Design automation community has been addressing these by developing more efficient and dependable devices and control methodologies. Our contributions in this thesis will embrace: \n1) novel machine learning and physics-based modeling techniques to capture CPS dynamics more accurately; 2) unique optimization problem formulations to make optimal control decisions; and 3)intelligent control methodologies that leverage the modeling and interaction within CPS to achieve reliable and efficient operation. These contributions are applied to the systems in EV such as navigation system\, climate control\, and battery management system. Our objectives are to further extend the EV driving range and prolong the battery lifetime while maintaining similar driving experience and comfort for passengers. \n 
URL:https://www.cecs.uci.edu/event/reliable-and-energy-efficient-battery-powered-cyber-physical-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180530T150000
DTEND;TZID=America/Los_Angeles:20180530T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14528-1527692400-1527696000@www.cecs.uci.edu
SUMMARY:"Are there any questions?"
DESCRIPTION:Name: Yale Patt\nDate and Time: Thursday\, June 7 at 2:00 p.m. – 3:00 p.m. \nLocation: Engineering Hall 2430 \nAbstract:  \nToo many seminars can be characterized as 50 minutes of lecture\, followed by 5 minutes of questions. …and the first question makes it clear that nothing the speaker said in the 50 minutes was at all interesting to the audience. So\, we will take the opposite approach: 5 minutes of lecture\, followed by 50 minutes of questions. 5 minutes of lecture just to set the tone. Where the questions will take us is anybody’s guess. It will probably have something to do with computer architecture\, historical or current\, but it may venture off into something political …or at least politically correct. \nBiography: \nYale Patt is a Professor of Electrical and Computer Engineering and the Ernest\nCockrell\, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He divides his\ntime between teaching the freshman and senior courses and his advanced graduate course in\nmicroarchitecture\, working with his PhD students\, and consulting in the microprocessor industry.\nHe earned obligatory degrees from reputable universities and has received more than his share of\nawards for his research and teaching. Patt has spent much of his career pursuring aggressive ILP\,\nout-of-order\, and speculative computer architectures\, such as HPSm. He has a Fellow of both the\nIEEE and ACM\, and a member of the National Academy of Engineering. He received his master’s\nand Ph.D. degrees in Electrical Engineering from Stanford University.
URL:https://www.cecs.uci.edu/event/are-there-any-questions/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180521T150000
DTEND;TZID=America/Los_Angeles:20180521T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14527-1526914800-1526918400@www.cecs.uci.edu
SUMMARY:"One does not need a Village to make a Billion Gate ASIC\, only a family if Synchoros VLSI Design Style is adopted"
DESCRIPTION:Name: Ahmed Hemani\nDate and Time: June 6\, 2018 at 4:00 p.m. \nLocation: Engineering Hall 2430 \nCommittee: Nikil Dutt (Host) \nAbstract: \nNorman Jouppi while introducing the record long list of authors of Google’s TPU paper at ISCA 2017 remarked – one needs a village to make a chip. This talk proposes a VLSI design method that holds promise of getting the same work done with just a family. This new VLSI design method is based on two principles\, one is to raise the abstraction of physical design to micro-architecture level from the present day boolean level standard cells and the second is to adopt a synchoros VLSI design style that enables composition by abutment to eliminate logic and physical synthesis for the end user. \nThe proposed method raises the abstraction of physical design to micro-architecture level by adopting coarse grain reconfigurable logic for computation\, storage and interconnect. All variations in function\, capacity\, architecture and degree of parallelism are realised by clustering and configuration of the coarse grain reconfigurable cells that we call as SiLago blocks – Silicon Lego Blocks. The micro-architecture level SiLago blocks replace boolean level standard cells as the atomic building blocks of the VLSI systems. These CGRA fabrics are domain specific – inner modem\, outer modem\, scratchpad memory\, dynamic programming\, NOCs\, infrastructural elements like RISC system controller\, PLL/CGU\, RGU\, DRAM control etc. Each CGRA fabric is holistically customized for its domain\, not just for computation but also for control\, interconnect\, address generation\, local storage etc. \nThe CGRAs provide an architecturally regular basis for a synchoros VLSI design style. Synchoricity is derived from the Greek word “choros” for space. The way synchronous systems divide time uniformly with clock ticks and enables temporal composition\, synchoros systems divide space uniformly with grids and enables spatial composition. All SiLago blocks are synchoros or ratiochoros and bring out all their interconnects to periphery on grid at right place and on right metal layer to enable composition by abutment of valid neighbours. \nThe net result of adopting the above two principles is that as soon as a design is refined down to micro-architecture level\, the dimension and position of every single wire segment and transistor is known with certainty in the 100 million gate design. Unlike standard cells\, where the position of standard cells and wires connecting them is left to physical synthesis\, in synchoros design style these aspects are parametrically hardened. Global wires like power grid\, clocks\, resets\, NOCs are not synthesised\, they emerge as a result of the abutment process. This enables automation of system models down to GDSII to create custom\, spatially distributed functional hardware\, i.e.\, ASICs with just a family. \nA proof of concept synthesis flow exists for transforming applications\, hierarchy of algorithms\, to GDSII and a path for system level to GDSII is well defined and is being implemented. System-level implies interacting applications. \nBiography: \nAhmed Hemani is Professor in Electronic Systems Design at School of ICT\, KTH\, Kista\, Sweden. His current areas of research interests are massively parallel architectures and design methods and their applications to scientific computing and autonomous embedded systems inspired by brain. In past he has contributed to high-level synthesis – his doctoral thesis was the basis for the first high-level\nsynthesis product introduced by Cadence called visual architect. He has also pioneered the Networks-on-chip concept and has contributed to clocking and low power architectures and design methods. He has extensively worked in industry including National Semiconductors\, ABB\, Ericsson\, Philips Semiconductors\, Newlogic. He has also been part of three start-ups.
URL:https://www.cecs.uci.edu/event/one-does-not-need-a-village-to-make-a-billion-gate-asic-only-a-family-if-synchoros-vlsi-design-style-is-adopted/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180517T150000
DTEND;TZID=America/Los_Angeles:20180517T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14526-1526569200-1526572800@www.cecs.uci.edu
SUMMARY:Reflective On-Chip Resource Management Policies for Energy-Efficient Heterogeneous Multiprocessors
DESCRIPTION:Name: Tiago Mück\nDate: May 16\, 2018 \nTime: 2:00pm \nLocation: Donald Bren Hall 2011 \nCommittee: Nikil Dutt (Chair)\, Alex Nicolau\, Tony Givargis \nAbstract: \nEffective exploitation of power-performance tradeoffs in heterogeneous many-core platforms (HMPs)\, requires intelligent on-chip resource management at different layers\, in particular at the operating system level. Operating systems need to continuously analyze the application behavior and find a proper answer for questions such as: What is the most power efficient core type to execute the application without violating its performance requirements? or Which option is more power-efficient for the current application: an out-of-order core at a lower frequency or an inorder core at a higher frequency?\nUnfortunately\, existing operating systems (e.g. Linux) do not offer mechanisms to properly address these questions and therefore are unable to fully exploit architectural heterogeneity for scalable energy-efficient execution of dynamic workloads.\nThis dissertation proposes a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software.\n\nThe general idea of reflection is to change your actions based on both external feedback and introspection (i.e.\, self-assessment).\n\n\nFrom a practical computer system perspective\, reflection means performing resource management actions considering both sensing information (e.g.\, readings from performance counters\, power sensors\, etc.) to assess the current system state\, as well as models to predict the behavior of the system before performing an action.\nIn this context\, this dissertation describes MARS\, a Middleware for Adaptive Reflective computer Systems. MARS consists of a framework and a set of models for creating reflective resource managers. MARS is implemented and evaluated on top a real Linux-based platform. Furthermore\, MARS also provides an offline simulation infrastructure for fast prototyping of policies and large-scale or long-term policy evaluation.\n\nExperimental evaluation shows that MARS’s models allow different policies for task mapping and dynamic voltage scaling to be seamlessly integrated\, resulting in up-to 1.8x energy efficiency improvements without performance degradation when compared to vanilla Linux.
URL:https://www.cecs.uci.edu/event/reflective-on-chip-resource-management-policies-for-energy-efficient-heterogeneous-multiprocessors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14524-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:“Self-aware Computing: Combining Learning and Control to Manage Complex\, Dynamic Systems”
DESCRIPTION:<stThese self-aware systems are distinguished by awareness of user goals and operating environment; they continuously monitor themselves and adapt their behavior and foundational models to ensure the goals are met despite the challenges of complexity (diverse hardware resources to be managed) and dynamics (unpredictable changes in input workload or resource availability). In this talk\, I will describe how to build self-aware systems through a combination of control theoretic and machine learning techniques. I will then show how this combination enables new capabilities\, like increasing system robustness\, reducing application energy\, and meeting latency requirements even with no prior knowledge of the application. Finally\, these LTE protocol exploits are analyzed in the context of the recently (December 2017) published first release of the 3GPP 5G specifications (3GPP Rel. 15) for the 5G Radio Access Network (5G New Radio) and Core Network (5G System). Unfortunately\, not only most protocol-aware radio jamming issues and LTE protocol exploits are still a potential threat\, but there is a large number of new pre-authentication messages and new fields to already existing messages that could open the doors to further 5G-specific exploits. \nBiography: \nHenry Hoffmann is an Associate Professor in the Department of Computer Science at the University of Chicago. He was granted early tenure in 2018. At Chicago he leads the Self-aware computing group (or SEEC project) and conducts research on adaptive techniques for power\, energy\, accuracy\, and performance management in computing systems. He received the DOE Early Career Award in 2015. He has spent the last 17 years working on multicore architectures and system software in both academia and industry. He completed a PhD in Electrical Engineering and Computer Science at MIT where his research on self-aware computing was named one of the ten “World Changing Ideas”  by Scientific American in December 2011. He received his SM degree in Electrical Engineering and Computer Science from MIT in 2003. As a Masters student he worked on MIT’s Raw processor\, one of the first multicores. Along with other members of the Raw team\, he spent several years at Tilera Corporation\, a startup which commercialized the Raw architecture and created one of the first manycores (Tilera was sold for $130M in 2014). His implementation of the BDTI Communications Benchmark (OFDM) on Tilera’s 64- core TILE64 processor still has the highest certified performance of any programmable processor. In 1999\, he received his BS in Mathematical Sciences with highest honors and highest distinction from UNC Chapel Hill. \n 
URL:https://www.cecs.uci.edu/event/self-aware-computing-combining-learning-and-control-to-manage-complex-dynamic-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14525-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:SIMD Assisted Fault Detection and Fault Attack Mitigation
DESCRIPTION:Name: Zhi Chen\nDate: May 15\, 2018 \nTime: 2:30pm \nLocation: Donald Bren Hall 3011 \nCommittee: Professor Alex Nicolau (Chair)\, Alex Veidenbaum\, Nikil Dutt \nAbstract: \nModern processors continue to aggressively scale down the feature size and reduce voltage levels to run faster and be more energy efficient. However\, this trend also poses significant reliability concern as it makes transistors more susceptible to soft errors. Soft errors are transient. Although they don’t impair the computing systems permanently\, these errors can corrupt the output of a program or even crash the entire system. Hardware or software redundant techniques could be used to detect errors during the execution of a program. However\, hardware redundancy\, e.g. DMR (dual-modular redundancy) and TMR (triple-modular redundancy)\, leads to significant area overhead and very high energy cost. Software redundancy\, e.g. instruction duplication\, has lower performance and energy penalty and  virtually no hardware cost by sacrificing a small degree of error coverage. Yet commodity processors generally don’t require “five-nines” reliability as they are not mission-critical. Instead\, performance and energy consumption have more priority. This dissertation proposes a novel approach to instruction duplication\, which exploits the redundancy within SIMD instructions. The key idea is to pack the original data and its duplicate in the different lanes of the same vector register instead of executing two scalar instructions separately as these registers are underutilized on most applications. The proposed solution is implemented in the LLVM compiler as a stand-alone pass. Evaluation on a host of benchmarks reveal that proposed SIMD-based error detection technique causes much less performance\, code size\, and energy overheads.\n\nThis dissertation further extends the proposed approach as a countermeasure to protect cryptographic algorithms. These algorithms are widely adopted in modern processors and embedded systems to protect information. A number of popular cryptographic algorithms in the Libgcrypt library are protected using the SIMD-based instruction duplication technique. A large amount of errors are injected to these algorithms. The results show that almost all injected faults can be detected with reasonable performance and code size cost.\n 
URL:https://www.cecs.uci.edu/event/simd-assisted-fault-detection-and-fault-attack-mitigation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180507T150000
DTEND;TZID=America/Los_Angeles:20180507T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14518-1525705200-1525708800@www.cecs.uci.edu
SUMMARY:"Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks"
DESCRIPTION:Title: “Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks”\nSpeaker: Roger Piqueras Jover\, Security Researcher at Bloomberg LP \nDate and Time: Tuesday\, May 15 at 10:00 a.m. \nLocation: Donald Bren Hall 3011 \nAbstract:  \nThe Long Term Evolution (LTE) is the latest mobile communications standard being deployed globally to provide connectivity to billions of mobile devices\, from personal cell-phones to all types of critical systems\, such as self-driving cars\, medical appliances and industrial IoT sensors. As such\, the security of this communication standard is of paramount importance. However\, there is concerning inherent protocol security threats in LTE due to the large amount of unauthenticated and unprotected messages exchanged between a base station and a mobile device prior to the authentication security handshake. \nOpen source implementations of the LTE standards rapidly matured within the last couple of years. This\, in combination with sophisticated yet low cost software radio hardware\, fueled a new wave of security research that identified numerous protocol security issues in LTE that could allow an adversary to deny the service of mobile endpoints and track the location of users. This talk will summarize an ongoing effort on protocol-fuzzing LTE mobile networks using open-software tools. The protocol exploits against mobile endpoints that were discovered two years ago will be discussed as an introduction to the new systematic approach to protocol-fuzz LTE networks\, introducing as well a series of new potential exploits in the uplink\, against the network infrastructure and mobile devices outside of the radio range of the adversary. \nFinally\, these LTE protocol exploits are analyzed in the context of the recently (December 2017) published first release of the 3GPP 5G specifications (3GPP Rel. 15) for the 5G Radio Access Network (5G New Radio) and Core Network (5G System). Unfortunately\, not only most protocol-aware radio jamming issues and LTE protocol exploits are still a potential threat\, but there is a large number of new pre-authentication messages and new fields to already existing messages that could open the doors to further 5G-specific exploits. \nBiography: \nRoger Piqueras Jover is a Wireless Security Research Scientist and Security Architect at the CTO Security Architecture team of Bloomberg LP\, where he leads projects on mobile/wireless security and is actively involved in hardware security\, network security\, machine learning and anomaly/fraud detection. Previous to Bloomberg\, he spent 5 years at the AT&T Security Research Center (AT&T SRC)\, where he led the research area on wireless and LTE mobile network security and received numerous awards for his work. \nRoger holds 17 issued patents on mobile and wireless security\, has co-authored manuscripts in numerous top communications and security conferences and is the Technical Co-Chair for the ongoing IEEE 5G Summit series. \nRoger holds a Dipl. Ing. from Politechnical University of Catalunya (Barcelona\, Spain)\, a Master’s in Electrical and Computer Engineering from University of California Irvine and a Master’s/MPhil and EBD (Everything But Dissertation) in Electrical Engineering from Columbia University. \nFor a much more detailed biography\, details on his wireless security work on LTE\, 5G\, LoRaWAN and other technologies\, one can refer to http://rogerpiquerasjover.net/
URL:https://www.cecs.uci.edu/event/protocol-fuzzing-mobile-networks-with-open-source-tools-to-enhance-the-security-of-lte-and-5g-mobile-networks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180503T150000
DTEND;TZID=America/Los_Angeles:20180503T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14517-1525359600-1525363200@www.cecs.uci.edu
SUMMARY:"Efficient Acceleration of Computation Using Associative In-memory Processing"
DESCRIPTION:Title: “Efficient Acceleration of Computation Using Associative In-memory Processing”\nSpeaker: Hasan Erdem Yantir\, University of California\, Irvine \nDate and Time: Monday\, May 14\, 2018 at 9:00AM \nLocation: Engineering Hall 3206 \nCommittee: Professor Fadi Kurdahi (Chair)\, Ahmed Eltawil\, Rainer Doemer \nAbstract: \nThe complexity of the computational problems is rising faster than the computational platforms’ capabilities. This forces researchers to find alternative paradigms and methods for efficient computing. One promising paradigm is accelerating compute-intensive kernels using in-memory computing accelerators since memory is the major bottleneck that limits the amount of parallelism and performance of a system and dominates energy consumption in computation. Leveraging the memory intensive nature of big data applications\, an in-memory-based computation system can be presented where logic can be replaced by memory structures\, virtually eliminating the need for memory load/store operations during computation. The massive parallelism enabled by such a paradigm results in highly scalable structures. \nThe present thesis is studied against this background. The objective is to conduct a broad perspective research on in-memory computing. For this purpose\, associative computing architectures (i.e.\, Associative Processors\, or AP) are built by both traditional (SRAM) and emerging (ReRAM) memory technologies together with their corresponding software frameworks. For ReRAM-based APs\, the reliability concerns coming with the emerging memories are resolved. Architectural innovations are developed to increase the energy efficiency. Furthermore\, approximate computing approach is introduced for APs to perform efficient/low-power approximate in-memory computing for the tasks which can tolerate some accuracy lost.  The works also propose a novel two-dimensional in-memory computing architecture to cope with the existing deficiencies of the traditional one-dimensional AP architectures.
URL:https://www.cecs.uci.edu/event/efficient-acceleration-of-computation-using-associative-in-memory-processing/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180411T150000
DTEND;TZID=America/Los_Angeles:20180411T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190729Z
UID:14516-1523458800-1523462400@www.cecs.uci.edu
SUMMARY:"A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models"
DESCRIPTION:Title: “A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models”\nSpeaker: Tim Schmidt\, University of California\, Irvine \nDate and Time: Friday\, April 20\, 2018 at 10:00AM-11:00PM \nLocation: Engineering Hall 3206 \nCommittee: Professor Rainer Doemer (Chair)\, Fadi Kurdahi\, Kwei-Jay Lin \nAbstract: \nThe design of embedded systems is a well-established research domain for many decades. However\, the constantly increasing complexity and requirements of state-of-the-art embed- ded systems pushes designers to new challenges while maintaining established design methodologies. Embedded system design uses the concept of Discrete Event Simulation (DES) to prototype and test the interaction of individual components. \nIn this dissertation\, we provide the Recoding Infrastructure for SystemC (RISC) compiler framework to perform static and hybrid analysis of IEEE SystemC models. On one hand\, RISC generates thread communication charts to visualize the communication between individual design components. The\nvisualization respects the underlying discrete event simulation semantics and illustrates the individual synchronization steps. On the other hand\, RISC translates a sequential model into a parallel model\nwhich effectively utilizes multi- and many-core host simulation platforms for faster simulation. This work extends the conflict analysis capabilities for libraries\, dynamic memory allocation\, channel instance awareness\, and references. Additionally\, the traditional thread level parallelism is extended with data level parallelism for even faster simulation.
URL:https://www.cecs.uci.edu/event/a-compiler-infrastructure-for-static-and-hybrid-analysis-of-discrete-event-system-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180402T150000
DTEND;TZID=America/Los_Angeles:20180402T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190729Z
UID:14515-1522681200-1522684800@www.cecs.uci.edu
SUMMARY:"ASSISTECH: Assistive Technology for the Visually Impaired"
DESCRIPTION:Title: “ASSISTECH: Assistive Technology for the Visually Impaired”\nSpeaker: Professor Mayandiambalam Balakrishnan\, CSE\, Indian Institute of Technology\, Delhi\, India \nDate and Time: Monday\, March 26 at 3:00PM-4:00PM \nLocation: Donald Bren Hall 4011 \nAbstract:  \nMore than ten years back we started on the ASSISTECH journey – a laboratory dedicated to finding\ntechnology solutions for the mobility and education of the visually impaired. It has been a very challenging but deeply fulfilling journey. Globally there are many technology solutions available for addressing the mobility as well as education needs of the visually impaired. Unfortunately they fail to address the challenges of mobility and education in India and other developing countries and even if they do they are completely unaffordable. In this talk I would tell the story of development and dissemination of devices and technologies like SmartCane\, OnBoard and Tactile Diagrams. These started in the ASSISTECH laboratory as inter-disciplinary projects and are today slowly finding their way to the users. \nBiography: \nM Balakrishnan has a B.Tech.(EEE) from BITS Pilani and PhD(EE) from IIT Delhi. He has been\ninvolved in teaching and research in EDA\, VLSI and Embedded systems for more than three decades. He has published over 120 papers in leading journals and conferences\, supervised 13 PhD students and over 180 B.Tech. and M.Tech. student projects. He has held visiting positions in Canada\, US and Germany. He has founded the ASSISTECH laboratory at IIT Delhi which is engaged in finding affordable technology based solutions for education and mobility of visually impaired. He is a recipient of two national awards for his work in the disability space. He has been HoD(CSE)\, Dean(Post Graduate Studies & Research)\, Deputy Director(Faculty) and is currently Deputy Director(Strategy & Planning) at IIT Delhi.
URL:https://www.cecs.uci.edu/event/assistech-assistive-technology-for-the-visually-impaired/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180222T150000
DTEND;TZID=America/Los_Angeles:20180222T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190724Z
LAST-MODIFIED:20231011T190729Z
UID:14514-1519311600-1519315200@www.cecs.uci.edu
SUMMARY:”Cost and Power Efficient Deep Neural Network Acceleration”
DESCRIPTION:Title: “Cost and Power Efficient Deep Neural Network Acceleration”\nSpeaker: Associate Prof. Jongeun Lee\, School of ECE\, UNIST\, Ulsan\, Korea \nDate and Time: Monday\, February 26\, 2018 at 11:00am – 12:00pm \nLocation: EH 2430 \nAbstract: \nDeep neural networks prove to be a right direction after all\, but the enormous computational complexity calls for new research into novel ways of making efficient implementations of the connectionist model for small\, mobile devices. \nIn this talk I will discuss two directions\, one based on FPGA and the other based on a new computing paradigm called stochastic computing (SC).  FPGA is a very capable device housing thousands of processing elements in a single chip with low power consumption.  However\, FPGAs are very different from GPUs\, and making it easy to program FPGAs for deep neural networks is one of the key challenges facing FPGAs today.  I will present a design space exploration approach to help find the best design for a given FPGA and for a specific deep neural network model. \nStochastic computing (SC) was first introduced in the 60’s when computing devices were not very reliable.  Unlike conventional binary number representations\, stochastic computing uses a bitstream to represent a number\, and is therefore inherently more error-resilient. \nIn addition\, SC shares some good qualities with analog computing such as low power dissipation and low cost while strictly operating in the digital domain.  At the same time\, error fluctuation and conversion overhead are the key challenges facing SC today.  I will present a new SC architecture for deep neural networks that is much more accurate and efficient than previous SC solutions. \nBiography: \nJongeun Lee received his B.S. and M.S. in Electrical Engineering\, and his Ph.D. in electrical engineering and computer science all from Seoul National University\, Korea. In 2009 he joined UNIST (Ulsan National Institute of Science and Technology)\, Ulsan\, Korea\, where he is now an Associate Professor of Electrical and Computer Engineering. Prior to joining UNIST\, he worked as a postdoctoral research associate at Arizona State University\, and previously worked for Samsung Electronics. His current research interests include reconfigurable architectures\, compilers\, stochastic computing\, and deep neural networks.
URL:https://www.cecs.uci.edu/event/cost-and-power-efficient-deep-neural-network-acceleration/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180206T150000
DTEND;TZID=America/Los_Angeles:20180206T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14512-1517929200-1517932800@www.cecs.uci.edu
SUMMARY:“Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins”
DESCRIPTION:Title: “Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins”\nSpeaker: Prof. Sergio Bampi\, Informatics Institute – Microelectronics Design – Federal University of Rio Grande do Sul\, Brazil \nDate and Time: Thursday\, February 15\, 2018 at 2:00PM-3:00PM \nLocation: ICS 432 \nAbstract: \nPromising opportunities for research on heterogeneous Internet-of- Things (IoT) devices lie at the energy-bottom floor\, where CMOS is still an unbeatable\, flexible technology to make the internet of “everything” possible and cost-effective. Near-threshold computing (NTC) in CMOS is a promising alternative for any application which can tolerate or benefit from very wide voltage-frequency scaling (VFS). The digital blocks of devices may operate at very different power-performance modes\, from sub-MHz to peaks of hundreds of MHz\, which requires CMOS design libraries targeted for NTC. The analog and RF content on IoT chips will be even more crucial\, from a power-savings standpoint. In IoT it is best to avoid using costlier CMOS\, and yet closer to an end\, two-dimensional transistor and IC scaling. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific logic design techniques to be applied in digital CMOS. This talk addresses a method to design CMOS digital circuits for a wide dynamic range of VFS\, and targets near-threshold for best energy-efficiency. Our work on 65nm CMOS has demonstrated 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their system operating modes. The results in CMOS were obtained using the minimal cycle time achievable at each supply voltage\, down to very low 200 mV supplies. The strategy for transistor sizing in digital cells and static noise margin maximization will be addressed in particular. The seminar seeks to stimulate system-level and circuit-level design approaches for IoT nodes\, as the presenter is available to discuss digital\, mixed-signal\, and even RF aspects of CMOS systems-on- IoT-devices. \nBiography: \nSergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS\, 1979)\, and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics design fields at the Informatics Institute\, member of the faculty since 1986. He is a member of the PPGC Computing Graduate Program since 1988\, and of the PGMICRO since its start in 2002. He served as Graduate Program Coordinator (2003-2007)\, head of research group and projects\, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff\, and a visiting research faculty at Stanford University (1998-99). His research interests are in the area of IC design\, nano-CMOS devices\, mixed signal and RF CMOS design\, ultra-low power digital design\, dedicated complex algorithms\, architectures\, and ASICs for image and video processing. He has co-authored more than 360 papers in these fields and in MOS devices and EDA. He is a senior member of IEEE. He was Technical Program Chair of IEEE SBCCI Symposium (1997\, 2005)\, SBMICRO (1989\, 1995)\, IEEE LASCAS (2013)\, VARI 2016 Conferences and Workshops.
URL:https://www.cecs.uci.edu/event/near-threshold-computing-the-bottom-floor-for-energy-in-iot-devices-and-its-vanishing-design-noise-margins/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180118T150000
DTEND;TZID=America/Los_Angeles:20180118T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14511-1516287600-1516291200@www.cecs.uci.edu
SUMMARY:"Digital Early Warning Scoring – A Cognitive IoT based approach"
DESCRIPTION:Title: “Digital Early Warning Scoring – A Cognitive IoT based approach”\nSpeaker: Prof. Pasi Liljeberg\, University of Turku \nDate and Time: Thursday\, January 25\, 2018 at 2:00PM-3:00PM \nLocation: Engineering Hall 2430 \nAbstract: \nIn healthcare\, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs of deterioration exist as early as 24 hours prior having a serious impact on the health of a person. As hospitalization times have to be minimized\, in-home or remote early warning systems can fill the gap by allowing in-home care while having the potentially problematic conditions and their signs under surveillance and control. \nEarly warning score (EWS) is an approach to detect the deterioration of a patient. It is based on a fact that there are several changes in the physiological parameters prior a clinical deterioration of a patient. Currently\, EWS procedure is mostly used for in-hospital clinical cases and is performed in a manual paper-based fashion. However\, it is possible to build an automated EWS health monitoring system to intelligently monitor vital signs and prevent health deterioration for in-home and hospitalized patients using Internet-of-Things technologies. \nBiography: \nPasi Liljeberg received the MSc and PhD degrees in electronics and information technology from the University of Turku\, Turku\, Finland\, in 1999 and 2005\, respectively. He received Adjunct professorship in embedded computing architectures in 2010. Currently he is working as full professor in University of  Turku in the field of Embedded Systems and Internet of Things. At the moment his research is focused on biomedical engineering and health technology. In that context he has established and leading the Internet-of-Things for Healthcare\, IoT4Health\, ( http://iot4health.utu.fi [1] ) research group. Liljeberg is the author of more than 270 peer-reviewed publications.
URL:https://www.cecs.uci.edu/event/digital-early-warning-scoring-a-cognitive-iot-based-approach/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171221T150000
DTEND;TZID=America/Los_Angeles:20171221T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14513-1513868400-1513872000@www.cecs.uci.edu
SUMMARY:“Hierarchial Non-Intrusive In-Situ  Requirements Monitoring for Embedded Systems”
DESCRIPTION:Title:“Hierarchial Non-Intrusive In-Situ Requirements Monitoring for Embedded Systems”\nSpeaker: PhD Candidate Minjun Seo\, University of Arizona\, Tuscon \nDate and Time: Thursday\, December 21\, 2017 at 2:00PM-3:00PM \nLocation:  Engineering Hall 2430 \nAbstract: \nAccounting for all operating conditions of a system at the design stage is typically infeasible for complex systems. In-situ runtime monitoring and verification can enable a system to introspectively ensure the system is operating correctly in the presence of dynamic environment\, to rapidly detect failures\, and to provide detailed execution traces to find the root cause thereof. Two key challenges faced in using in-situ runtime verification for embedded systems include 1) efficiently defining and automatically constructing a requirements model for embedded system software and 2) minimizing the runtime overhead of observing and verifying the runtime execution adheres to the requirements model. In this talk\, we present a methodology to construct a hierarchical runtime monitoring graph from system requirements specified us- ing multiple UML sequence diagrams\, which are already commonly used in software development. We further present the design of on-chip hardware that nonintrusively monitors the system at runtime to ensure the execution matches the requirements model. We evaluate the proposed methodology using a case study of a fail-safe autonomous vehicle subsystem and analyze the relationship between event coverage\, detection rate\, and hardware requirements. \nBiography: \nMinjun Seo is a Ph.D. Candidate in the Department of Electrical and Computer Engineering at the University of Arizona.  His current research focuses on efficient specification and implementation of in-situ requirements monitoring of embedded systems. His research interests also include design tools and optimization methods supporting efficient verification hardware\, FPGAs\, and HW/SW co-design. Mr. Seo received a B.S. in Computer Science and Engineering in 2006 and a M.S. in Computer Science in 2008 from Kyungnam University.
URL:https://www.cecs.uci.edu/event/hierarchial-non-intrusive-in-situ-requirements-monitoring-for-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171128T150000
DTEND;TZID=America/Los_Angeles:20171128T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14510-1511881200-1511884800@www.cecs.uci.edu
SUMMARY:"I/O Optimization for Mobile Flash Storage"
DESCRIPTION:Title: “I/O Optimization for Mobile Flash Storage”\nSpeaker: Prof. Chun Jason Xue\, City University of Hong Kong \nDate and Time: Tuesday\, December 5\, 2017 at 10:00AM-11:00AM \nLocation: DBH 3011 \nAbstract: \nNAND flash memory is the primary choice of data storage for mobile devices due to its high performance\, shock resistance and low power consumption. However\, compared to high-end solid-state drives\, mobile flash storage does not have the luxury of sophisticated hardware and firmware features because of the resource-constraint limits. Instead\, mobile flash storage often equipped with scarce built-in RAM\, slow embedded processors and low-cost flash memories\, all of which make it a challenge to apply traditional techniques for I/O performance improvements. This talk presents a couple of work that we have done recently to optimize I/O for Mobile Flash Storage. First\, this talk will introduce a novel I/O scheduling approach to improve demand-based page-level mapping cache performance. This technique generates mapping cache friendly I/O workloads by strengthening I/O locality at host I/O scheduler. Both temporal locality and spatial localities are taken into consideration for I/O scheduling. Second\, this talk will present a lightweight data compression technique at the flash controller to reduce write pressure on mobile flash storage. It first characterizes data compressibility based on real smartphones\, and the analysis shows that write traffics bound to mobile storage volumes are highly compressible. This technique is the first to investigate firmware-based data compression for mobile flash storage without adding extra data compression hardware. Experimental results demonstrate the proposed techniques outperform state-of-the-art schemes in terms of I/O latency and flash memory lifespan. \nBiography: \nDr. Chun Jason Xue is an Associate Professor at City University of Hong Kong Computer Science Department. His research interests include non-volatile memories\, embedded and real time systems. He is currently Associate Editor for ACM Transaction on Embedded Computing Systems\, Associate Editor for ACM Transaction on CPS\, Associated Editor for ACM Transaction on Storage. He was the TPC co-chair for LCTES 2015\, TPC co-char for ISVLSI 2016\, and has served as TPC members in premiere conferences such as DAC\, DATE\, RTSS\, RTAS\, CODES\, EMSOFT and ISLPED.
URL:https://www.cecs.uci.edu/event/i-o-optimization-for-mobile-flash-storage/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171120T150000
DTEND;TZID=America/Los_Angeles:20171120T160000
DTSTAMP:20231011T193349Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T193349Z
UID:14509-1511190000-1511193600@www.cecs.uci.edu
SUMMARY:Daniel D. Gajski has been conferred with the EDA-Award 2017 by edacentrum
DESCRIPTION:from: https://m.pressebox.de/boxid/881033\nIn recognition of his outstanding lifetime contributions and achievements in research\, development\, and application in the domain of Electronic Design Automation (EDA)\, edacentrum confers the first edacentrum EDA Contribution Award to Prof. Daniel D. Gajski on November 12th \,2017. \nDaniel D. Gajski is one of the most influential scientists in EDA with more than 40 years of intensive engagement in industry and academia. He developed principles for structured design of electronic systems\, implemented these principles by means of languages and tools\, and proved their wide industrial applicability. \nThe “Y-Chart” is likely one of the most cited illustrations in electronic system design. It structures the design space and locates design states\, processes\, tasks and tools. Wolfgang Nebel\, vice chairman of edacentrum handed out the award… more details
URL:https://www.cecs.uci.edu/event/daniel-d-gajski-has-been-conferred-with-the-eda-award-2017-by-edacentrum/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171114T150000
DTEND;TZID=America/Los_Angeles:20171114T160000
DTSTAMP:20231011T190709Z
CREATED:20231011T190702Z
LAST-MODIFIED:20231011T190709Z
UID:14501-1510671600-1510675200@www.cecs.uci.edu
SUMMARY:"Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems"
DESCRIPTION:Title: “Software Assists to On-chip Memory Hierarchy of Manycore Embedded Systems”\nSpeaker: Majid Namaki Shoushtari\, University of California\, Irvine \nDate and Time: Tuesday\, November 7\, 2017 at 11:00AM-12:00PM \nLocation: Donald Bren Hall 2011 \nAbstract:\nThe growing computing demands of emerging application domains such as Recognition/Mining/Synthesis (RMS)\, visual computing\, wearable devices and the Internet of Things (IoT) has driven the move towards manycore architectures to better manage tradeoffs among performance\, energy efficiency\, and reliability.\nThe memory hierarchy of manycore architectures has a major impact on their overall performance\, energy efficiency and reliability. We identify three major problems that make traditional memory hierarchies unattractive for manycore architectures and their data-intensive workloads: (1) they are power hungry and not a good fit for manycores in face of dark silicon\, (2) they are not adaptable to the variable workload’s requirements and memory behavior\, and (3) they are not scalable due to coherence overheads. \nThis thesis argues that many of these inefficiencies are the result of software-agnostic hardware-managed memory hierarchies. Application semantics and behavior captured in software can be exploited to more efficiently manage the memory hierarchy. This thesis exploits some of this information and proposes a number of techniques to mitigate the aforementioned inefficiencies in two broad contexts: (1) explicit management of hybrid cache-SPM memory hierarchy\, and (2) exploiting approximate computing to improve the energy efficiency of the memory hierarchy.\nWe first present the required hardware and software support for a software-assisted memory hierarchy that is composed of distributed memories which can be partitioned between caches and SPMs at runtime. We discuss our SPM APIs\, the protocol needed for data movements\, and our approach for explicit management of shared data.\nNext\, we augment caches and SPMs in this hierarchy with approximation support in order to improve the energy efficiency of the memory subsystem when running approximate programs.\nFinally\, we discuss a quality-configurable memory approximation strategy using formal control theory that adjusts the level of approximation at runtime depending on the desired quality for the program’s output. \n 
URL:https://www.cecs.uci.edu/event/software-assists-to-on-chip-memory-hierarchy-of-manycore-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171114T080000
DTEND;TZID=America/Los_Angeles:20171115T170000
DTSTAMP:20231026T194430Z
CREATED:20191126T204419Z
LAST-MODIFIED:20231026T194430Z
UID:15648-1510646400-1510765200@www.cecs.uci.edu
SUMMARY:Amir Rahmani Won Best Paper Award at MobiHealth 2017
DESCRIPTION:At the 7th EAI International Conference on Wireless Mobile Communication and Healthcare (MobiHealth) between November 14-15\, 2017\, in Vienna\, Austria\, Professor Amir Rahmani won the Best Paper Award with paper “Enhancing the Self-Aware Early Warning Score System through Fuzzified Data Reliability Assessment’. Congrats Prof. Rahmani!
URL:https://www.cecs.uci.edu/event/amir-rahmani-won-best-paper-award-at-mobihealth-2017/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171107T150000
DTEND;TZID=America/Los_Angeles:20171107T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190701Z
LAST-MODIFIED:20231011T190708Z
UID:14499-1510066800-1510070400@www.cecs.uci.edu
SUMMARY:"Network Resource Management in Cyber-Physical Systems"
DESCRIPTION:Title: “Network Resource Management in Cyber-Physical Systems”\nSpeaker: Dr. Xiabo Sharon Hu\, University of Notre Dame\, USA \nDate and Time: Friday\, November 17\, 2017 at 2:00PM-3:00PM \nLocation: ICS 432 \nAbstract: \nA cyber-physical system (CPS) is a system built from close integration of computational fabrics and physical components. Examples of such systems include avionic systems\, industrial control and civil infrastructure monitoring. In a CPS\, sensors and actuators are used to monitor and control the physical components while the computational fabrics determine the control values for the actuators based on the sensed data. All CPSs require timely delivery of sensed data from sensors to the computing fabrics and control signals from the computing fabrics to actuators. Managing the limited resources (e.g.\, computation power and communication bandwidth) to meet the timing requirements in a CPS is a challenging task. Even more challenging is that CPSs should degrade gracefully in the presence of various external disturbances such as failure in critical civil infrastructures and malicious attacks. \nIn this talk\, I first give a general introduction of WNCSs and the challenges that they present to network resource management. In particular\, I will discuss the complications due to external disturbances and the need for dynamic data-link layer scheduling. I then highlight our recent work that aims at tackling this challenge. Our work balances the scheduling effort between a gateway (or access points) and the rest of the nodes in a network. It paves the way towards decentralized network resource management in\norder to achieve scalability. Experimental implementation on a wireless test bed further validates the applicability of our proposed research. I will end the talk outlining our on-going effort in this exciting and growing area of research. \nXiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana\, USA. Her research interests include low-power system design\, real-time embedded systems\, circuit and architecture design with emerging technologies\, and hardware/software co-design. She has published more than 300 papers in these areas\, and received the Best Paper Award from the Design Automation Conference in 2001 and from the IEEE Symposium\non Nanoscale Architectures in 2009. She is the General Chair of Design Automation Conference in 2018. She is an Associate Editor for ACM Transactions on Cyber- Physical Systems\, and also served as Associate Editor for IEEE Transactions on VLSI\, etc. Sharon Hu is a Fellow of the IEEE. \nBiography: \nXiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana\, USA. She also holds a joint appointment in the department of Electrical Engineering at the same university. She received B.S. degree from Tianjin University\, China\, M.S. degree from Polytechnic University of New York\, and Ph.D. degree from Purdue University. She worked for General Motors Research Labs for almost 4 years before she started her academic career. Between 1993 and 1996\, she was an assitant professor in the department of Electrical and Computer Engineering at Western Michigan University\, Kalamazoo\, Michigan\, USA. \nHer research interests include analysis and design of low power\, real-time\, and embedded systems\, computing with emerging technologies\, and computational medicine. She has published more than 200 referred papers in these areas and received numerous research grants from both the U.S. government agencies and private industry. She received the CAREER award from U.S. National Science Foundation in 1997. She received the Best Paper Award from the ACM/IEEE Design Automation Conference in 2001 and from the IEEE Symposium on Nanoscale Architectures in 2009. Another paper of hers was named one of “The Most Influential Papers of 10 Years Design\, Automation\, and Test in Europe Conference (DATE)”. \nSharon is currently Associate Editor for ACM Transactions on Embedded Computing and Co-Chair of the Technical Program Committee of 2014 Design Automation Conference (DAC). She also served as Associate Editor for IEEE Transactions on VLSI and ACM Transactions on Design Automation of Electronic Systems. She has served as guest editors for several different journals/magazines such as the IEEE Computer Magazine and IEEE Transactions on Industrial Informatics. She was the Technical Program Co-Chair of the 9th International Symposium on Hardware/Software Codesign (CODES’2001) and the General Co-Chair of the same conference in 2002. She also served or is serving on the program committee of a number of conferences such as Design Automation Conference (DAC)\, International Conference on Computer-Aided Design (ICCAD)\, Design\, Automation and Test in Europe Conference )DATE)\, IEEE Real-Time Systems Symposium (RTSS)\, and IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)\, etc. \nAt the University of Notre Dame\, Sharon had been the Director of Graduate Studies for 10 years in the department of Computer Science and Engineering\, and was Senior Assistant Provost for ND International between 2012–2013. Currently\, she is the Associate Dean for Professional Development at the Graduate School. \n \n 
URL:https://www.cecs.uci.edu/event/network-resource-management-in-cyber-physical-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171107T150000
DTEND;TZID=America/Los_Angeles:20171107T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190701Z
LAST-MODIFIED:20231011T190708Z
UID:14500-1510066800-1510070400@www.cecs.uci.edu
SUMMARY:CECS Evening Reception in Association with ICCAD
DESCRIPTION:This event will take place on the UCI campus on Sunday\, November 12\, after 4pm.\nLocation: 6th floor of Donald Bren Hall\, building 314 on the UCI campus map (https://communications.uci.edu/documents/pdf/UCI_16_map_campus_core.pdf) \nTentative agenda: \n5pm  –  Welcome by Prof. Fadi Kurdahi (CECS Director) \n–  Opening Address\, Dr. Sanjiv Narayan (MC) \n–  Speakers:\nProf. Wolfgang Rosenstiel (University of Tuebingen\, Germany)\nProf. Frank Vahid (University of California\, Riverside)\nProf. Yale N. Patt (The University of Texas at Austin)\nProf. Rainer Doemer (University of California\, Irvine) \n–  Toast and cake cutting \n6pm  –  Socializing \nIn order to get to the event location\, we suggest to share a ride with Uber or Lyft. Please use this as the target address: \nDonald Bren Hall (DBH)\,\nUniversity of California\, Irvine\nEngineering Ct\,\nIrvine\, CA 92617 \nDriving Directions: \nIf you are driving to the event\, we suggest putting the following into your GPS navigation software (or Anteater Dr & E Peltason Dr intersection): \nAnteater Parking Structure\,\nIrvine\, California 92697 \nGeneral driving directions from ICCAD (Irvine Marriot): \n\nProceed south on Von Karman Ave.\nTurn left onto Campus Dr.\nTurn right onto E Peltason Dr.\nTurn right into the parking structure at Anteater Dr.\n\nFrom there\, DBH is just a short walk west of the structure. \n \nWe look forward to meeting you at the reception this Sunday afternoon! \nSunny greetings from Irvine\, \nCECS Event Organizing Committee
URL:https://www.cecs.uci.edu/event/cecs-evening-reception-in-association-with-iccad/
CATEGORIES:Other Events
ATTACH;FMTTYPE=image/gif:https://cecs.uci.edu/files/2023/10/aps-to-dbh-x5trbf.tmp_.gif
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171106T150000
DTEND;TZID=America/Los_Angeles:20171106T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190700Z
LAST-MODIFIED:20231011T190708Z
UID:14497-1509980400-1509984000@www.cecs.uci.edu
SUMMARY:“ThirdEye: Visual Assist for Grocery Shopping”
DESCRIPTION:Title: “ThirdEye: Visual Assist for Grocery Shopping”\nSpeaker: Prof. Vijaykrishnan Narayanan\, Pennsylvania State University\, USA \nDate and Time: Wednesday\, November 15\, 2017 at 11:00AM-12:00PM \nLocation: 2430 Engineering Hall \nAbstract: \nShopping is widely considered as a relaxing leisure activity. However\, grocery shopping can be a frustrating experience for those with visual impairment. While getting to a grocery shop itself is not as much of a challenge for them\, locating and picking the items in the grocery shelf becomes a task as challenging as picking a needle from the haystack. Imagine picking up five items for your dinner recipe from a typical grocery store in the US that carries around 35\,000 unique items and can have more than 30 aisles spanning 45\,000 square meters. This talk will showcase synergistic advances in algorithms\, architectures and interface design for assisting those with visual impairment to do shopping. We will specifically focus on new non-boolean hardware approaches to significantly impact the energy-efficiency of the overall system. \nBiography: \nVijay Narayanan is a Distinguished Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is the director of the NSF Expeditions-in-Computing Program on Visual Cortex on Silicon and a thrust leader for the DARPA-MARCO LEAST Center. He has published more than 400 papers and won several awards in recognition of his research in power-aware systems\, embedded systems and computer architecture. He is a fellow of IEEE and ACM. \n 
URL:https://www.cecs.uci.edu/event/thirdeye-visual-assist-for-grocery-shopping/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T185012Z
CREATED:20231031T185012Z
LAST-MODIFIED:20231031T185012Z
UID:15732-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Mohsen Imani Received Best Paper Nomination at ACM DAC 2019
DESCRIPTION:Assistant Professor Mohsen Imani received Best Paper Nomination at ACM Design Automation Conference 2019 for his research paper titled\, “Locality-based Encoding for Energy-Efficient Brain-Inspired Hyperdimensional Computing.” Congrats Prof. Imani!
URL:https://www.cecs.uci.edu/event/mohsen-imani-received-best-paper-nomination-at-acm-dac-2019/
CATEGORIES:Awards
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171031T080000
DTEND;TZID=America/Los_Angeles:20171031T170000
DTSTAMP:20231031T182948Z
CREATED:20231031T182948Z
LAST-MODIFIED:20231031T182948Z
UID:15688-1509436800-1509469200@www.cecs.uci.edu
SUMMARY:Quoc-Viet Dang Won Dean’s Honoree for Excellence in Undergraduate Teaching
DESCRIPTION:Assistant Professor Quoc-Viet Dang won Dean’s Honoree for Excellence in Undergraduate Teaching under the Henry Samueli School of Engineering for his excellence in undergraduate teaching and engaging in pedagogical research in the field of e-learning and data analysis. Congrats!
URL:https://www.cecs.uci.edu/event/quoc-viet-dang-won-deans-honoree-for-excellence-in-undergraduate-teaching/
CATEGORIES:Awards
END:VEVENT
END:VCALENDAR