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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150709T150000
DTEND;TZID=America/Los_Angeles:20150709T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14436-1436454000-1436457600@www.cecs.uci.edu
SUMMARY:Reviving Processing-in-Memory for Large Data Workload on Existing Computer Architecture
DESCRIPTION:Speaker:  Professor Sungjoo Yoo\, Computing and Memory Architecture Lab\, Seoul National University \nTitle:  Reviving Processing-in-Memory for LArge Data Workload on Existing Computer Architecture \nDate:  Tuesday\, July 14\, 2015 \nTime:  11:00 AM \nLocation:  Donald Bren Hall 3011 \nHost:  Nikil Dutt \nAbstract:  Processing-in-memory (PIM) is rebounding from its unsuccessful attempts in 1990s due to two main reasons\, recent advances in 3D stacking technologies and emerging large data workload.  In this talk\, we present two of our recent works\, PIM for large data workload and combining PIM with the existing computer architecture.\nGraph data are becoming more and more popular in many areas such as machine learning\, social network analysis\, etc.  Graph computation is to process a query to the graph database\, e.g.\, finding the most popular personality.  Graph computation is characterized by computation parallelism (per-vertex parallel computation) and significant random memory accesses (to neighbor vertices).  The conventional architecture is not well suited for this type of workload.  We present a programmable PIM accelerator for large-scale graph processing called Tesseract.  Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth\, (2) an efficient method of communication between different memory partitions\, and (3) a programming interface that reflects and exploits the unique hardware design.  It also includes two hardware prefecthers specialized for memory access patterns of graph processing\, which operate base on the hints provided by our programming model.\nIn order to make best use of PIM in more areas\, it is required to integrate the PIM architectures with existing systems in a seamless manner.  The current PIM proposals lack due to two common characteristics: unconventional programming models for in-memory computation units (as programmable co-processors) and lack of ability to utilize large on-chip caches.  We propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data.  The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions\, which we call PIM-enabled instructions\, to invoke in-memory computation.  This allows PIM operations to be interoperable with existing programming models\, cache coherence protocols\, and virtual memory mechanisms with no modification. \nView Details
URL:https://www.cecs.uci.edu/event/reviving-processing-in-memory-for-large-data-workload-on-existing-computer-architecture/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150528T150000
DTEND;TZID=America/Los_Angeles:20150528T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14435-1432825200-1432828800@www.cecs.uci.edu
SUMMARY:Computational Neuroscience for Technology: Event-based Vision Sensors and Information Processing
DESCRIPTION:Speaker:  Prof. Jörg Conradt\nTitle:  Computational Neuroscience for Technology: Event-based Vision Sensors and Information Processing \nDate:  Tuesday\, June 2\, 2015 \nTime:  3:00 p.m. \nLocation:  Donald Bren Hall 4011 \nHost:  Jeff Krichmar and Nikil Dutt \nAbstract:  \nIn recent decades the field of Computer Vision has developed sophisticated algorithms for problems such as object tracking or motion extraction based on sequences of high-resolution camera images. Applying such algorithms in real-time robotics reveals an inherent problem: they typically require high data bandwidth and high processing power\, which results in substantial computing machinery and/or delayed processing of data. As part of an optimized biological solution for vision\, our brain developed retinal receptor cells that largely respond with asynchronous events (“neural spikes”) to temporal changes of brightness. Such encoding of visual information substantially reduces the amount of transmitted data and simultaneously increases temporal precision. \nRecently “silicon retinas” have been developed as specialized vision sensors to provide such neuro-inspired vision input for technical systems. Visual information obtained from these sensors differs substantially from traditional sequences of images\, which requires an “event-based” redesign of computer vision algorithms. This talk introduces the neuro-inspired vision sensors and presents event-based algorithms for applications such as real-time computation of optic flow and visual object tracking at high update rates on minimalistic computing hardware. \nView Details
URL:https://www.cecs.uci.edu/event/computational-neuroscience-for-technology-event-based-vision-sensors-and-information-processing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150512T150000
DTEND;TZID=America/Los_Angeles:20150512T160000
DTSTAMP:20231011T190510Z
CREATED:20231011T190510Z
LAST-MODIFIED:20231011T190510Z
UID:14431-1431442800-1431446400@www.cecs.uci.edu
SUMMARY:Design Technologies for Embedded Multiprocessor Systems-on-Chip
DESCRIPTION:Speaker:  Prof. Rainer Leupers \nTitle: Design Technologies for Embedded Multiprocessor Systems-on-Chip \nDate: Thursday\, April 9\, 2015 \nTime: 11:00am \nLocation: Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Mohammad Al Faruque \nAbstract:  \nThe trend towards Multicore and even Manycore architectures affects virtually all areas of computing today. Especially in the mobiles and consumer domains\, an extremely high architectural efficiency (MIPS/Watt) is required. In order to manage the complexity of multi-billion transistor IC designs with dozens of heterogeneous processing engines\, advanced Electronic System Level (ESL) tools are required. ESL can be roughly subdivided into four categories: architecture modeling and optimization\, application SW mapping\, simulation and verification\, and efficient IP block design. After a general introduction to embedded MPSoC (Multiprocessor Systems-on-Chip) architectures and ESL technologies\, this seminar talk will cover selected aspects from the above four domains\, in particular ESL power estimation\, embedded multicore SW development\, fast virtual platforms\, and application-specific processor design. \nFor more information\, click here.
URL:https://www.cecs.uci.edu/event/design-technologies-for-embedded-multiprocessor-systems-on-chip/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150304T150000
DTEND;TZID=America/Los_Angeles:20150304T160000
DTSTAMP:20231011T190510Z
CREATED:20231011T190510Z
LAST-MODIFIED:20231011T190510Z
UID:14429-1425481200-1425484800@www.cecs.uci.edu
SUMMARY:Architectural Support for Security in Emerging Platforms
DESCRIPTION:Speaker: Nael Abu-Ghazaleh \nTitle: Architectural Support for Security in Emerging Platforms \nDate: Wednesday\, March 4\, 2015 \nTime: 10:00am \nLocation: Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Fadi Kurdahi \nAbstract:  \nComputer systems are facing a growing threat from increasingly motivated\, organized and sophisticated attackers.  The problem is complicated by the rapid evolution that computing platforms are experiencing towards mobile and embedded devices\, as well as many-core systems\, distributed systems\, virtualization and clouds.  These emerging platforms offer new system and use models and therefore are subject to new vulnerabilities and threat models.  This talk motivates the role that computer architecture must play in securing current and emerging systems.  I will define this role spanning three primary directions: (1) new security models for protecting not only systems but also applications; (2) architecture support for monitoring to improve resilience to attacks\, but also to rapidly detect and contain successful attacks; and (3) Security for emerging architectures.  I will animate each of these directions with examples from our recent work.
URL:https://www.cecs.uci.edu/event/architectural-support-for-security-in-emerging-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150304T150000
DTEND;TZID=America/Los_Angeles:20150304T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14423-1425481200-1425484800@www.cecs.uci.edu
SUMMARY:Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks
DESCRIPTION:Speaker: Francesco Regazzoni \nTitle: Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks \nDate: Tuesday\, March 3\, 2015 \nTime: 2:00pm \nLocation: Donald Bren Hall 3011 \nHost: Nikil Dutt & Rosario Cammarota \nAbstract:  \nPhysical attacks exploit the physical weaknesses of cryptographic devices to reveal the secret information stored on them. Countermeasures against these attacks are often considered only in the later stages of the full design flow\, and applied manually by designers with strong security expertise. This approach\, however\, negatively affects the robustness\, the cost\, and the production time of secure devices. \nIn view of this increasingly relevant problem\, it is crucial to address the design challenges associated with the proliferation of physical attacks\, developing a methodology to automate the design and the verification of secure embedded systems. \nThis talk focuses on one type of physical attacks\, the differential power analysis (DPA)\, and presents the design and the implementation of the infrastructure needed to enable the automatic application and verification of DPA countermeasures.
URL:https://www.cecs.uci.edu/event/towards-the-automatic-application-and-verification-of-countermeasures-against-physical-attacks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150212T150000
DTEND;TZID=America/Los_Angeles:20150212T160000
DTSTAMP:20231011T190458Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190458Z
UID:14419-1423753200-1423756800@www.cecs.uci.edu
SUMMARY:Inertial and Bio-potential-based Wearable Computers: Algorithms and Applications
DESCRIPTION:Title: Inertial and Bio-potential-based Wearable Computers: Algorithms and Applications\nSpeaker:  Professor Roozbeh Jafari \nDate/Time:  Thursday\, February 12\, 2015\, 11:00am to 12:00pm \nLocation:  Donald Bren Hall 4011 \nHost: Eli Bozorgzadeh \nAbstract:  \nWearable computers bring to fruition many new opportunities to continuously monitor human body with sensors placed on body; whether they are intended to detect an early onset of a disease\, assess human performance or determine the effectiveness of a treatment. In the past few years\, the community has observed a large number of applications leveraging wearable computers. There are\, however\, a number of fundamental challenges that need to be addressed before realizing the true ubiquitous use of the wearable computing systems. \nIn the first half of the talk\, we highlight several inertial-based wearable applications including systems capable of monitoring activities of daily living (ADLs) and home exercises for senior citizen. We focus on a class of signal processing algorithms that provide extreme robustness leveraging accelerometers and gyroscopes. We present our results on ADLs and highlight our efforts in line with data dissemination for the scientific community. In the second half of the presentation\, we focus on dry-contact electroencephalography (EEG). We present our brain-computer interface (BCI) system developed for intensive care units leveraging dry-contact EEG. We outline several components of EEG systems and focus on skin-electrode contact noise. \nWe provide techniques for noise reduction including contact reconfiguration along with experimental verifications. We provide concluding remarks on the trends of wearable computing technology development and future directions.
URL:https://www.cecs.uci.edu/event/inertial-and-bio-potential-based-wearable-computers-algorithms-and-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150210T150000
DTEND;TZID=America/Los_Angeles:20150210T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14420-1423580400-1423584000@www.cecs.uci.edu
SUMMARY:Design Automation of Things: Power Consumption Characterization\, Modeling and Estimation of Electric Vehicles
DESCRIPTION:Title: Design Automation of Things: Power Consumption Characterization\, Modeling and Estimation of Electric Vehicles\nSpeaker:  Professor Naehyuck Chang \nDate/Time:  Tuesday\, February 10\, 2015\, 2:00pm to 3:00pm \nLocation:  Harut Barsamian Colloquia Room (EH 2430) \nHost: Nikil Dutt \nAbstract:  \nRapid electric vehicle (EV) penetration gives a threatening challenge in electric energy generation. An 1\,814 kg curb weight full electric vehicle driving 18\,129 km/year consumes electricity energy equivalent to 74% of the total residential electricity use per person in the US. This implies that 27% more nationwide electricity generation is needed when 70% of passenger vehicles are replaced with EVs. \nThis talk introduces the first step toward systematic EV design-time and runtime optimization. We develop instantaneous power consumption modeling of an EV by the curb weights\, speed\, acceleration\, road slope\, passenger and cargo weights\, motor capacity\, and so on\, as a battery discharge model. The model also considers the onboard charger\, regenerative braking and so on\, as a battery charge model. To insure model fidelity\, we fabricate a lightweight custom EV\, perform extensive measurement\, and derive model coefficients using multivariable regression analysis. We estimate the EV instantaneous power consumption of a given speed and route profiles and verify the estimation fidelity with a real test run data. This talk will also cover the on-going project for the next version electric vehicle with four-wheel drive capability. \n 
URL:https://www.cecs.uci.edu/event/design-automation-of-things-power-consumption-characterization-modeling-and-estimation-of-electric-vehicles/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150210T150000
DTEND;TZID=America/Los_Angeles:20150210T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14422-1423580400-1423584000@www.cecs.uci.edu
SUMMARY:Connected Context Computing for Smart IoT
DESCRIPTION:Speaker: Jane Yung-jen Hsu \nTitle: Connected Context Computing for Smart IoT \nDate: Tuesday\, February 10\, 2015 \nTime: 3:30pm \nLocation: Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Professor Kwei-Jay Lin \nAbstract:  \nWe are witnessing the explosion of connected devices\, or the so-called Internet of Things\, in our everyday lives. This new trend has created new opportunities to monitor human activities and to configure environments for comfort\, security\, or energy savings. In the US\, buildings account for roughly 40% of total energy usage\, with major contributions from the cooling demands. While most people have no intention of wasting energy\, they are often unaware of the energy footprint of their daily routines. Activity recognition is a key capability for a smart environment to offer timely services and intelligent interactions with people. \nIn this talk\, I will introduce connected context computing and its significance in enabling our vision of smart IoT. In particular\, I will share our experience on monitoring the Computer Science building on NTU campus to improve its air conditioning and space utilization. First\, an agent-based HVAC service is designed to analyze cooling demands and wastes. Second\, experiments on SweetFeedback are conducted to encourage energy-saving behaviors. Third\, crowd sourcing cyber-physical agents are deployed to acquire status labels for activity recognition from people situated in the environment. Â Our experiments showed that context computing\, predictive analytics\, and proactive control are the fundamental building blocks for a smart IoT framework that can SCALE (Sense\, Communicate\, Analyze\, Learn\, Expect and Effect). \n 
URL:https://www.cecs.uci.edu/event/connected-context-computing-for-smart-iot/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14404-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:The Delft Reconfigurable VLIW Processor
DESCRIPTION:Speaker: Prof. Stephan Wong\, Computer Engineering Laboratory\, Delft University of Technology\, NetherlandsTitle: The Delft Reconfigurable VLIW ProcessorDate: Tuesday\, March 26\, 2013Time: 2:00pm – 3:00pmLocation: 2111 Engineering Hall \nHost: Prof. Fadi Kurdahi \nView Details \nAdditional information
URL:https://www.cecs.uci.edu/event/the-delft-reconfigurable-vliw-processor/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14405-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Functionality\, Performance\, and Power Consumption Challenges in Smartphones
DESCRIPTION:Speaker: Prof. Sung-Soo Lim\, Kookmin University\, South KoreaTitle: Functionality\, Performance\, and Power Consumption Challenges in SmartphonesDate: Friday\, April 12\, 2013Time: 11:00am – 12:00pmLocation: Donald Bren Hall 6011 \nHost: Prof. Eli Bozorgzadeh \nView Details
URL:https://www.cecs.uci.edu/event/functionality-performance-and-power-consumption-challenges-in-smartphones/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14406-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Models and Architectures for Heterogeneous System Design
DESCRIPTION:Speaker: Prof. Andreas Gerstlauer\, University of Texas\, AustinTitle: Models and Architectures for Heterogeneous System DesignDate: Monday\, May 6\, 2013Time: 11:00am – 12:00pmLocation: Harut Barsamian Colloquia Room (2430 Engineering Hall) \nHost: Prof. Rainer Dömer \nView Details
URL:https://www.cecs.uci.edu/event/models-and-architectures-for-heterogeneous-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130531T150000
DTEND;TZID=America/Los_Angeles:20130531T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14407-1370012400-1370016000@www.cecs.uci.edu
SUMMARY:Evaluating GALS Systems for System Integration-Outlook and Future Prospects
DESCRIPTION:Speaker: Dr. Milos KrsticDate: Friday May 17\, 2013Time: 2:00pm – 3:00pmLocation: Donald Bren Hall 4011 \nHost: Dr. Steffen Peter \nView Details
URL:https://www.cecs.uci.edu/event/evaluating-gals-systems-for-system-integration-outlook-and-future-prospects/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130221T150000
DTEND;TZID=America/Los_Angeles:20130221T160000
DTSTAMP:20231011T190321Z
CREATED:20231011T190321Z
LAST-MODIFIED:20231011T190321Z
UID:14396-1361458800-1361462400@www.cecs.uci.edu
SUMMARY:A Thermal Perspective of Dependability in Systems on Chip
DESCRIPTION:Speaker: Prof. Jörg Henkel\, Karlsruhe Institute of Technology\, GermanyLocation: Harut Barsamian Colloquia Room (EH 2430)Date/Time: Monday\, February 25\, 2013\, 11:00am to 12:00pmView Details
URL:https://www.cecs.uci.edu/event/a-thermal-perspective-of-dependability-in-systems-on-chip/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130220T150000
DTEND;TZID=America/Los_Angeles:20130220T160000
DTSTAMP:20231011T192456Z
CREATED:20231011T190320Z
LAST-MODIFIED:20231011T192456Z
UID:14395-1361372400-1361376000@www.cecs.uci.edu
SUMMARY:Introduction to Consumer Computing
DESCRIPTION:Speaker:  Prof. Sinisa SrbljicLocation: Harut Barsamian Colloquia Room (EH 2430)Time/Date: Monday\, February 4\, 2013\, 11:00am-12:00pmView Details
URL:https://www.cecs.uci.edu/event/introduction-to-consumer-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120924T150000
DTEND;TZID=America/Los_Angeles:20120924T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14390-1348498800-1348502400@www.cecs.uci.edu
SUMMARY:Cyber-Physical Systems at Small and Large Scales
DESCRIPTION:Speaker:  Prof. Marilyn Wolf\, Georgia Institute of TechnologyLocation:  4011 Donal Bren Hall\nDate/Time: Friday\, September 28\, 2012\, 2:00-3:00PM\nView Details
URL:https://www.cecs.uci.edu/event/cyber-physical-systems-at-small-and-large-scales/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120906T150000
DTEND;TZID=America/Los_Angeles:20120906T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14389-1346943600-1346947200@www.cecs.uci.edu
SUMMARY:Flexible Error Handling for Resource-Constrained Embedded Systems
DESCRIPTION:Speaker:  Dr. Michael Engel\, TU Dortmund University\, GermanyLocation:  2430 Engineering Hall\nDate/Time:   Friday\, August 31\, 2012\, 2:30-4:00PM\nView Details
URL:https://www.cecs.uci.edu/event/flexible-error-handling-for-resource-constrained-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120627T150000
DTEND;TZID=America/Los_Angeles:20120627T160000
DTSTAMP:20231011T181236Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T181236Z
UID:14257-1340809200-1340812800@www.cecs.uci.edu
SUMMARY:Addressing Supply Chain Security with Split Manufacturing
DESCRIPTION:Addressing Supply Chain Security with Split Manufacturing\n\n\n\n\nSpeaker\n\n\nDr. Ted Huffmire\nNaval Postgraduate School\, Monterey\, California\n\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDBH 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 27\, 2012\nSeminar begins at 11:00am\, Refreshment at 10:45am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nSecurity is an essential design goal in computer architecture\, and security is a concern throughout the entire lifecycle of a system. The process of designing hardware requires trusting intellectual property (IP) cores and computer-aided design (CAD) tools developed by third parties\, as well as the fabrication\, packaging\, assembly\, and delivery of the final system. Valuable IP is vulnerable to theft and modification during tape-out\, even if a perfect design free of security flaws is sent to the foundry. Of course\, no design is ever perfect\, and having a trusted foundry does not solve the problem of flawed designs. Furthermore\, the trusted foundry may not have the capability to deliver the most aggressive technology node\, volume\, yield\, or cost. Even the extraordinary step of building everything from scratch in-house\, including all of the tool chains\, both digital and analog\, is not guaranteed to result in a trustworthy design.  \nThis short\, informal\, seminar-style talk will explore three split manufacturing approaches for addressing hardware supply chain security: reconfigurable hardware\, 2D IC split manufacturing\, and 3D IC split manufacturing. Reconfigurable hardware allows the design to be loaded onto a field-programmable gate array (FPGA) device in a secure facility after fabrication. With 2D IC split manufacturing\, different metal layers of the same wafer are fabricated in different foundries\, one of which is a trusted foundry. With 3D IC split manufacturing\, two or more individual die are fabricated in different foundries\, one of which is a trusted foundry\, and then assembled in a trusted facility. The challenges and opportunities of each of these approaches will be compared and contrasted\, as well as the viability of split manufacturing in general.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nTed Huffmire is an Assistant Professor of Computer Science at the Naval Postgraduate School in Monterey\, California. His research spans both computer security and computer architecture\, focusing on hardware-oriented security and the development of policy enforcement mechanisms for application-specific devices. He has a Ph.D. in computer science from the University of California\, Santa Barbara. He is a member of the IEEE and the ACM. The views presented in this talk are those of the speaker and do not necessarily reflect the views of the United States Department of Defense
URL:https://www.cecs.uci.edu/event/addressing-supply-chain-security-with-split-manufacturing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120612T150000
DTEND;TZID=America/Los_Angeles:20120612T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181235Z
LAST-MODIFIED:20231011T192031Z
UID:14254-1339513200-1339516800@www.cecs.uci.edu
SUMMARY:Architectural Modeling of Embedded Systems - Challenges and Opportunities
DESCRIPTION:Architectural Modeling of Embedded Systems – Challenges and Opportunities\n\n\n\n\nSpeaker\n\n\nDr. Achim Rettberg\nCarl von Osseitzky University Oldenburg\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Rainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall 3216\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 12\, 2012\nColloquium begins at 2:00PM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nToday embedded system design has to cover the increasing complexity and has to fulfil requirements. With traditional design methods the time-to-market is to long. New design methods as model-based design offers the reduction of product development time\, but it requires a different development process. This talk will give an overview of model-based design and show the complexity designers have to cope with. The idea to realize the system based on a virtual platform will also be covered in the talk. The reference technology platform (RTP) proposed and developed at OFFIS Institute (Oldenburg\, Germany) will be presented. The RTP gives the designer an excellent overview of the system and allows requirement coverage and analysis.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nACHIM RETTBERG was born in Einbeck\, Germany. He received his M.S. (Dipl.-Inform.) in computer science and economics in 1997 and his Ph. D. (Dr. rer. nat.) degree in 2006 from the University of Paderborn\, Germany\, where he studied computer science and economics. From 1992 until 1997 he was employed as a working student for the University of Paderborn and C-LAB. From 1997 until 2000 he worked at C-LAB in industrial projects together with dSPACE and Siemens. From 2001 until 2006 he worked as a Ph.D. student and researcher for the C-LAB in the field of embedded system design. Afterwards he worked from 2007 until 2008 as Post-Doc at C-LAB and managed EU-Projects. In 2008 he became professor of complex integrated systems/embedded systems at the Computer Science department at Carl von Ossietzky University Oldenburg. Prof. Rettberg is founder and General Chair of the International Embedded Systems Symposium (IESS). Furthermore\, he is active in several conference/workshop committees and reviewers for journals. Prof. Rettberg is author and co-author of several scientific books\, journal articles and conference papers. His general research interests are model-based design\, real-time systems and HW/SW architectures. He is chairman of the IFIP working group 10.2 for embedded systems.
URL:https://www.cecs.uci.edu/event/architectural-modeling-of-embedded-systems-challenges-and-opportunities/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120531T150000
DTEND;TZID=America/Los_Angeles:20120531T160000
DTSTAMP:20231011T182435Z
CREATED:20231011T182435Z
LAST-MODIFIED:20231011T182435Z
UID:14258-1338476400-1338480000@www.cecs.uci.edu
SUMMARY:Flash Memory Management for Embedded Systems
DESCRIPTION:Prof. Zili Shao\n	Hong Kong Polytechnic University\n	DBH 3011\n	Seminar\, May 31\, 2012\n	Abstract
URL:https://www.cecs.uci.edu/event/flash-memory-management-for-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120502T150000
DTEND;TZID=America/Los_Angeles:20120502T160000
DTSTAMP:20231011T182435Z
CREATED:20231011T182435Z
LAST-MODIFIED:20231011T182435Z
UID:14259-1335970800-1335974400@www.cecs.uci.edu
SUMMARY:COMS Process Variations: A "Critical Operation Point" Hypothesis"
DESCRIPTION:Dr. Janak H. PatelUniversity of Illinois at Urbana-Champaign\nDBH 3011\nDistinguished Lecture\, May 2\, 2012\nAbstract
URL:https://www.cecs.uci.edu/event/coms-process-variations-a-critical-operation-point-hypothesis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120301T150000
DTEND;TZID=America/Los_Angeles:20120301T160000
DTSTAMP:20231011T182435Z
CREATED:20231011T182435Z
LAST-MODIFIED:20231011T182435Z
UID:14260-1330614000-1330617600@www.cecs.uci.edu
SUMMARY:A Couple of Research Topics for UCI CECS Visit
DESCRIPTION:A Couple of Research Topics for UCI CECS Visit\n\n\n\n\nSpeaker\n\n\nDr. Pyung-Soo Kim\nKorea Polytechnic University\nKorea\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 1\, 2012\nSeminar begins at 2:00 PM\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk\, a couple of research topics for UCI CECS visit are presented.\nFirstly\, the finite memory structure (FMS) filter for state emstimation in state space models and its applications are briefly introduced.\nResearch issues on the application of FMS filter are introduced for mobile tracking system\, wireless sensor network\,\nbattery management system\, etc. Secondly\, as a basic principle of addressing architecture for Future Internet\, the identifer/locator split is briefly introduced. Research issues are also introduced in designing name space and name system for Future Internet based on the identifer/locator split.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nProf. Pyung-Soo Kim received the Ph.D. degree at the School of Electrical Engineering and Computer Science from Seoul National University\, Seoul\, Korea\, in 2001. From 2001 to 2005\, he was a senior researcher at the\nDigital Media R&D Center of Samsung Electronics Co. Ltd. Since 2005\, he has been with the Department of Electronics Engineering at Korea Polytechnic University\, Shiheung\, Korea. His main research interests are in the areas of system software solutions\, statistical signal processing\, wireless mobile networks\, Future Internet architecture design\, and various industrial applications.
URL:https://www.cecs.uci.edu/event/a-couple-of-research-topics-for-uci-cecs-visit/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20111027T150000
DTEND;TZID=America/Los_Angeles:20111027T160000
DTSTAMP:20231011T182436Z
CREATED:20231011T182436Z
LAST-MODIFIED:20231011T182436Z
UID:14261-1319727600-1319731200@www.cecs.uci.edu
SUMMARY:Distributed Algorithms for the Self-organization of the Scale-free Network: Statistical Mechanics Inspired Methods
DESCRIPTION:Distributed Algorithms for the Self-organization of the Scale-free Network: Statistical Mechanics Inspired Methods\n\n\n\n\nSpeaker\n\n\nDr. Jae-Hyun Park\nChung-Ang University\,\nKorea\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 3206\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 27\, 2011\nSeminar begins at 11:00 AM\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRecently\, by physicists\, it has been recognized that the scale-free network is made by a simple random process\, if a kind of bias is given to purely random state of nodes in network. Because some biased physical quantities such as the availability of nodes are observed in real networks\, we devise a distributed algorithm for the self-organization of the scale-free network from this discovery. Each node independently tries to connect to the best node which is superior to the node itself and all the nodes that had been connected\, while the node received the request accepts it if the node asked is better than all the nodes that had been connected. Because each node deterministically finds out the candidate nodes in terms of partial order\, a partial order relationship among the nodes exists. Each node working for the related algorithms uses the state information changed over time. But the node working for the proposed algorithm uses the constant observable quantity of node state so it requires only one-time broadcasting to share all the global node state data. The number of broadcast messages is tremendously diminished. We also propose a distributed algorithm for which only local node state data is used. To devise the algorithm\, we analyze the scale-free network formation problem with the Statistical Mechanics\, from which we show the insight that\, if the degree-distribution of network is the power law\, each node is adjacent to symmetric sub-graphs (or indistinguishable links).\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Jae-Hyun Park received the B.S. degree in Computer Science from Chung-Ang University\, Korea\, in 1988\, and the M.S. and Ph.D. degrees in Computer Science from the KAIST\, Taejon\, in 1991 and 1995\, respectively. >From 1991 to 1994\, as a research staff of the Satellite Research Center in KAIST\, He had developed the embedded operating system for the onboard computer of KITSAT (the first Korean satellite). Especially\, he had modified the Nucleus RTX Kernel (real-time operating system kernel) for dynamic process creation in a mission control on-board computer system. This works was published in the Proc. of AIAA/IEEE Digital Avionics Systems Conference. As his Ph.D. research\, he did work on the fault-tolerant high-performance multistage interconnection networks for ATM switching and multiprocessing\, which was published in IEEE/ACM Trans. on Networking. From 1995 to 2000\, he was with the Samsung Electronics Co.\, Korea\, where he had developed the multiprotocol label switching system over the Asynchronous Transfer Mode Switching System\, including the development of the label distribution protocol\, which was published in IEICE Trans. on Comm. He received the 1996 Best Research Paper Award-Golden Prize in 1997 and the 1997 Award of Excellence in Research and Development-Silver Prize in 1998\, all from Samsung Electronics Co. From 2000 to 2002\, he was with the School of EECS\, Yeungnam University\, Korea. Since 2002\, he has been a professor of the School of Computer Science and Engineering\, Chung-Ang University\, Korea. His current research interests include switching architectures\, self-organization\, ad hoc networks\, and scale-free networks. He is a visiting scholar at UC Irvine\, hosted by Professor Pai H. Chou from February 2011 to January 2012.
URL:https://www.cecs.uci.edu/event/distributed-algorithms-for-the-self-organization-of-the-scale-free-network-statistical-mechanics-inspired-methods/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20111018T150000
DTEND;TZID=America/Los_Angeles:20111018T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T192254Z
UID:14255-1318950000-1318953600@www.cecs.uci.edu
SUMMARY:High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement
DESCRIPTION:High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement\n\n\n\n\nSpeaker\n\n\nDr. Yuko Hara-Azumi\nRitsumeikan University\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 18\, 2011\nRefreshments at 2:30PM\, Colloquium begins at 3:00PM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThese years\, there has been a considerable interest in practical techniques to improve the yield of LSIs at little sacrifice of performance and area. Recently\, we presented a new concept device\, called Partially-Programmable Circuit (PPC)\, which consists of conventional gates\, LUTs\, and wires\, and enhances yield only by implicit logic redundancy (by partial reconfiguration of the LUTs) and redundant wires. In this talk\, a novel high-level synthesis (HLS) approach using PPC-realized resources is presented. Considering reconfiguration of the resources after fabrication\, our work aims at maximizing yield expectation.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nYuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. Currently she is a research fellow of the Japan Society for the Promotion of Science at Ritsumeikan University. Her research interests include system-level design methodology for embedded systems\, especially high-level and logic synthesis\, and task mapping technologies for many-core architectures.
URL:https://www.cecs.uci.edu/event/high-level-synthesis-using-partially-programmable-resources-for-yield-improvement/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110923T150000
DTEND;TZID=America/Los_Angeles:20110923T160000
DTSTAMP:20231011T182436Z
CREATED:20231011T182436Z
LAST-MODIFIED:20231011T182436Z
UID:14262-1316790000-1316793600@www.cecs.uci.edu
SUMMARY:Post-Silicon Patchable Hardware
DESCRIPTION:Post-Silicon Patchable Hardware\n\n\n\n\nSpeaker\n\n\nProf. Masahiro Fujita\nVLSI Design and Education Center (VDEC)\,\nThe University of Tokyo and CREST\n\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Rainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 3206\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nSeptember 23\, 2011\nSeminar begins at 2:00 PM\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWith the shorter time-to-market and the rising cost in SoC development\, the demand for post-silicon programmability has been increasing. Recently\, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However\, programmable accelerators suffers from 5?10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then\, we propose a patch compilation method from a given pair of an original design and a modified design. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nMasahiro Fujita received his Ph.D. from the University of Tokyo in 1985. He is a professor in VLSI Design and Education Center (VDEC) at the University of Tokyo. Prior to joining the University of Tokyo in 2000\, he was director of CAD for VLSI in Fujitsu Laboratories of America for 6 years. He has done innovative works in the areas of digital design verification\, synthesis\, and testing. He has authored and co-authored 10 books\, and has over 150 publications. He has been given several research awards from Japanese scientific societies. His current research interests include synthesis and verification in higher level design stages\, hardware/sfotware co-designs and also digital/analog co-designs.
URL:https://www.cecs.uci.edu/event/post-silicon-patchable-hardware/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110712T150000
DTEND;TZID=America/Los_Angeles:20110712T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14263-1310482800-1310486400@www.cecs.uci.edu
SUMMARY:Hybrid Electrical Energy Storage Systems
DESCRIPTION:Hybrid Electrical Energy Storage Systems\n\n\n\n\nSpeaker\n\n\nProf. Naehyuck Chang\nSeoul National University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 2111\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 12 \, 2011\nLecture begins at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nElectrical energy is a high-quality form of energy in the sense that it can be easily and efficiently converted into other forms of energy\, and furthermore it can be used to control other forms of energy. Unfortunately\, electricity supply and demand are typically not balanced with each other. Storage of excessive energy and compensation of the energy shortage can significantly mitigate the over-investment in the generation facilities.  \nLike memory devices\, no single type of electrical energy storage (EES) element can fulfill all the desirable requirements. Despite active research on the new EES technologies\, it is not likely to have an ultimate high-efficiency\, high- power/energy capacity\, low-cost\, and long-cycle life EES element in the near future. We propose an hybrid electrical energy storage (HEES) system that consists of two or more heterogeneous EES elements\, thereby realizing the advantages of each EES element while hiding their weaknesses. \nCompared with the conventional homogeneous EES systems\, HEES systems provide high output power and energy density as well as high power conversion efficiency and low self-discharge at a low capital cost. Cycle efficiency of a HEES system\, which is defined as the ratio of energy which is delivered by the HEES system to the load device to energy which is supplied by the power source to the HEES system\, is one of the most important factors in determining the overall operational cost of the system. \nWe formulate the HEES management problems and project them into computer memory system design and management. We break the HEES management problems into charge allocation into different banks of EES elements\, charge replacement (i.e.\, discharge) from different banks of EES elements\, and charge migration from one bank to another bank of EES elements. Even a hybrid EES system cannot achieve high cycle efficiency if their storage banks have a fixed power and voltage rating because the optimal power capacity and voltage rating varies by the application and the state of charge (SoC) of the storage bank. Bank reconfiguration dynamically changes the array structure of an EES bank and maximizes the efficiency. \nIn this talk\, we start from introduction to the concept of HEES systems including EES element characteristics and power converter characteristics. The main body of this talk is charge allocation\, migration\, optimization\, and bank reconfiguration. The HEES research is recently brought up\, and thus there are a lot of important open problems. We will conclude this talk with remarks on the future work.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nNaehyuck Chang is a Full Professor in Dept. of Electrical Engineering and Computer Science\, Seoul National University\, Korea. He was a Visiting Associate Professor at Arizona State University in 2005\, and a Visiting Professor at University of Southern California in 2009-2010. He serves (and served) as Technical Program Committee of major EDA and embedded systems conferences and symposia including DAC\, ICCAD\, ISLPED\, DATE\, ASP-DAC\, GLS-VLSI\, ISQED\, PATMOS\, ESTIMedia\, ICCD\, and so on.  He served as the TPC Co-Chair of RTCSA in 2007\, ISLPED in 2009\, and ESTIMedia in 2009 and 2010. He was Vice GC of ISLPED 2010 and is General Co-Chair of ISLPED 2011. He is also General Chair of ESTIMedia in 2011. He will serve as a TPC Co-Chair of CODES+ISSS 2012. He is an Associate Editor of IEEE TCAD and ACM TODAES\, and editorial board members of JOLPE and JEC. He is a guest editor of ACM TODAES in 2011 and TECS for low-power design and embedded multi-media systems in 2010 and 2011. He also serves as the Chair of ACM SIGDA Low-Power Technical Committee\, ASP-DAC SIGDA Representative and ACM SIGDA Executive Committee (Technical Activity Chair). He is a Senior Member of ACM and IEEE.
URL:https://www.cecs.uci.edu/event/hybrid-electrical-energy-storage-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110603T150000
DTEND;TZID=America/Los_Angeles:20110603T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T192031Z
UID:14256-1307113200-1307116800@www.cecs.uci.edu
SUMMARY:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund
DESCRIPTION:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund\n\n\n\n\nSpeaker\n\n\nPeter Marwedel\nChair for Embedded Systems\nTU Dortmund/Informatik 12 + ICD\nDortmund\, Germany\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nRainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 3\, 2011\nRefreshments at 9:30 am\, Lecture begins at 10:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe group headed by Dr. Marwedel focuses on the design of efficient embedded systems. The talk will provide an overview of the research performed in this group:  \n\nEmbedded systems connected to the physical environment must meet timing constraints. Typically\, timing verification is performed after software generation\, possibly leading to many design iterations until timing constraints are finally met. In order to avoid such loops\, compilers can be made timing-aware. An approach for such integration will be presented together with some results.\nThe next part of the talk will be about addressing the memory wall problem. In particular\, the use of energy-efficient and timing-predictable scratchpad memories will be presented. Results on the worst-case execution time aware compilation for an automotive application using scratchpad memories will be included.\nThe final part will cover other research projects in the DAES group. These include two projects of the collaborative research project on resource constrained machine learning (SFB 876). In the first project\, resource-efficient image analysis for an advanced real-time virus detector is the subject for design space exploration. The second project aims at speeding up the execution of programs written in R (a language frequently used for statistical analyses) by about two orders of magnitude\, thereby enabling more comprehensive statistical analyses\, particularly in life sciences. Another project addresses the problem of guaranteeing timeliness for systems based on unreliable hardware.
URL:https://www.cecs.uci.edu/event/an-overview-over-research-activities-at-the-design-automation-for-embedded-systems-daes-group-at-tu-dortmund/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110602T150000
DTEND;TZID=America/Los_Angeles:20110602T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14264-1307026800-1307030400@www.cecs.uci.edu
SUMMARY:GoldMine: Automatic Assertion Generation and Achieving Test Coverage Closure
DESCRIPTION:GoldMine: Automatic Assertion Generation and Achieving Test Coverage Closure\n\n\n\n\nSpeaker\n\n\nProf. Shobha Vasudevan\nECE\, University of Illinois at Urbana-Champaign\nUrbana\, Illinois\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 2\, 2011\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAssertions are ubiquitous in the modern system design cycle. They are used in pre-Silicon verification\, post-Silicon validation and debug\, emulation\, reliability checking\, and many related functional assurance phases. Assertion generation is an intensely manual\, time-intensive task. GoldMine\, developed by my group in UIUC\, is an assertion generation software that uses a combination of data mining and static analysis of the design. GoldMine uses formal verification to guide the data mining algorithms. GoldMine assertions are attested by designers\, as adding value to the verification process. In the first part of my talk\, I will present the function and working of this engine\, as well as its recent application at the specification level.  \nCounterexample feedback from formal verification of an assertion can be used to grow the size of the data set that is mined by GoldMine. When iteratively applied\, this data set eventually captures the entire behavior. This data set now forms a test suite where coverage closure can be achieved. This algorithm for monotonically increasing coverage of validation inputs is presented in the second part of my talk. I will also discuss how GoldMine can be applied in the context of soft error detection and emulation.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nShobha Vasudevan is an assistant professor of Computer Engineering in the ECE Department\, at the Univ of Illinois. She obtained her PhD and MS degrees from the University of Texas at Austin. Her research interests are in design verification\, validation\, reliability\, software testing\, data mining and formal verification. She is a recepient of the 2010 NSF CAREER award and the YWCA leadership in Science award.
URL:https://www.cecs.uci.edu/event/goldmine-automatic-assertion-generation-and-achieving-test-coverage-closure/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110309T150000
DTEND;TZID=America/Los_Angeles:20110309T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14265-1299682800-1299686400@www.cecs.uci.edu
SUMMARY:Multi-Agent Automated Negotiation and its Application to Collective Collaboration Systems
DESCRIPTION:Multi-Agent Automated Negotiation and its Application to Collective Collaboration Systems\n\n\n\n\nSpeaker\n\n\nDr. Takayuki Ito\nNagoya Institute of Technology\, The University of Tokyo and Japan Science and Technology Agency\nNagoya\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nKwei-Jay Lin\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 9 \, 2011\nRefreshments at 1:00 pm\, Lecture begins at 1:30pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nMulti-agent system is a system which cooperatively or competitively solve shared or distributedproblems. While agents could be acting on behalf of human users\, agents could be intelligent entities in the virtual world. In this talk\, I would like to introduce what is “multi-agent systems”\, and show the state of the art of theoretical researches and practical results. Also\, I would like to mention about the application to cloud computing and collective intelligence.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Takayuki ITO received the B.E.\, M.E\, and Doctor of Engineering from the Nagoya Institute of Technology in 1995\, 1997\, and 2000\, respectively. From 1999 to 2001\, he was a research fellow of the Japan Society for the Promotion of Science (JSPS). From 2000 to 2001\, he was a visiting researcher at USC/ISI (University of Southern California/Information Sciences Institute). From April 2001 to March 2003\, he was an associate professor of Japan Advanced Institute of Science and Technology (JAIST).  He joined Nagoya Institute of Technology as an associate professor of Graduate School of Engineering in April 2003. From 2005 to 2006\, he is a visiting researcher at Division of Engineering and Applied Science\, Harvard University and a visiting researcher at Sloan School of Management\, Massachusetts Institute of Technology. From 2008 to 2010\, he was\, again\, a visiting researcher at Sloan School of Management\, Massachusetts Institute of Technology. From 2010\, he is a senior researcher of the Policy Alternatives Research Institute\, University of Tokyo. \nFrom 2010\, he is a researcher selected for the most advanced and next generation research development program (1\,850\,000USD) by the Japan Cabinet Office. From 2009 to 2010\, he was the JST PREST (Sakigake fund 490\,000USD\, Big Challenge Type) Researcher. He resigned the JST PREST researcher because of the Cabinet office program. He received several Grants-in-Aid for Science Research funds from the Japan Society for the Promotion of Science (JSPS). The amounts are 212\,500USD(2005-2008) and 226\,500USD(2006-2009)\, for example\, and other national funds. \nHe received the Young Scientists’ Prize\, The Commendation for Science and Technology by the Minister of Education\, Culture\, Sports\, Science\, and Technology\, 2007\, the Nagao Special Research Award of the Information Processing Society of Japan\, 2007\, the Best Paper Award of AAMAS2006\, the 2005 Best Paper Award from Japan Society for Software Science and Technology\, the Best Paper Award in the 66th annual conference of 66th Information Processing Society of Japan\, and the Super Creator Award of 2004 IPA Exploratory Software Creation Projects. \nHe edited and is editing 5 Books. He published over 35 Journal papers\, over 100 conference/workshop papers\, and over 100 other papers. He is a board member of the International Foundation of Autonomous Agents and Multi-Agent Systems (IFAAMAS)\, Steering Committee Member\, International Conference on Principles and Practice of Multi-Agent Systems (PRIMA)\, the Editor-In-Chief of Journal of Information Processing Society of Japan\, and the editor of Journal of Japanese Society of Artificial Intelligence (JSAI). \nHe was SPC of the International Joint Conference on Artificial Intelligence (IJCAI2009\,2001)\, a SPC of the 8th International Joint Conference on Autonomous Agents and Multi-Agent Systems(AAMAS2007\,2008\,2011)\,  SPC of The 25th AAAI Conference on Artificial Intelligence (AAAI-11) \, 2011. Senior Program Committee\, the Publications Chair of the 6th International Joint Conference on Autonomous Agents and Multi-Agent Systems (AAMAS2006)\, PC member of The 19th European Conference on Artificial Intelligence (ECAI2010)\, the Organizing Chair of the International Workshop on Rational\, Robust\, and Secure Negotiations among Multiple Agents (RRS 2005 to 2007)\, Agent-based Complex Automated Negotiations (ACAN2008 to 2011)\, Program Committee member of the ACM Conference on Electronic Commerce(ACM-EC2007)\, the Program Chair of the International Workshop on the Pacific Rim International Workshop on Electronic Commerce (PRIWEC2006)\, the Program Committee of the International Conference of Industrial & Engineering Applications of Artificial Intelligence & Expert Systems (IEA/AIE 2003 to 2008)\, the Program Committee of International Workshop on Data Engineering Issues in E-Commerce (DEEC 2005 to 2006)\, and other Committees. His main research interestsinclude multi-agent systems\, intelligent agents\, group decision support systems\, agent-mediated electronic commerce\, and softwareengineering on offshoring.
URL:https://www.cecs.uci.edu/event/multi-agent-automated-negotiation-and-its-application-to-collective-collaboration-systems/
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20110210T150000
DTEND;TZID=America/Los_Angeles:20110210T160000
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SUMMARY:Worst Case Execution Time Estimation
DESCRIPTION:Worst Case Execution Time Estimation\n\n\n\n\nSpeaker\n\n\nDr. Y.N. Srikant\,\nDepartment of Computer Science and Automation\nIndian Institute of Science\nBangalore\, India\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFebruary 10\, 2011\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nEstimation of worst case execution time of programs is extremely important in the context of real time systems where the correctness of the system depends not only on the computations performed\, but also on the timing of such computations. For task scheduling on such systems\, it is necessary to know whether the task can execute to completion within a predetermined time interval. Thus\, given a program and a target architecture\, the WCET problem is to estimate a bound on the maximum execution time taken by the program for any input data set.  \nWCET estimation is usually required to be safe and tight. Static analysis based techniques for WCET estimation use micro-architectural models for the target architecture and abstract interpretation for program analysis. Their results are safe but are not very tight. Measurement based techniques estimate the execution time for basic blocks by actual execution\, and then combine the results using integer linear programming. These results are tighter but not safe. \nIn this talk\, an overview of a probabilistic scheme for WCET estimation\, which is a hybrid of static and measurement based methods is presented. Preliminary results on a novel measurement based technique using program phases will also be presented.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nY.N. Srikant received his B.E in Electronics from Bangalore University\, and M.E and Ph.D in Computer Science from the Computer Science and Automation department of the Indian Institute of Science. He was the recipient of Young Scientist medal of the Indian National Science Academy in 1988. Srikant is currently a Professor in the Department of Computer Science and Automation at the Indian Institute of Science in Bangalore. He was the chair of the CSA department from 2000-05. \nHis area of interest is compiler design. He is the editor of a handbook on advanced compiler design published by CRC Press in 2002 and 2008 (2nd ed.). His most recent research includes compiler and runtime optimizations for reducing energy consumption in embedded systems and performance estimation of programs through program analysis.
URL:https://www.cecs.uci.edu/event/worst-case-execution-time-estimation/
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20101025T150000
DTEND;TZID=America/Los_Angeles:20101025T160000
DTSTAMP:20231011T182453Z
CREATED:20231011T182453Z
LAST-MODIFIED:20231011T182453Z
UID:14267-1288018800-1288022400@www.cecs.uci.edu
SUMMARY:Component-Based Design of Embedded Systems
DESCRIPTION:Component-Based Design of Embedded Systems\n  \n\n\n\n\nSpeaker\n\n\nProf. Hermann Kopetz\,\nUniversity of Vienna\, Austria\n\n\n\n\n\n\n\n\n\n\nCECS Hosts\n\n\nKane Kim\, Rainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nCalIT2 Room 3008\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 25 \, 2010\nLecture begins at 10:30 AM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn many engineering disciplines\, large systems are built from prefabricated components with known and validated properties. Components are connected via stable\, understandable\, and standardized interfaces. The system engineer has knowledge about the global properties of the components–as they relate to the system functions– and of the detailed specification of the component interfaces. Knowledge about the internal design and implementation of the components is neither needed\, nor available in many cases. Component-based design refers to a meet-in-the middle design methodology\, where\, starting from a purpose and requirements on one side and a set of available components on the other side a new design is produced that tries to satisfy the requirements by a proper interconnection of available and newly developed components. In this lecture we introduce the recursive component concept and the integration framework of the time- triggered architecture and demonstrate how the component-based design of embedded systems can be realized within this framework\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nHermann Kopetz received his PhD in physics sub auspiciis praesidentis from the University of Vienna\, Austria in 1968. After eight years in Industry he accepted in 1978 an appointment as a Professor for Computer Process Control at the Technical University of West-Berlin\, moving to the Technical University of Vienna in 1992. Kopetz is a full member of the Austrian Academy of Science\, Fellow of the IEEE\, and is a member of the Information Society Advisory Group (ISTAG)\, advising the European Commission in Brussels in the domain of Information Technology since 2008. In June 2007 he received the honorary degree of Dr. honoris causa from the University Paul Sabatier in Toulouse\, France. Kopetz is the chief architect of the Time-Triggered Architecture for dependable Embedded Systems and a co-founder of the company TTTech that has industrialized the time-triggered technology in many reputable projects\, among others in the Boeing 787 Dreamliner and the Audi A8 premium car.
URL:https://www.cecs.uci.edu/event/component-based-design-of-embedded-systems/
CATEGORIES:Seminars at CECS
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