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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180206T150000
DTEND;TZID=America/Los_Angeles:20180206T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14512-1517929200-1517932800@www.cecs.uci.edu
SUMMARY:“Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins”
DESCRIPTION:Title: “Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins”\nSpeaker: Prof. Sergio Bampi\, Informatics Institute – Microelectronics Design – Federal University of Rio Grande do Sul\, Brazil \nDate and Time: Thursday\, February 15\, 2018 at 2:00PM-3:00PM \nLocation: ICS 432 \nAbstract: \nPromising opportunities for research on heterogeneous Internet-of- Things (IoT) devices lie at the energy-bottom floor\, where CMOS is still an unbeatable\, flexible technology to make the internet of “everything” possible and cost-effective. Near-threshold computing (NTC) in CMOS is a promising alternative for any application which can tolerate or benefit from very wide voltage-frequency scaling (VFS). The digital blocks of devices may operate at very different power-performance modes\, from sub-MHz to peaks of hundreds of MHz\, which requires CMOS design libraries targeted for NTC. The analog and RF content on IoT chips will be even more crucial\, from a power-savings standpoint. In IoT it is best to avoid using costlier CMOS\, and yet closer to an end\, two-dimensional transistor and IC scaling. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific logic design techniques to be applied in digital CMOS. This talk addresses a method to design CMOS digital circuits for a wide dynamic range of VFS\, and targets near-threshold for best energy-efficiency. Our work on 65nm CMOS has demonstrated 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their system operating modes. The results in CMOS were obtained using the minimal cycle time achievable at each supply voltage\, down to very low 200 mV supplies. The strategy for transistor sizing in digital cells and static noise margin maximization will be addressed in particular. The seminar seeks to stimulate system-level and circuit-level design approaches for IoT nodes\, as the presenter is available to discuss digital\, mixed-signal\, and even RF aspects of CMOS systems-on- IoT-devices. \nBiography: \nSergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS\, 1979)\, and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics design fields at the Informatics Institute\, member of the faculty since 1986. He is a member of the PPGC Computing Graduate Program since 1988\, and of the PGMICRO since its start in 2002. He served as Graduate Program Coordinator (2003-2007)\, head of research group and projects\, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff\, and a visiting research faculty at Stanford University (1998-99). His research interests are in the area of IC design\, nano-CMOS devices\, mixed signal and RF CMOS design\, ultra-low power digital design\, dedicated complex algorithms\, architectures\, and ASICs for image and video processing. He has co-authored more than 360 papers in these fields and in MOS devices and EDA. He is a senior member of IEEE. He was Technical Program Chair of IEEE SBCCI Symposium (1997\, 2005)\, SBMICRO (1989\, 1995)\, IEEE LASCAS (2013)\, VARI 2016 Conferences and Workshops.
URL:https://www.cecs.uci.edu/event/near-threshold-computing-the-bottom-floor-for-energy-in-iot-devices-and-its-vanishing-design-noise-margins/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180222T150000
DTEND;TZID=America/Los_Angeles:20180222T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190724Z
LAST-MODIFIED:20231011T190729Z
UID:14514-1519311600-1519315200@www.cecs.uci.edu
SUMMARY:”Cost and Power Efficient Deep Neural Network Acceleration”
DESCRIPTION:Title: “Cost and Power Efficient Deep Neural Network Acceleration”\nSpeaker: Associate Prof. Jongeun Lee\, School of ECE\, UNIST\, Ulsan\, Korea \nDate and Time: Monday\, February 26\, 2018 at 11:00am – 12:00pm \nLocation: EH 2430 \nAbstract: \nDeep neural networks prove to be a right direction after all\, but the enormous computational complexity calls for new research into novel ways of making efficient implementations of the connectionist model for small\, mobile devices. \nIn this talk I will discuss two directions\, one based on FPGA and the other based on a new computing paradigm called stochastic computing (SC).  FPGA is a very capable device housing thousands of processing elements in a single chip with low power consumption.  However\, FPGAs are very different from GPUs\, and making it easy to program FPGAs for deep neural networks is one of the key challenges facing FPGAs today.  I will present a design space exploration approach to help find the best design for a given FPGA and for a specific deep neural network model. \nStochastic computing (SC) was first introduced in the 60’s when computing devices were not very reliable.  Unlike conventional binary number representations\, stochastic computing uses a bitstream to represent a number\, and is therefore inherently more error-resilient. \nIn addition\, SC shares some good qualities with analog computing such as low power dissipation and low cost while strictly operating in the digital domain.  At the same time\, error fluctuation and conversion overhead are the key challenges facing SC today.  I will present a new SC architecture for deep neural networks that is much more accurate and efficient than previous SC solutions. \nBiography: \nJongeun Lee received his B.S. and M.S. in Electrical Engineering\, and his Ph.D. in electrical engineering and computer science all from Seoul National University\, Korea. In 2009 he joined UNIST (Ulsan National Institute of Science and Technology)\, Ulsan\, Korea\, where he is now an Associate Professor of Electrical and Computer Engineering. Prior to joining UNIST\, he worked as a postdoctoral research associate at Arizona State University\, and previously worked for Samsung Electronics. His current research interests include reconfigurable architectures\, compilers\, stochastic computing\, and deep neural networks.
URL:https://www.cecs.uci.edu/event/cost-and-power-efficient-deep-neural-network-acceleration/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180402T150000
DTEND;TZID=America/Los_Angeles:20180402T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190729Z
UID:14515-1522681200-1522684800@www.cecs.uci.edu
SUMMARY:"ASSISTECH: Assistive Technology for the Visually Impaired"
DESCRIPTION:Title: “ASSISTECH: Assistive Technology for the Visually Impaired”\nSpeaker: Professor Mayandiambalam Balakrishnan\, CSE\, Indian Institute of Technology\, Delhi\, India \nDate and Time: Monday\, March 26 at 3:00PM-4:00PM \nLocation: Donald Bren Hall 4011 \nAbstract:  \nMore than ten years back we started on the ASSISTECH journey – a laboratory dedicated to finding\ntechnology solutions for the mobility and education of the visually impaired. It has been a very challenging but deeply fulfilling journey. Globally there are many technology solutions available for addressing the mobility as well as education needs of the visually impaired. Unfortunately they fail to address the challenges of mobility and education in India and other developing countries and even if they do they are completely unaffordable. In this talk I would tell the story of development and dissemination of devices and technologies like SmartCane\, OnBoard and Tactile Diagrams. These started in the ASSISTECH laboratory as inter-disciplinary projects and are today slowly finding their way to the users. \nBiography: \nM Balakrishnan has a B.Tech.(EEE) from BITS Pilani and PhD(EE) from IIT Delhi. He has been\ninvolved in teaching and research in EDA\, VLSI and Embedded systems for more than three decades. He has published over 120 papers in leading journals and conferences\, supervised 13 PhD students and over 180 B.Tech. and M.Tech. student projects. He has held visiting positions in Canada\, US and Germany. He has founded the ASSISTECH laboratory at IIT Delhi which is engaged in finding affordable technology based solutions for education and mobility of visually impaired. He is a recipient of two national awards for his work in the disability space. He has been HoD(CSE)\, Dean(Post Graduate Studies & Research)\, Deputy Director(Faculty) and is currently Deputy Director(Strategy & Planning) at IIT Delhi.
URL:https://www.cecs.uci.edu/event/assistech-assistive-technology-for-the-visually-impaired/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180507T150000
DTEND;TZID=America/Los_Angeles:20180507T160000
DTSTAMP:20231011T190730Z
CREATED:20231011T190725Z
LAST-MODIFIED:20231011T190730Z
UID:14518-1525705200-1525708800@www.cecs.uci.edu
SUMMARY:"Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks"
DESCRIPTION:Title: “Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks”\nSpeaker: Roger Piqueras Jover\, Security Researcher at Bloomberg LP \nDate and Time: Tuesday\, May 15 at 10:00 a.m. \nLocation: Donald Bren Hall 3011 \nAbstract:  \nThe Long Term Evolution (LTE) is the latest mobile communications standard being deployed globally to provide connectivity to billions of mobile devices\, from personal cell-phones to all types of critical systems\, such as self-driving cars\, medical appliances and industrial IoT sensors. As such\, the security of this communication standard is of paramount importance. However\, there is concerning inherent protocol security threats in LTE due to the large amount of unauthenticated and unprotected messages exchanged between a base station and a mobile device prior to the authentication security handshake. \nOpen source implementations of the LTE standards rapidly matured within the last couple of years. This\, in combination with sophisticated yet low cost software radio hardware\, fueled a new wave of security research that identified numerous protocol security issues in LTE that could allow an adversary to deny the service of mobile endpoints and track the location of users. This talk will summarize an ongoing effort on protocol-fuzzing LTE mobile networks using open-software tools. The protocol exploits against mobile endpoints that were discovered two years ago will be discussed as an introduction to the new systematic approach to protocol-fuzz LTE networks\, introducing as well a series of new potential exploits in the uplink\, against the network infrastructure and mobile devices outside of the radio range of the adversary. \nFinally\, these LTE protocol exploits are analyzed in the context of the recently (December 2017) published first release of the 3GPP 5G specifications (3GPP Rel. 15) for the 5G Radio Access Network (5G New Radio) and Core Network (5G System). Unfortunately\, not only most protocol-aware radio jamming issues and LTE protocol exploits are still a potential threat\, but there is a large number of new pre-authentication messages and new fields to already existing messages that could open the doors to further 5G-specific exploits. \nBiography: \nRoger Piqueras Jover is a Wireless Security Research Scientist and Security Architect at the CTO Security Architecture team of Bloomberg LP\, where he leads projects on mobile/wireless security and is actively involved in hardware security\, network security\, machine learning and anomaly/fraud detection. Previous to Bloomberg\, he spent 5 years at the AT&T Security Research Center (AT&T SRC)\, where he led the research area on wireless and LTE mobile network security and received numerous awards for his work. \nRoger holds 17 issued patents on mobile and wireless security\, has co-authored manuscripts in numerous top communications and security conferences and is the Technical Co-Chair for the ongoing IEEE 5G Summit series. \nRoger holds a Dipl. Ing. from Politechnical University of Catalunya (Barcelona\, Spain)\, a Master’s in Electrical and Computer Engineering from University of California Irvine and a Master’s/MPhil and EBD (Everything But Dissertation) in Electrical Engineering from Columbia University. \nFor a much more detailed biography\, details on his wireless security work on LTE\, 5G\, LoRaWAN and other technologies\, one can refer to http://rogerpiquerasjover.net/
URL:https://www.cecs.uci.edu/event/protocol-fuzzing-mobile-networks-with-open-source-tools-to-enhance-the-security-of-lte-and-5g-mobile-networks/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180516T150000
DTEND;TZID=America/Los_Angeles:20180516T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14524-1526482800-1526486400@www.cecs.uci.edu
SUMMARY:“Self-aware Computing: Combining Learning and Control to Manage Complex\, Dynamic Systems”
DESCRIPTION:<stThese self-aware systems are distinguished by awareness of user goals and operating environment; they continuously monitor themselves and adapt their behavior and foundational models to ensure the goals are met despite the challenges of complexity (diverse hardware resources to be managed) and dynamics (unpredictable changes in input workload or resource availability). In this talk\, I will describe how to build self-aware systems through a combination of control theoretic and machine learning techniques. I will then show how this combination enables new capabilities\, like increasing system robustness\, reducing application energy\, and meeting latency requirements even with no prior knowledge of the application. Finally\, these LTE protocol exploits are analyzed in the context of the recently (December 2017) published first release of the 3GPP 5G specifications (3GPP Rel. 15) for the 5G Radio Access Network (5G New Radio) and Core Network (5G System). Unfortunately\, not only most protocol-aware radio jamming issues and LTE protocol exploits are still a potential threat\, but there is a large number of new pre-authentication messages and new fields to already existing messages that could open the doors to further 5G-specific exploits. \nBiography: \nHenry Hoffmann is an Associate Professor in the Department of Computer Science at the University of Chicago. He was granted early tenure in 2018. At Chicago he leads the Self-aware computing group (or SEEC project) and conducts research on adaptive techniques for power\, energy\, accuracy\, and performance management in computing systems. He received the DOE Early Career Award in 2015. He has spent the last 17 years working on multicore architectures and system software in both academia and industry. He completed a PhD in Electrical Engineering and Computer Science at MIT where his research on self-aware computing was named one of the ten “World Changing Ideas”  by Scientific American in December 2011. He received his SM degree in Electrical Engineering and Computer Science from MIT in 2003. As a Masters student he worked on MIT’s Raw processor\, one of the first multicores. Along with other members of the Raw team\, he spent several years at Tilera Corporation\, a startup which commercialized the Raw architecture and created one of the first manycores (Tilera was sold for $130M in 2014). His implementation of the BDTI Communications Benchmark (OFDM) on Tilera’s 64- core TILE64 processor still has the highest certified performance of any programmable processor. In 1999\, he received his BS in Mathematical Sciences with highest honors and highest distinction from UNC Chapel Hill. \n 
URL:https://www.cecs.uci.edu/event/self-aware-computing-combining-learning-and-control-to-manage-complex-dynamic-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180521T150000
DTEND;TZID=America/Los_Angeles:20180521T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14527-1526914800-1526918400@www.cecs.uci.edu
SUMMARY:"One does not need a Village to make a Billion Gate ASIC\, only a family if Synchoros VLSI Design Style is adopted"
DESCRIPTION:Name: Ahmed Hemani\nDate and Time: June 6\, 2018 at 4:00 p.m. \nLocation: Engineering Hall 2430 \nCommittee: Nikil Dutt (Host) \nAbstract: \nNorman Jouppi while introducing the record long list of authors of Google’s TPU paper at ISCA 2017 remarked – one needs a village to make a chip. This talk proposes a VLSI design method that holds promise of getting the same work done with just a family. This new VLSI design method is based on two principles\, one is to raise the abstraction of physical design to micro-architecture level from the present day boolean level standard cells and the second is to adopt a synchoros VLSI design style that enables composition by abutment to eliminate logic and physical synthesis for the end user. \nThe proposed method raises the abstraction of physical design to micro-architecture level by adopting coarse grain reconfigurable logic for computation\, storage and interconnect. All variations in function\, capacity\, architecture and degree of parallelism are realised by clustering and configuration of the coarse grain reconfigurable cells that we call as SiLago blocks – Silicon Lego Blocks. The micro-architecture level SiLago blocks replace boolean level standard cells as the atomic building blocks of the VLSI systems. These CGRA fabrics are domain specific – inner modem\, outer modem\, scratchpad memory\, dynamic programming\, NOCs\, infrastructural elements like RISC system controller\, PLL/CGU\, RGU\, DRAM control etc. Each CGRA fabric is holistically customized for its domain\, not just for computation but also for control\, interconnect\, address generation\, local storage etc. \nThe CGRAs provide an architecturally regular basis for a synchoros VLSI design style. Synchoricity is derived from the Greek word “choros” for space. The way synchronous systems divide time uniformly with clock ticks and enables temporal composition\, synchoros systems divide space uniformly with grids and enables spatial composition. All SiLago blocks are synchoros or ratiochoros and bring out all their interconnects to periphery on grid at right place and on right metal layer to enable composition by abutment of valid neighbours. \nThe net result of adopting the above two principles is that as soon as a design is refined down to micro-architecture level\, the dimension and position of every single wire segment and transistor is known with certainty in the 100 million gate design. Unlike standard cells\, where the position of standard cells and wires connecting them is left to physical synthesis\, in synchoros design style these aspects are parametrically hardened. Global wires like power grid\, clocks\, resets\, NOCs are not synthesised\, they emerge as a result of the abutment process. This enables automation of system models down to GDSII to create custom\, spatially distributed functional hardware\, i.e.\, ASICs with just a family. \nA proof of concept synthesis flow exists for transforming applications\, hierarchy of algorithms\, to GDSII and a path for system level to GDSII is well defined and is being implemented. System-level implies interacting applications. \nBiography: \nAhmed Hemani is Professor in Electronic Systems Design at School of ICT\, KTH\, Kista\, Sweden. His current areas of research interests are massively parallel architectures and design methods and their applications to scientific computing and autonomous embedded systems inspired by brain. In past he has contributed to high-level synthesis – his doctoral thesis was the basis for the first high-level\nsynthesis product introduced by Cadence called visual architect. He has also pioneered the Networks-on-chip concept and has contributed to clocking and low power architectures and design methods. He has extensively worked in industry including National Semiconductors\, ABB\, Ericsson\, Philips Semiconductors\, Newlogic. He has also been part of three start-ups.
URL:https://www.cecs.uci.edu/event/one-does-not-need-a-village-to-make-a-billion-gate-asic-only-a-family-if-synchoros-vlsi-design-style-is-adopted/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180530T150000
DTEND;TZID=America/Los_Angeles:20180530T160000
DTSTAMP:20231011T190732Z
CREATED:20231011T190732Z
LAST-MODIFIED:20231011T190732Z
UID:14528-1527692400-1527696000@www.cecs.uci.edu
SUMMARY:"Are there any questions?"
DESCRIPTION:Name: Yale Patt\nDate and Time: Thursday\, June 7 at 2:00 p.m. – 3:00 p.m. \nLocation: Engineering Hall 2430 \nAbstract:  \nToo many seminars can be characterized as 50 minutes of lecture\, followed by 5 minutes of questions. …and the first question makes it clear that nothing the speaker said in the 50 minutes was at all interesting to the audience. So\, we will take the opposite approach: 5 minutes of lecture\, followed by 50 minutes of questions. 5 minutes of lecture just to set the tone. Where the questions will take us is anybody’s guess. It will probably have something to do with computer architecture\, historical or current\, but it may venture off into something political …or at least politically correct. \nBiography: \nYale Patt is a Professor of Electrical and Computer Engineering and the Ernest\nCockrell\, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He divides his\ntime between teaching the freshman and senior courses and his advanced graduate course in\nmicroarchitecture\, working with his PhD students\, and consulting in the microprocessor industry.\nHe earned obligatory degrees from reputable universities and has received more than his share of\nawards for his research and teaching. Patt has spent much of his career pursuring aggressive ILP\,\nout-of-order\, and speculative computer architectures\, such as HPSm. He has a Fellow of both the\nIEEE and ACM\, and a member of the National Academy of Engineering. He received his master’s\nand Ph.D. degrees in Electrical Engineering from Stanford University.
URL:https://www.cecs.uci.edu/event/are-there-any-questions/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14532-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:“Regional Coherence and Near Memory Acceleration in Distributed-Shared-Memory Architectures”
DESCRIPTION:Name: Andreas Herkersdorf\nDate and Time: Thursday\, July 26 at 11:00 a.m. – 12:00 p.m. \nLocation: Donald Bren Hall 3011 \nAbstract:  \nData access latencies and bandwidth bottlenecks frequently represent major limiting factors for the computational effectiveness of many-core processor architectures. This presentation introduces two\nconceptually complementary approaches to reduce the synchronization overheads for coherence\nmaintenance and to improve the locality between computing resources and data: Region-based cache\ncoherence and near memory acceleration. \nA 2D array of compute tiles with multiple\, heterogeneous RISC cores\, two levels of caches and a tile-local\nSRAM memory serves as reference processing platform. These compute tiles\, various I/O tiles and a globally shared DDR SDRAM memory tile are interconnected by a meshed Network on Chip (NoC) with support for multiple quality of service levels. Overall\, this processing architecture follows a distributed-\nshared-memory model. The limited degree of parallelism in many embedded computing applications\nalso bounds the number of compute tiles possibly sharing associated data structures. Therefore\, we favor region-based cache coherence (RBCC) among a limited number of compute tiles over global coherence approaches. Coherence regions are dynamically configured at runtime and comprise a number of arbitrary (adjacent or non-adjacent) compute tiles which are interconnected through regular NoC channels for the exchange of coherency protocol messages. We will show that region-based coherence allows maintaining substantially smaller coherence directories (e.g.\, by approx. 40% reduced in size for 16 tiles systems with up to 4 tiles per region) and shorter sharer checking latencies than global coherence. RBCC increases the locally usable intra-tile shared SRAM memories and may reduce execution times of sample video processing applications by 30% in comparison to message passing based parallelization. However\, the benefits of RBCC may strongly depend on the task and data placement among tiles in the coherency region which can affect performance by up to an order of magnitude. Near memory processing using near memory accelerators (NMA) positions processing resources for specific data manipulations as close as possible to the data memory for the benefit of shortening access latencies and increasing compute efficiency. \nBiography: \nAndreas Herkersdorf is a professor in the Department of Electrical and Computer Engineering and also\naffiliated to the Department of Informatics at Technical University of Munich (TUM). He received a Dr.\ndegree from ETH Zurich\, Switzerland\, in 1991. Between 1988 and 2003\, he has been in technical and\nmanagement positions with the IBM Research Laboratory in Rüschlikon\, Switzerland.\nSince 2003\, Dr. Herkersdorf leads the Chair of Integrated Systems at TUM. He is a senior member of the\nIEEE\, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer and De Gruyter journals for design automation and information technology. His research interests include application-specific multi-processor architectures\, IP network processing\, Network on Chip and self-adaptive fault-tolerant computing.
URL:https://www.cecs.uci.edu/event/regional-coherence-and-near-memory-acceleration-in-distributed-shared-memory-architectures/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14533-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Accurate and Stable CPU Power Modelling and Run-Time System Management"
DESCRIPTION:Name: Matthew Walker\nDate and Time: Friday\, July 27 at 11:00 a.m. – 12:00 p.m. \nLocation: Donald Bren Hall 4011 \nAbstract:  \nModern processors must provide an ever-increasing level of performance and are therefore including\nhigher numbers of Heterogeneous Multi-Processing (HMP) units. Intelligent run-time control of performance and power consumption is required to extend battery-life in mobile systems\, reduce energy and cooling costs in data centres\, and increase peak performance while respecting thermal and power constraints. Accurate online power estimation is essential in guiding run-time power management mechanisms and energy-aware scheduling decisions.\n\nIn this talk Matt will share his experience with CPU modelling and run-time management\, and present three open-source software tools for developing power models on mobile devices (http://www.powmon.ecs.soton.ac.uk)\, calibrating performance and energy models in the gem5 simulation framework (http://gemstone.ecs.soton.ac.uk)\, and developing run-time management algorithms (https://github.com/PRiME-project/PRiME-Framework/).\nBiography: \nMatthew J. Walker received his M.Eng. degree in Electronic Engineering (Hons) from the University of Southampton\, UK\, in 2013. In 2016 he worked on implementing non-volatile memory technologies in mobile systems at Intel Labs\, CA\, and has also completed two internships at Arm\, UK\, in 2015 and 2018. He is currently in his fourth year of his PhD at the University of Southampton researching CPU modelling techniques and run-time management approaches.
URL:https://www.cecs.uci.edu/event/accurate-and-stable-cpu-power-modelling-and-run-time-system-management/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190805Z
CREATED:20231011T190805Z
LAST-MODIFIED:20231011T190805Z
UID:14534-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Sensors" Innovation at Intersections"
DESCRIPTION:Name: Khaled Salama\nDate and Time: Friday\, August 3 at 10:00 a.m. – 11:00 a.m. \nLocation: Engineering Hall 2430 \nAbstract:  \n\nEnergy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. We will provide a summary of various sensors developed under the KAUST sensors initiative a consortium of 9 universities (KAUST\, MIT\, UCLA\, GATECH\, MIT\, UCLA\, Brown University\, Georgia Tech\, TU Delft\, Swansea University\, the University of Regensburg and the Australian Institute of Marine Science (AIMS). \n\nBiography: \nKhaled N. Salama received the B.S. degree from the Department Electronics and Communications\, Cairo University\, Cairo\, Egypt\, in 1997\, and the M.S. and Ph.D. degrees from the Department of Electrical Engineering\, Stanford University\, Stanford\, CA\, USA\, in 2000 and 2005\, respectively. He was an Assistant Professor at Rensselaer Polytechnic Institute\, NY\, USA\, between 2005 and 2009. He joined King Abdullah University of Science and Technology (KAUST) in January 2009\, where he is now a professor\, and was the founding Program Chair until August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford–Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc. He is the author of 200 papers and 14 US patents on low-power mixed-signal circuits for intelligent fully integrated sensors and neuromorphic circuits using memristor devices.
URL:https://www.cecs.uci.edu/event/sensors-innovation-at-intersections/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190808Z
LAST-MODIFIED:20231011T190813Z
UID:14539-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Sensors" Innovation at Intersections"
DESCRIPTION:Name: Khaled Salama\nDate and Time: Friday\, August 3 at 10:00 a.m. – 11:00 a.m. \nLocation: Engineering Hall 2430 \nAbstract:  \n\nEnergy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. We will provide a summary of various sensors developed under the KAUST sensors initiative a consortium of 9 universities (KAUST\, MIT\, UCLA\, GATECH\, MIT\, UCLA\, Brown University\, Georgia Tech\, TU Delft\, Swansea University\, the University of Regensburg and the Australian Institute of Marine Science (AIMS). \n\nBiography: \nKhaled N. Salama received the B.S. degree from the Department Electronics and Communications\, Cairo University\, Cairo\, Egypt\, in 1997\, and the M.S. and Ph.D. degrees from the Department of Electrical Engineering\, Stanford University\, Stanford\, CA\, USA\, in 2000 and 2005\, respectively. He was an Assistant Professor at Rensselaer Polytechnic Institute\, NY\, USA\, between 2005 and 2009. He joined King Abdullah University of Science and Technology (KAUST) in January 2009\, where he is now a professor\, and was the founding Program Chair until August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford–Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc. He is the author of 200 papers and 14 US patents on low-power mixed-signal circuits for intelligent fully integrated sensors and neuromorphic circuits using memristor devices.
URL:https://www.cecs.uci.edu/event/sensors-innovation-at-intersections-2/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180719T150000
DTEND;TZID=America/Los_Angeles:20180719T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190806Z
LAST-MODIFIED:20231011T190813Z
UID:14535-1532012400-1532016000@www.cecs.uci.edu
SUMMARY:"Efficient Processing when Intelligence Moves to the Edge"
DESCRIPTION:Name: Tinoosh Mohsenin\nDate and Time: Friday\, July 20 at 10:00 a.m. – 11:00 a.m. \nLocation: Donald Bren Hall 4011 \nAbstract:  \n\nContinuous collection and processing of vast amounts of data is becoming more common with the advancement of wearable sensors\, Internet of Things (IoT) devices and cyber physical systems. Despite their potential significant impact\, intelligent mobile technologies face a number of challenges for use in daily life. These devices usually stream raw data to cloud computers for computation which leads to massive storage\, significant transmission power consumption\, real time constraints and privacy/security issues\, thus processing at the edge of sensors is becoming increasingly preferred. Processing these sensor-level data requires a variety of signal processing and machine learning tasks that come at the cost of high computational complexity and memory storage which is overwhelming for these light weight and battery constrained platforms. \nIn this talk I will present research solutions that enable efficient processing of machine learning tasks to improve energy efficiency and throughout without sacrificing application accuracy for wide deployment of embedded/edge processing. First\, I present DeepMatter a scalable framework across algorithms\, architectures and hardware to design an embedded Deep Neural Net (DNN) accelerator. DeepMatter takes any number of raw sensor data for variety of applications and classifies the events within 92% accuracy and consumes very low power. Next I present two programmable domain-specific manycore accelerators namely PENC and BinMACthat achieve energy and speed efficiencies comparable to application-specific custom hardware through data-level and task level parallelization as well as customization of instruction-sets per-core and near-memory computing. I will show the efficiency of DeepMatter as well as PENC and BinMAC solutions for several application domains including multi-physiological processing for seizure and stress monitoring\, tongue drive assistive device\, air quality monitoring andvision-based situational awareness. The solutions derived at the intersection of algorithms\, architectures and implementation allow designers to rapidly prototype and deploy the next generation of sophisticated and intelligent systems for efficient edge processing in extreme environments. \n\nBiography: \nTinoosh Mohsenin is an Assistant Professor in the Department of Computer Science and Electrical Engineering at University of Maryland Baltimore County\, where she directs Energy Efficient High Performance Computing (EEHPC) Lab. She received her PhD from University of California\, Davis in 2010 and M.S. degree from Rice University in 2004\, both in Electrical and Computer Engineering. Prof. Mohsenin’s research focus is on designing highly accurate and energy efficient embedded processors for machine learning\, signal processing and knowledge extraction techniques for autonomous systems\, wearable smart health monitoring\, and embedded big data computing. She has over 80 peer-reviewed journal and conference publications and is the recipient of NSF CAREER award in 2017\, the best paper award in the GLSVLSI conference in 2016\, and the best paper honorable award in ISCAS 2017 for developing domain-specific accelerators for biomedical\, deep learning and cognitive computing. She currently leads 8 research projects in her lab which are all funded by National Science Foundation (NSF)\, Army Research Lab (ARL)\, Northrop Grumman\, Boeing\, Nvidia and Xilinx. She has served as associate editor in IEEE Transactions on Circuits and Systems-I (TCAS-I) and IEEE Transactions on Biomedical Circuits and Systems (TBioCAS). She was the local arrangement co-chair for the 50th IEEE\nInternational Symposium on Circuits and Systems (ISCAS) in Baltimore. She has also served as technical program committee member of the IEEE International Solid-State Circuits Conference Student Research (ISSCC-SRP)\, IEEE Biomedical Circuits and Systems (BioCAS)\, IEEE International Symposium on Circuits and Systems (ISCAS)\, ACM Great Lakes Symposium on VLSI (GLSVLSI and IEEE International Symposium on Quality Electronic Design (ISQED) conferences. She also serves as secretary of IEEE P1890 on Error Correction Coding for Non-Volatile Memories.
URL:https://www.cecs.uci.edu/event/efficient-processing-when-intelligence-moves-to-the-edge/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180904T150000
DTEND;TZID=America/Los_Angeles:20180904T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190807Z
LAST-MODIFIED:20231011T190813Z
UID:14537-1536073200-1536076800@www.cecs.uci.edu
SUMMARY:“SAT-based Design Debugging and Its Application to Undergraduate Circuit Experiment”
DESCRIPTION:Name: Takeshi Matsumoto\nDate and Time: Friday\, September 7 at 11:00 a.m. – 12:00 p.m. \nLocation: Donald Bren Hall 3011 \nAbstract: \nAs VLSI designs are becoming larger and more complicated\, designers spend a larger amount of\ntime for verification and debug to detect bugs in designs and avoid them. Moreover\, some bugs may not be detected in the verification processes before fabrication and are only recognized by running an actual chip after fabrication. In post-silicon debugging\, it is not practical that a large part of the circuit is changed for fixing bugs\, since such large change requires designers to do time-consuming physical and timing design processes again. Usually\, more than a half of the verification time is spent for correcting the buggy portions of the designs rather than identifying them\, since debugging is much less automated than checking correctness of the designs. Thus\, automating and shortening the debugging processes is now one of the most important issues in VLSI designs. In this talk\, SAT-based design debugging methods in gate-level and behavior-level are introduced. In the methods\, debugging consists of two processes: locating the suspicious portions in the designs and correcting them through replacements with appropriate sets of gates. In the locating process\, designers try to find locations of bugs (or candidate locations) which should be the root cause of the bugs. Then\, they modify logic functions at those possibly buggy locations in the correcting process. Both processes can be solved by repeatedly solving Boolean satisfiability (SAT) problems by introducing programmable logic elements\, such as MUX (multiplexer) and/or LUT (look-up table)\, to the original designs under debugging. This talk gives the details of the theoretical aspect of those methods and experimental results on several circuits. In the last part of the talk\, a trial activity to apply the debugging methods to an undergraduate experiment\, where a simple 4-bit CPU is made on breadboard through six 90-minute classes\, is introduced.\nThis activity can be seen as an application example of state-of-the-art research results to education field. \nBiography: \nTakeshi Matsumoto is an Associate Professor in the Department of Electronics and Information\nEngineering at National Institute of Technology\, Ishikawa College\, Japan. He directs Integrated System Lab in the department. He received his M.S. and Ph.D. degrees in Electronic Engineering from the University of Tokyo\, Japan\, in 2005 and 2008\, respectively. The topic of his Ph.D. thesis is equivalence checking of system level design. From 2008 to 2013\, he has been a Research Associate of VLSI Design and Education Center\, the University of Tokyo. His research interests include formal verification of system-level designs\, automated debugging and debugging support for pre- and post-silicon circuits\, education and teaching materials on electric and electronic circuits. He received IPSJ Yamashita SIG Research Award in 2012 from Information Processing Society of Japan.
URL:https://www.cecs.uci.edu/event/sat-based-design-debugging-and-its-application-to-undergraduate-circuit-experiment/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20181010T150000
DTEND;TZID=America/Los_Angeles:20181010T160000
DTSTAMP:20231011T190814Z
CREATED:20231011T190807Z
LAST-MODIFIED:20231011T190814Z
UID:14538-1539183600-1539187200@www.cecs.uci.edu
SUMMARY:"Security of Additive Manufacturing: New Frontiers"
DESCRIPTION:Name: Mark Yampolskiy\nDate and Time: Friday\, October 19 at 10:00 a.m. – 11:00 a.m. \nLocation: Engineering Hall 2430 \nAbstract: Additive Manufacturing (AM)\, a.k.a. 3D printing\, is a rapidly growing multibillion-dollar industry that is increasingly used to manufacture functional parts\, including components of safety critical systems in the aerospace\, automotive\, and other industries. However\, reliance on the IT infrastructure and the high degree of computerization of the manufacturing machines make AM susceptible to a variety of cyber and cyber-physical attacks. \nAM Security is a fairly new and highly inter-disciplinary field of research that aims to address the novel threats emerging for this manufacturing technology. This talk will first provide an introduction to the field. Focusing on AM sabotage\, one of the identified threat categories\, Dr. Mark Yampolskiy will then introduce emerging frontiers: sabotage of composite material parts\, AM forensics\, and detection of sabotage attacks via side-channel measurements. The talk will conclude with a summary of identified research gaps in the current state of the art. \nBiography: \nMark Yampolskiy received Ph.D. in Computer Science from Ludwig-Maximilians University of\nMunich\, Germany in 2009. He currently holds an Assistant Professor position at the University\nof South Alabama. Since his post-doctoral appointment at Vanderbilt University (2012-2013)\,\nMark Yampolskiy is performing research on Security of Cyber-Physical Systems (CPS). Mark\nYampolskiy was among the researchers who pioneered Security of Additive Manufacturing (AM\,\na.k.a. 3D Printing) around 2014. AM Security remains his major research focus\, and he is\ncurrently one of the leading experts in this field. His work is predominantly associated with two\nthreat categories\, sabotage of 3D-printed functional parts and theft of intellectual property. He\nhas numerous seminal publications in the field\, ranging from attacks on/with AM up to novel\napproaches for the detection of such attacks. \nAM Security is a highly interdisciplinary field of research. In order to address this challenge\,\nMark Yampolskiy actively collaborates with experts from different disciplines. His major\ncollaboration partners are affiliated with Lawrence Livermore National Laboratory (LLNL)\, Ben\nGurion University of the Negev (BGU) in Israel\, Singapore University of Technology and Design\n(SUTD)\, Auburn University (AU)\, and University of Tennessee at Chattanooga (UTC).
URL:https://www.cecs.uci.edu/event/security-of-additive-manufacturing-new-frontiers/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20181030T150000
DTEND;TZID=America/Los_Angeles:20181030T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190807Z
LAST-MODIFIED:20231011T190813Z
UID:14536-1540911600-1540915200@www.cecs.uci.edu
SUMMARY:"Plasmonic Wave Computing: Concepts and Potential"
DESCRIPTION:Name: Francky Catthoor\nDate and Time: Wednesday\, October 31 at 11:00 a.m. – 12:00 p.m. \nLocation: Engineering Hall 2430 \nAbstract:  \n\nSeveral beyond CMOS computing directions are being explored given that the CMOS scaling roadmap faces increasing challenges. Any alternative is however facing strong competition from the extremely optimized CMOS roadmap. One of the potential directions which can complement CMOS in an area where it is less good is highly parallel “wave-type” computing. In this talk I will discuss some of the promising concepts and their potential but also challenges. \n\nBiography: \nFrancky Catthoor received a Ph.D. in EE from the Katholieke Univ. Leuven\, Belgium in 1987. Between 1987 and 2000\, he has headed several research domains in the area of synthesis techniques and architectural methodologies. Since 2000 he is strongly involved in other activities at IMEC including deep submicron technology aspects\, IoT and biomedical platforms\, and smart photovoltaic modules\, all at IMEC Leuven\, Belgium. Currently he is an IMEC fellow. He is also part-time full professor at the EE department of the KULeuven. He has been associate editor for several IEEE and ACM journals and was elected IEEE fellow in 2005.
URL:https://www.cecs.uci.edu/event/plasmonic-wave-computing-concepts-and-potential/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20181101T150000
DTEND;TZID=America/Los_Angeles:20181101T160000
DTSTAMP:20231011T190843Z
CREATED:20231011T190827Z
LAST-MODIFIED:20231011T190843Z
UID:14545-1541084400-1541088000@www.cecs.uci.edu
SUMMARY:Accelerated Computing for Edge-Centric IoT
DESCRIPTION:Name: Tulika Mitra\nDate and Time: Monday\, November 5 at 2:00 p.m. – 3:00 p.m. \nLocation: Donald Bren Hall 3011 \nAbstract: Internet of Things (IoT)\, an ever-growing network of billions of devices embedded within physical objects\, is revolutionizing our daily life. The IoT devices in the edge are primarily responsible only for collecting and communicating the data to the cloud\, where the computationally intensive data analytics takes place. However\, the data privacy and the connectivity issues—in conjunction with the fast real-time response requirement of certain IoT applications—call for smart edge devices that should be able to support privacy-preserving\, time-sensitive computation for machine intelligence on-site. In this talk\, I will present the computation challenges in edge-centric IoT and introduce hardware-software co-designed approaches to overcome these challenges. I will discuss the  design of configurable\, customizable accelerators that are completely software programmable and can be universally deployed across diverse domains to speed up computation and realize the edge analytics vision at ultra-low power budget. I will also demonstrate the potential to achieve low-power\, real-time intelligence on the IoT edge devices via collaborating computing that engages all the on-chip heterogeneous compute elements (CPU\, GPU\, reconfigurable computing\, and accelerators) in a synergistic fashion though sophisticated compile- and runtime strategies. \nBiography: Tulika Mitra is a Professor of Computer Science at School of Computing\, National University of Singapore (NUS). Her research interests span various aspects of the design automation of embedded real-time systems with particular emphasis on low-power computing\, heterogeneous computing\, application-specific processors\, and software timing analysis/optimizations. She has authored over hundred and fifty scientific publications in leading international journals and conferences and holds multiple US patents. Her research has been recognized by best paper award and nominations in leading conferences. She is the recipient of the Indian Institute of Science Outstanding Woman Researcher Award and is an IEEE Distinguished Visitor.  Prof. Mitra currently serves as Senior Associate Editor of the ACM Transactions on Embedded Computing Systems\, Deputy Editor-in-Chief of IEEE Embedded Systems Letters\, and Associate Editor of IEEE Design & Test Magazine. She has served as Associate Editor of IEEE TCAD and organizing/program committee member of almost all major conferences in embedded systems\, real-time systems\, and electronic design automation including program chair of EMOSFT and CASES.
URL:https://www.cecs.uci.edu/event/accelerated-computing-for-edge-centric-iot/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190129T150000
DTEND;TZID=America/Los_Angeles:20190129T160000
DTSTAMP:20231011T190843Z
CREATED:20231011T190827Z
LAST-MODIFIED:20231011T190843Z
UID:14547-1548774000-1548777600@www.cecs.uci.edu
SUMMARY: Partial logic synthesis and its application to automatic generation of parallel/distributed algorithms
DESCRIPTION:Name: Masahiro Fujita\nDate and Time: Thursday\, January 14 at 3:00 p.m. \nLocation:Engineering Hall 3206 \nAbstract: In this talk first we review the partial logic synthesis problem and its associated\nalgorithm based on QBF (Quantified Boolean Formula) formulation. Partial logic synthesis\nis to generate appropriate sub-circuits for the missing portions in the target design so that\nthe entire circuit becomes equivalent to the specification which is separately given. Then\nwe show the problem to automatically generate distributed/parallel computing for the\ngiven specification can be defined as partial logic synthesis problem. Taking matrix-vector\nproduct computation as an example\, we show how theoretical optimum distributed/parallel\ncomputation can be automatically generated targeting many cores/chips which are\nconnected through a ring connection. \nBiography: Masahiro Fujita receivedh is Ph.D. in Information Engineering from the\nUniversity of Tokyo in 1985 on his work on model checking of hardware designs by using\nlogic programming languages. In 1985\, he joined Fujitsu as a researcher and started to\nwork on hardware automatic synthesis as well as formal verification methods and tools\,\nincluding enhancements of BDD/SAT-based techniques. Since March 2000\, he has been a\nprofessor at VLSI Design and Education Center of the University of Tokyo. He has been\ninvolved in a Japanese governmental research project for dependable system designs and\nhas developed a formal verifier for C programs that could be used for both hardware and\nembedded software designs. He has authored and co-authored 10 books\, and has more\nthan 200 publications.
URL:https://www.cecs.uci.edu/event/partial-logic-synthesis-and-its-application-to-automatic-generation-of-parallel-distributed-algorithms/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190307T150000
DTEND;TZID=America/Los_Angeles:20190307T160000
DTSTAMP:20231011T190843Z
CREATED:20231011T190828Z
LAST-MODIFIED:20231011T190843Z
UID:14549-1551970800-1551974400@www.cecs.uci.edu
SUMMARY:"Poly-Logarithmic Side Channel Rank Estimation via Exponential Sampling"
DESCRIPTION:Name: Liron David\nDate and Time: Tuesday\, March 12 at 10:00 a.m. \nLocation: Engineering Hall 5204 \nAbstract: \nRank estimation is an important tool for a side-channel evaluations laboratories. It allows estimating the remaining security after an attack has been performed\, quantified as the time complexity and the memory consumption required to brute force the key given the leakages as probability distributions over d subkeys (usually key bytes). These estimations are particularly useful where the key is not reachable with exhaustive search. \nWe propose ESrank\, the first rank estimation algorithm that enjoys provable poly-logarithmic time- and space-complexity\, which also achieves excellent practical performance. Our main idea is to use exponential sampling to drastically reduce the algorithm’s complexity. Importantly\, ESrank is simple to build from scratch\, and requires no algorithmic tools beyond a sorting function. After rigorously bounding the accuracy\, time and space complexities\, we evaluated the performance of ESrank on a real SCA data corpus\, and compared it to the currently-best histogram-based algorithm. We show that ESrank gives excellent rank estimation (with roughly a 1-bit margin between lower and upper bounds)\, with a performance that is on-par with the Histogram algorithm: a run-time of under 1 second on a standard laptop using 6.5 MB RAM. \nBiography: \nLiron David is a Ph.D. candidate in Electrical Engineering at Tel-Aviv University under the supervision of Prof. Avishai Wool. She received her B.Sc. degree in Computer Science and Electrical and Electronics Engineering from Tel-Aviv University and her M.Sc. degree in Electrical Engineering from Tel-Aviv University. Liron has won the Weinstein award for excellence in studies in 2017 \,the Weinstein best paper prize in 2018 and the Tel-Aviv University excellence in teaching in 2018.
URL:https://www.cecs.uci.edu/event/poly-logarithmic-side-channel-rank-estimation-via-exponential-sampling/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190501T150000
DTEND;TZID=America/Los_Angeles:20190501T160000
DTSTAMP:20231011T190852Z
CREATED:20231011T190846Z
LAST-MODIFIED:20231011T190852Z
UID:14555-1556722800-1556726400@www.cecs.uci.edu
SUMMARY:"Safety Verification and Training for Learning-enabled Cyber-Physical Systems"
DESCRIPTION:Name: Jyotirmoy Vinay Deshmukh\nDate and Time: Tuesday\, May 14\, 2019 at 2:00 p.m. \nLocation: Donald Bren Hall 4011 \nAbstract: \nWith the increasing popularity of deep learning\, there have been several efforts to use neural network based controllers in cyber-physical system applications. However\, neural networks are equally well-known for their lack of interpretability\, explainability and verifiability. This is especially an issue for safety-critical cyber-physical systems such as unmanned aerial vehicles or autonomous ground vehicles. How can we verify that a neural network based controller will always keep the system safe? We look at a new verification approach based on automatically synthesizing a barrier certificate for the system to prove that: starting from a given set of initial conditions\, the system behavior can never reach an unsafe state. Barrier Certificates are essentially a generalization of inductive invariants for continuous dynamical systems\, and we will show how we can use nonlinear SMT solvers to establish the barrier certificate conditions. A more intriguing challenge is whether we can actually train neural networks to obey safety constraints. We will look at a new way of reward shaping in reinforcement learning that could help achieve this goal. \nBiography: \nJyotirmoy V. Deshmukh (Jyo) is an assistant professor in the Department of Computer Science in the Viterbi School of Engineering at the University of Southern California in Los Angeles\, USA. Before joining USC\, Jyo worked as a Principal Research Engineer in Toyota Motors North America R&D. He got his Ph.D. degree from the University of Texas at Austin and was a post-doctoral fellow at the University of Pennsylvania. Jyo’s research interest is in the broad area of formal methods. Currently\, Jyo is interested in using logic-based methods for machine learning\, and in techniques for the analysis\, design\, verification and synthesis of cyber-physical systems\, especially those that use AI-based perception\, control and planning algorithms.
URL:https://www.cecs.uci.edu/event/safety-verification-and-training-for-learning-enabled-cyber-physical-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190703T150000
DTEND;TZID=America/Los_Angeles:20190703T160000
DTSTAMP:20231011T190852Z
CREATED:20231011T190846Z
LAST-MODIFIED:20231011T190852Z
UID:14557-1562166000-1562169600@www.cecs.uci.edu
SUMMARY:"Scalable Set-based Analysis for Verification of Cyber-Physical Systems”
DESCRIPTION:Name: Stanley Bak\nDate and Time: Tuesday\, July 9\, 2019 \nLocation: Engineering Hall 2430 \nAbstract: \nCyber-physical systems combine complex physics with complex software. Although these systems offer significant potential in fields such as smart grid design\, autonomous robotics and medical systems\, verification of CPS designs remains challenging. Model-based design permits simulations to be used to explore potential system behaviors\, but individual simulations do not provide full coverage of what the system can do. In particular\, simulations cannot guarantee the absence of unsafe behaviors\, which is unsettling as many CPS are safety-critical systems. \nThe goal of set-based analysis methods is to explore a system’s behaviors using sets of states\, rather than individual states. The usual downside of this approach is that set-based analysis methods are limited in scalability\, working only for very small models. This talk describes our recent process on improving the scalability of set-based reachability computation for LTI hybrid automaton models\, some of which can apply to very large systems (up to one billion continuous state variables!). Lastly\, we’ll discuss the significant overlap of techniques used for our scalable reachability analysis methods with set-based input/output analysis of neural networks. \nBiography: \nStanley Bak is a research computer scientist investigating the formal verification of cyber-physical systems. He strives to create scalable and automatic formal analysis methods for complex models with both ordinary differential equations and discrete behaviors. The ultimate goal is to make formal approaches applicable\, which demands developing new theory\, programming efficient tools and building experimental systems. \nStanley Bak received a Bachelor’s degree in Computer Science from Rensselaer Polytechnic Institute (RPI) in 2007 (summa cum laude)\, a Master’s degree in Computer Science from the University of Illinois at Urbana-Champaign (UIUC) in 2009\, and a PhD from UIUC in 2013. He received the Founders Award of Excellence for his undergraduate research at RPI in 2004\, the Debra and Ira Cohen Graduate Fellowship from UIUC twice\, in 2008 and 2009\, and was awarded the Science\, Mathematics and Research for Transformation (SMART) Scholarship from 2009 to 2013. Stanley worked as a research computer scientist for the Air Force Research Laboratory (AFRL) from 2013 to 2018\, both in the Information Directorate and the Aerospace Systems Directorate. Currently\, he helps run Safe Sky Analytics\, a small research consulting company working with the FAA and the Air Force.
URL:https://www.cecs.uci.edu/event/scalable-set-based-analysis-for-verification-of-cyber-physical-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20191016T150000
DTEND;TZID=America/Los_Angeles:20191016T160000
DTSTAMP:20231011T190904Z
CREATED:20231011T190900Z
LAST-MODIFIED:20231011T190904Z
UID:14568-1571238000-1571241600@www.cecs.uci.edu
SUMMARY:"Energy-Aware Data Center Management: Monitoring Trends and Insights via Machine Learning"
DESCRIPTION:Name: Hayk Shoukourian\nDate and Time: Friday\, November 15\, 2019 \nLocation: Donald Bren Hall 3011 \nAbstract: \nThe increasing demand for online resources has led to an immense energy burden on contemporary\nHigh Performance Computing (HPC) and cloud data centers. Even though each new generation of HPC systems delivers a higher power efficiency\, the growth in system density and overall performance has continuously contributed to an increase in energy consumption. The mentioned energy consumption not only converts to high operational bills and affects the environment\, but also influences the stability of the underlying power grid. In fact\, all these have already led some governmental organizations to reconsider data center deployment procedures with an increased demand for the renewable energy utilization and waste heat recovery. \nThe talk will give an overview of Leibniz Supercomputing Centre (LRZ)\, introduce its flagship HPC systems\, discuss the high-temperature direct liquid cooling solution and the waste heat reuse. These will be followed by the recent R&D results that rely on ML technologies for forecasting various energy/power consumption relevant Key Performance Indicators at a data center building infrastructure level. The talk will highlight the applications of the developed model outlining its use in proactive management of modern data centers for tackling the above-mentioned challenges. \nBiography: \nDr. Hayk Shoukourian received his M.Sc. and PhD in Computer Science from Technical University of Munich in 2012 and 2015 correspondingly. He joined Leibniz Supercomputing Centre (LRZ) in 2012 and his R&D activities mainly involve efficient energy/power consumption management of the HPC data centers. In his current role\, Dr. Shoukourian is responsible for adaptive modelling of interoperability between the target HPC systems and the building infrastructure of the supercomputing site. He is also a team leader for PRACE (Partnership for Advanced Computing in Europe) work package on “HPC Commissioning and Prototyping”. Since August 2018 Dr. Shoukourian is a lecturer in Computer Science at Ludwig-Maximilians-Universität München (LMU).
URL:https://www.cecs.uci.edu/event/energy-aware-data-center-management-monitoring-trends-and-insights-via-machine-learning/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20200227T100000
DTEND;TZID=America/Los_Angeles:20200227T110000
DTSTAMP:20231011T190957Z
CREATED:20231011T190957Z
LAST-MODIFIED:20231011T190957Z
UID:14576-1582797600-1582801200@www.cecs.uci.edu
SUMMARY:"Answering Multi-Dimensional Analytical Queries under Local Differential Privacy"
DESCRIPTION:Name: Tianhao Wang\nDate and Time: Thursday\, February 27\, 2020 \nLocation: Engineering Hall 2430 \nAbstract: \nWhen collecting information\, local differential privacy (LDP) relieves users’ privacy concerns\, as it adds noise to users’ private information.  The LDP technique has been deployed by Google\, Apple\, and Microsoft for data collection and monitoring.  In this talk\, I will share the key algorithms we developed in a Chinese e-commercial company Alibaba.  We study the problem of answering multi-dimensional queries under LDP.  Several algorithms are proposed to handle queries with different types of predicates and aggregation functions.  We built a prototype that enables different departments to collect\, share\, and analyze data within the company. \nBiography: \nTianhao Wang is a Ph.D. candidate in the department of computer science\, Purdue University\, advised by Prof. Ninghui Li. He received his B.Eng. degree from software school\, Fudan University in 2015. His research interests include differential privacy and local differential privacy. He is a recipient of the Bilsland Dissertation Fellowship and the Emil Stefanov Memorial Fellowship. He was a member of DPSyn\, which won the second-place award in the NIST PSCR Differential Privacy Synthetic Data Challenge.
URL:https://www.cecs.uci.edu/event/answering-multi-dimensional-analytical-queries-under-local-differential-privacy/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220517T140000
DTEND;TZID=America/Los_Angeles:20220517T150000
DTSTAMP:20231011T032340Z
CREATED:20231011T032340Z
LAST-MODIFIED:20231011T032340Z
UID:14133-1652796000-1652799600@www.cecs.uci.edu
SUMMARY:"Beyond Approximate Computing: Quality-Scalability for Low-Power Embedded Systems and Machine Learning"
DESCRIPTION:Speaker: Younghyun Kim\nDate and Time: Tuesday\, May 17\, 2022 at 2:00 p.m. \nLocation: Zoom https://uci.zoom.us/j/98632011722 \nAbstract: \nApproximate computing is a new paradigm to accomplish energy-efficient computing in this twilight of Moore’s law by relaxing the exactness requirement of computation results for intrinsically error-resilient applications\, such as deep learning and signal processing\, and producing results that are “just good enough.” It exploits that the output quality of such error-resilient applications is not fundamentally degraded even if the underlying computations are greatly approximated. This favorable energy-quality tradeoff opens up new opportunities to improve the energy efficiency of computing\, and a large body of approximate computing methods for energy-efficient “data processing” have been proposed. In this talk\, I will introduce approximate computing methods to accomplish “full-system energy-quality scalability.” It extends the scope of approximation from the processor to other system components including sensors\, interconnects\, etc.\, for energy-efficient “data generation” and “data transfer” to fully exploit the energy-quality tradeoffs across the entire system. I will also discuss how approximate computing can benefit the implementation of machine learning on ultra low-power embedded systems. \nBiography: \nProf. Younghyun Kim is an Assistant Professor in the Department of Electrical and Computer Engineering and an ECE Grainger Faculty Scholar at the University of Wisconsin-Madison\, where leads the Wisconsin Embedded Systems and Computing (WISEST) Laboratory (https://wisest.ece.wisc.edu/). Prof. Kim received his B.S. degree in computer science and engineering and his Ph.D. degree in electrical engineering and computer science from Seoul National University in 2007 and 2013\, respectively. He was a Postdoctoral Research Assistant at Purdue University and a visiting scholar at the University of Southern California. His current research interests include energy-efficient computing and security and privacy of the Internet-of-Things. Prof. Kim was a recipient of several awards\, including the NSF Faculty Early Career Development Program (CAREER) Award\, Facebook Research Award\, IEEE Micro Top Pick\, the EDAA Outstanding Dissertation Award\, and the Design Contest Awards at the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED). He served on the Technical Program Committees of various conferences on design automation and embedded systems\, including the Design Automation Conference (DAC)\, ISLPED\, Asia and South Pacific Design Automation Conference (ASP-DAC)\, International Conference on VLSI Design (VLSID)\, and Symposium on Applied Computing (SAC). He served as a Guest Editor for a Special Issue of VLSI Integration Journal (Elsevier). \nHosted By: Prof. Nikil Dutt \n 
URL:https://www.cecs.uci.edu/event/beyond-approximate-computing-quality-scalability-for-low-power-embedded-systems-and-machine-learning/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220523T140000
DTEND;TZID=America/Los_Angeles:20220523T150000
DTSTAMP:20231011T032340Z
CREATED:20231011T032340Z
LAST-MODIFIED:20231011T032340Z
UID:14135-1653314400-1653318000@www.cecs.uci.edu
SUMMARY:"Runtime Monitoring of Distributed Cyber-physical Systems"
DESCRIPTION:Speaker: Borzoo Bonakdarpour\nDate and Time: Monday\, May 23\, 2022 at 2:00 pm \nLocation: DBH 3011 \nAbstract:  \nWe consider the problem of detecting violations of specification In the signal temporal logic over distributed continuous-time and continuous-valued signals in cyber-physical systems (CPS). We assume a partially synchronous setting\, where a clock synchronization algorithm guarantees a bound on clock drifts among all signals. We introduce a novel retiming method that allows reasoning about the correctness of predicates among continuous-time signals that do not share a global view of time. The resulting problem is encoded as an SMT problem and we introduce techniques to solve the SMT encoding efficiently. Leveraging simple knowledge of physical dynamics allows further runtime reductions. We will discuss case studies on monitoring a network of autonomous ground vehicles\, a network of aerial vehicles\, and a water distribution system. \nBiography: Borzoo Bonakdarpour is currently an Associate Professor of Computer Science at Michigan State University. His research interests include formal methods and its application in distributed systems\, computer security\, and cyber-physical systems. He has published more than 100 articles and papers in top journals and conferences. His work in these areas have received multiple best paper awards from highly prestigious conferences\, including\, RV’21\, SRDS’17\, SSS’14\, and SIES’10. He chaired the Technical Program Committee of the SRDS’20\, SSS’16\, and RV’14 conferences. \nHosted By: Prof. Eli Bozorgzadeh \n 
URL:https://www.cecs.uci.edu/event/runtime-monitoring-of-distributed-cyber-physical-systems/
LOCATION:DBH 3011\, Donald Bren Hall University of California\, Irve\, Irvine\, CA\, 92617\, United States
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220707T140000
DTEND;TZID=America/Los_Angeles:20220707T150000
DTSTAMP:20231011T032340Z
CREATED:20231011T032340Z
LAST-MODIFIED:20231011T032340Z
UID:14134-1657202400-1657206000@www.cecs.uci.edu
SUMMARY:"Anti-virus hardware: Applications in Embedded\, Automotive and Power Systems Security"
DESCRIPTION:Speaker: Kanad Basu\nDate and Time: Tuesday\, June 7\, 2:00 pm \nLocation: Zoom https://uci.zoom.us/j/97807443602 \nAbstract: \nAnti-virus software (AVS) tools are used to detect Malware in a system. However\, software-based AVS are vulnerable to attacks. A malicious entity can exploit these vulnerabilities to subvert the AVS. Recently\, hardware components such as Hardware Performance Counters (HPC) have been used for Malware detection\, in the form of Anti-virus Hardware (AVH). In this talk\, we will discuss HPC-based AVHs for improving embedded security and privacy. Furthermore\, we will discuss the application of HPCs in security cyber physical systems (CPS)\, namely automotive and microgrid systems. Subsequently\, we will discuss their pitfalls. Finally\, we will present PREEMPT\, a zero overhead\, high-accuracy and low-latency technique to detect Malware by re-purposing the embedded trace buffer (ETB)\, a debug hardware component available in most modern processors.  PREEMPT combines these hardware-level observations with machine learning-based classifiers to preempt Malware before it can cause damage. We will conclude the talk with future research directions and challenges. \nBiography: \nKanad Basu received his Ph.D. from the department of Computer and Information Science and Engineering\, University of Florida. His thesis was focused on improving signal observability for post-silicon validation. Post-PhD\, Kanad worked in various semiconductor companies like IBM and Synopsys. During his PhD days\, Kanad interned at Intel. Currently\, Kanad is an Assistant Professor at the Electrical and Computer Engineering Department of the University of Texas at Dallas\, where he leads the Trustworthy and Intelligent Embedded Systems (TIES) lab. Prior to this\, Kanad was an Assistant Research Professor at the Electrical and Computer Engineering Department of NYU. He has authored 1 book\, 2 US patents\, 2 book chapters and several peer reviewed journal and conference articles. His research is supported by SRC\, NSF\, DARPA and Ford Motors. Kanad was awarded the ”Best Paper Award” at the International Conference on VLSI Design 2011 and an honorable mention award at the same conference in 2021. Several News agencies have covered his research including NBC Austin and CBS Dallas-Fort Worth. Kanad’s current research interests are hardware and systems security as well as Deep learning hardware. \nHosted By: Prof. Nikil Dutt \n 
URL:https://www.cecs.uci.edu/event/anti-virus-hardware-applications-in-embedded-automotive-and-power-systems-security/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220715T100000
DTEND;TZID=America/Los_Angeles:20220715T110000
DTSTAMP:20231011T032348Z
CREATED:20231011T032346Z
LAST-MODIFIED:20231011T032348Z
UID:14137-1657879200-1657882800@www.cecs.uci.edu
SUMMARY:"Electric Power to the People: Secure & Resilient Cyber-Physical Systems in the Age of Renewable Energy"
DESCRIPTION:Speaker: Charalambos Konstantinou\nDate and Time: Friday\, July 15\, 10:00 am \nLocation: EH 2430 \nAbstract: \nRapid advancements in power electronics along with the increasing penetration of distributed energy resources (DERs) are transforming the electric power grids. Furthermore\, increasing types and number of loads and electric transportation are stressing the network. Overall\, the power system is facing unprecedented changes in operation and control as more and diverse sources and loads are being connected to this complex cyber-physical energy system. In light of this modernization\, and due to the growing number of Internet-of-things (IoT) connected controllers\, and the use of communication and control interfaces\, making cyber-physical energy systems resilient to high-impact\, low-probability cyber-physical adverse events\, such as cyber-attacks\, is a major priority for power grid operations. Such incidents\, if left unabated\, can intensify and elicit system dynamics instabilities\, eventually causing outages and system failures. In this talk\, we will give an overview of the research of the Secure Next Generation Resilient Systems (SENTRY) lab (sentry.kaust.edu.sa) at KAUST\, presenting different methodologies\, in the age of renewable energy\, contributing towards building secure and resilient cyber-physical grids. \nBiography: \nCharalambos Konstantinou is an Assistant Professor of Computer Science (CS) and Affiliate Professor of Electrical and Computer Engineering (ECE) at the Computer\, Electrical and Mathematical Science and Engineering Division (CEMSE) of King Abdullah University of Science and Technology (KAUST)\, Thuwal\, Saudi Arabia. He is the Principal Investigator of the SENTRY Lab (Secure Next Generation Resilient Systems – sentry.kaust.edu.sa) and a member of the Resilient Computing and Cybersecurity Center (RC3 – rc3.kaust.edu.sa) at KAUST. Before joining KAUST in 2021\, he was an Assistant Professor with the Center for Advanced Power Systems (CAPS) at Florida State University (FSU). His research interests are in secure\, trustworthy\, and resilient cyber-physical and embedded IoT systems. He is also interested in critical infrastructures security and resilience with special focus on smart grid technologies\, renewable energy integration\, and real-time simulation. He received a Ph.D. in Electrical Engineering from New York University (NYU)\, NY\, in 2018\, and an M.Eng. Degree in Electrical and Computer Engineering from National Technical University of Athens (NTUA)\, Greece\, in 2012. \nHosted By: Prof. Mohammad Al Faruque \n 
URL:https://www.cecs.uci.edu/event/electric-power-to-the-people-secure-resilient-cyber-physical-systems-in-the-age-of-renewable-energy/
LOCATION:EH 2430\, Engineering Hall\, University of California\, Irvine\, Irvine\, CA\, 92697\, United States
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220802T140000
DTEND;TZID=America/Los_Angeles:20220802T150000
DTSTAMP:20231011T032348Z
CREATED:20231011T032346Z
LAST-MODIFIED:20231011T032348Z
UID:14138-1659448800-1659452400@www.cecs.uci.edu
SUMMARY:“Securing Hardware for Designing Trustworthy Systems”
DESCRIPTION:Speaker: Prabhat Mishra\nDate and Time: Tuesday\, August 2\, 2:00 pm \nLocation: DBH 4011 OR Zoom Link \nAbstract: \nSystem-on-Chip (SoC) is the brain behind computing and communication in a wide variety of embedded systems. Reusable hardware Intellectual Property (IP) based SoC design has emerged as a pervasive design practice in the industry to dramatically reduce SoC design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs\, often gathered from untrusted third-party vendors\, severely affects the security and trustworthiness of computing platforms. It is crucial to evaluate the integrity and trustworthiness of third-party IPs for designing trustworthy systems. In this talk\, I will introduce a wide variety of hardware security vulnerabilities\, design-for-security solutions\, and possible attacks and countermeasures. I will briefly describe how the complementary abilities of simulation-based validation\, formal verification as well as side channel analysis can be effectively utilized for comprehensive SoC security and trust validation. \nBiography: \nPrabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering and a UF Research Foundation Professor at the University of Florida. He received his Ph.D. in Computer Science from the University of California at Irvine in 2004. His research interests include embedded and cyber-physical systems\, hardware security and trust\, energy-aware computing\, system-on-chip validation\, machine learning\, and quantum computing. He has published 8 books\, 35 book chapters\, and more than 200 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award\, IBM Faculty Award\, three best paper awards\, and EDAA Outstanding Dissertation Award. He currently serves as an Associate Editor of IEEE Transactions on VLSI Systems and ACM Transactions on Embedded Computing Systems. He is an IEEE Fellow and an ACM Distinguished Scientist. \nHosted By: Prof. Nikil Dutt \n 
URL:https://www.cecs.uci.edu/event/securing-hardware-for-designing-trustworthy-systems/
LOCATION:DBH 4011\, Donald Bren Hall\, University of California\, Irvine\, Irvine\, CA\, 92617\, United States
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220810T110000
DTEND;TZID=America/Los_Angeles:20220810T120000
DTSTAMP:20231011T032348Z
CREATED:20231011T032346Z
LAST-MODIFIED:20231011T032348Z
UID:14139-1660129200-1660132800@www.cecs.uci.edu
SUMMARY:"DRAC: Designing RISC-V-based Accelerators for next generation Computers"
DESCRIPTION:Speaker: Miquel Moreto\nDate and Time: Wednesday\, August 10\, 11:00 am \nLocation: DBH 3011 OR Zoom Link \nAbstract: \nDesigning RISC-V-based Accelerators for next-generation Computers (DRAC) is a 3-year project (2019-2022) funded by the ERDF Operational Program of Catalonia 2014-2020. DRAC will design\, verify\, implement and fabricate a high-performance general purpose processor that will incorporate different accelerators based on the RISC-V technology\, with specific applications in the field of post-quantum security\, genomics\, and autonomous navigation. In this talk\, we will provide an overview of the main achievements in the DRAC project\, including the fabrication of Lagarto\, the first RISC-V processor developed in Spain. \nBiography: \nMiquel Moreto is a Ramon y Cajal Fellow at the Computer Architecture Departament (DAC) at the Universitat Politècnica de Catalunya (UPC)\, and he leads the High Performance Domain Specific Architectures team at the Barcelona Supercomputing Center (BSC). Miquel received his Ph.D. from UPC in 2010. After finishing the PhD\, he spent 15 months at the International Computer Science Institute (ICSI)\, affiliated with UC Berkeley\, as a Fulbright Postdoctoral Research Fellowship Holder during 2011 and 2012. In 2013\, he returned to Barcelona to work on multiple European projects (RoMoL\, Mont-Blanc\, EPI\, DeepHealth\, eProcessor) and industrial projects (Arm\, IBM\, Lenovo). In 2019\, he led the design and fabrication of Lagarto\, the first processor developed in Spain based on the open source RISC-V instruction set architecture. Currently\, he coordinates the DRAC project\, which is promoting the Lagarto initiative with new generations of the Lagarto processor and accelerators. \nHosted By: Prof. Veidenbaum \n 
URL:https://www.cecs.uci.edu/event/drac-designing-risc-v-based-accelerators-for-next-generation-computers/
LOCATION:DBH 3011\, Donald Bren Hall University of California\, Irve\, Irvine\, CA\, 92617\, United States
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20220929T110000
DTEND;TZID=America/Los_Angeles:20220929T120000
DTSTAMP:20231011T032348Z
CREATED:20231011T032346Z
LAST-MODIFIED:20231011T032348Z
UID:14140-1664449200-1664452800@www.cecs.uci.edu
SUMMARY:"Design Automation and Computing based on Additive Printed Electronics”
DESCRIPTION:Speaker: Mehdi Tahoori\nDate and Time: Thursday\, September 29\, 11:00 am \nLocation: EH 2430 \nAbstract: \nPrinted electronics is an emerging and fast-growing field which can be used in many demanding and emerging application domains such as wearables\, smart sensors\, and Internet of Things (IoT). Unlike traditional computing and electronics domain which is mostly driven by performance characteristics\, printed and flexible electronics based on additive manufacturing processes are mainly associated with low fabrication costs and low energy. Printed electronics offer certain technological advantages over their silicon-based counterparts\, such as mechanical flexibility\, low process temperatures\, maskless and additive manufacturing possibilities. Electrolyte gated transistors (EGTs) using solution-processed inorganic materials which are fully printed using inkject printers at low temperatures are very promising to provide such solutions. However\, due to low device count\, large device dimension and high variabilities\, originated in low-cost additive manufacturing\, existing design automation and computing paradigms of digital VLSI are not applicable to printed electronics. This talk covers the technology\, process\, modeling\, fabrication\, design automation\, computing paradigms and security aspects of circuits and systems based on additive printed technologies. \nBiography: \nMehdi B. Tahoori is Professor and the Chair of Dependable Nano-Computing at Karlsruhe Institute of Technology (KIT)\, Germany. He received the B.S. degree in computer engineering from Sharif University of Technology\, Tehran\, Iran\, in 2000\, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University\, Stanford\, CA\, in 2002 and 2003\, respectively. He is currently the deputy editor-in-chief of IEEE Design and Test Magazine. He was the editor-in-chief of Elsevier Microelectronic Reliability journal. He was the program chair of IEEE VLSI Test Symposium in (VTS) in 2021 and 2018\, and General Chair of IEEE European Test Symposium (ETS) in 2019. Prof. Tahoori was a recipient of the US National Science Foundation Early Faculty Development (CAREER) Award in 2008 and European Research Council (ERC) Advanced Grant in 2022. He has received a number of best paper nominations and awards at various conferences and journals. He is currently the chair of IEEE European Test Technologies Technical Council (eTTTC). He is a fellow of the IEEE. \nHosted by: Prof. Bozorgzadeh \n 
URL:https://www.cecs.uci.edu/event/design-automation-and-computing-based-on-additive-printed-electronics/
LOCATION:EH 2430\, Engineering Hall\, University of California\, Irvine\, Irvine\, CA\, 92697\, United States
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20221103T150000
DTEND;TZID=America/Los_Angeles:20221103T160000
DTSTAMP:20231011T032352Z
CREATED:20231011T032352Z
LAST-MODIFIED:20231011T032352Z
UID:14147-1667487600-1667491200@www.cecs.uci.edu
SUMMARY:"Programmability\, Scalability\, and Security for Reconfigurable Computing in the Cloud"
DESCRIPTION:Speaker: Prof. Deming Chen\, University of Illinois at Urbana-Champaign (UIUC)\nDate and Time: Thursday\, November 3rd\, 3:00 pm \nLocation: EH 2430 or Zoom Link \nAbstract:  \nReconfigurable Computing uses FPGAs (Field-Programmable Gate Arrays) as an alternative to microprocessors to enable high-performance and low-energy customized computing. It is becoming a mainstream technology as evident by Intel’s $16.7B acquisition of Altera in 2015 and AMD’s $49B acquisition of Xilinx in 2022. However\, challenges remain in terms of FPGA programmability\, scalability\, and security before reconfigurable computing makes a transformative impact in the computing world\, especially in the cloud. In this talk\, Dr. Chen will present some new concepts and research results that demonstrate initial promises to overcome these challenges\, including shared virtual memory system for computing with FPGAs\, scalable high-level synthesis for FPGA programming\, and trusted execution environment with accelerators. These results are developed within the AMD-Xilinx Center of Excellence and the Hybrid-Cloud Thrust of the IBM-Illinois Discovery Accelerator Institute at UIUC. \nBio:  \nDeming Chen is the Abel Bliss Professor of the Grainger College of Engineering at University of Illinois at Urbana-Champaign (UIUC). His current research interests include reconfigurable computing\, hybrid cloud\, system-level design methodologies\, machine learning and acceleration\, and hardware security. He has published more than 250 research papers\, received ten Best Paper Awards and one ACM/SIGDA TCFPGA Hall-of-Fame Paper Award\, and given more than 140 invited talks. He is an IEEE Fellow\, an ACM Distinguished Speaker\, and the Editor-in-Chief of ACM Transactions on Reconfigurable Technology and Systems (TRETS). He is the Director of the AMD-Xilinx Center of Excellence and the Hybrid-Cloud Thrust Co-Lead of the IBM-Illinois Discovery Accelerator Institute at UIUC. He has been involved in several startup companies\, such as AutoESL and Inspirit IoT. He received his Ph.D. from the Computer Science Department of UCLA in 2005. \nHosted By: Prof. Sitao Huang \n 
URL:https://www.cecs.uci.edu/event/programmability-scalability-and-security-for-reconfigurable-computing-in-the-cloud/
LOCATION:EH 2430\, Engineering Hall\, University of California\, Irvine\, Irvine\, CA\, 92697\, United States
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR