BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:CECS X-ORIGINAL-URL:https://www.cecs.uci.edu X-WR-CALDESC:Events for CECS REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20150308T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20151101T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20160313T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20161106T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20170312T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20171105T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20180311T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20181104T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20190310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20191103T090000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20160929T150000 DTEND;TZID=America/Los_Angeles:20160929T160000 DTSTAMP:20231011T190611Z CREATED:20231011T190611Z LAST-MODIFIED:20231011T190611Z UID:14464-1475161200-1475164800@www.cecs.uci.edu SUMMARY:CMOS Process Variations: A “Critical Operation Point” Hypothesis DESCRIPTION:Title: CMOS Process Variations: A “Critical Operation Point” Hypothesis\nSpeaker: Dr. Janak H. Patel \nDate: May 2\, 2012 \nTime: 3:30-4:30 P.M. \nLocation: DBH 3011 \nHost: Professor Nikil Dutt \n  URL:https://www.cecs.uci.edu/event/cmos-process-variations-a-critical-operation-point-hypothesis/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20160929T150000 DTEND;TZID=America/Los_Angeles:20160929T160000 DTSTAMP:20231011T190612Z CREATED:20231011T190612Z LAST-MODIFIED:20231011T190612Z UID:14466-1475161200-1475164800@www.cecs.uci.edu SUMMARY:Resilience is a Critical Issue for Large-scale Platform DESCRIPTION:Speaker:  Prof. Yves Robert\, Ecole Normale Supérieure de Lyon\, France \nTitle:  Resilience is a Critical Issue for Large-scale Platform \nDate:  Monday\, May 18\, 2015 \nTime:  11:00 a.m. – 12:00 p.m. \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost:  Prof. Jean-Luc Gaudiot \nAbstract: Resilience is a critical issue for large-scale platforms. This talk will survey fault-tolerant techniques for high-performance computing:\n– Overview of failure types and typical probability distributions\n– Brief discussion of application-specific techniques\, such as ABFT\n– The standard general-purpose technique\, checkpoint and     rollback recovery\n– Recent extensions with replication\, prediction and silent error detection\n– Relevant execution scenarios\, evaluated and compared through quantitative models.\nThe talk includes several illustrative examples and targets a general audience. \nBio: Yves Robert received his PhD degree from Institut National Polytechnique de Grenoble. He is currently a full professor in the Computer Science Laboratory LIP at ENS Lyon. He is the author of 7 books\, 130+ papers published in international journals\, and 200+ papers published in international conferences.  He is the editor of 11 book proceedings and 13 journal special issues.  He is the advisor of 28 PhD theses.  His main research interests are scheduling techniques and resilient algorithms for large-scale platforms. Yves Robert served on many editorial boards\, including IEEE TPDS.  He was the program chair of HiPC’2006 in Bangalore\, IPDPS’2008 in Miami\, ISPDC’2009 in Lisbon\, ICPP’2013 in Lyon and HiPC’2013 in Bangalore. He is a Fellow of the IEEE. He has been elected a Senior Member of Institut Universitaire de France in 2007 and renewed in 2012.  He has been awarded the 2014 IEEE TCSC Award for Excellence in Scalable Computing.  He holds a Visiting Scientist position at the University of Tennessee\, Knoxville since 2011. \n  \n  URL:https://www.cecs.uci.edu/event/resilience-is-a-critical-issue-for-large-scale-platform/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20160929T150000 DTEND;TZID=America/Los_Angeles:20160929T160000 DTSTAMP:20231011T190612Z CREATED:20231011T190612Z LAST-MODIFIED:20231011T190612Z UID:14467-1475161200-1475164800@www.cecs.uci.edu SUMMARY:Hardware Security in the Zynq All-Programmable Soc DESCRIPTION:Title: “Hardware Security in the Zynq All-Programmable Soc”\nSpeaker: Dr. Steve Trimberger\, Xilinx \nDate:  Friday\, October 2\, 2015 \nTime:  2:00 p.m. \nLocation:  Donald Bren Hall 4011 \nHost: Prof. Fadi J. Kurdahi \nAbstract: FPGAs have grown from a simple logic replacement to fully-programmable SoC\, with multi-core CPU subsystems\, a broad spectrum of peripherals\, hundreds of thousands of gates of programmable logic and high-speed multi-gigabit transceivers. As the complexity of the underlying hardware has grown\, so has the value of the applications built in them and the data handled by them. Traditional FPGA bitstream security has been enhanced to address these greater security requirements. This talk presents an overview of hardware security issues and the security features of the Zynq All- Programmable SoC. The secure boot process includes asymmetric and symmetric authentication as well as symmetric encryption to protect software and programmable hardware during programming.During operation the hardware can disable test ports\, monitor on-chip power and temperature and detect tampering with configuration data. ARM Trust Zone is integrated through the AXI busses into both the processor and the programmable logic subsystems. \nBio: Dr. Stephen Trimberger holds a M.S. degree in ICS from UCI and a Ph.D. degree from California Institute of Technology. Since 1988\, he has been employed at Xilinx\, where he is currently Xilinx Fellow heading the Circuits and Architectures Group in Xilinx Research Labs in San Jose\, California. He was the technical leader for the XC4000 design automation software\, developed a dynamically -reconfigurable multi-context FPGA\, led the architecture definition group for the Xilinx XC4000X device families and designed the Xilinx bitstream security functions in the Virtex families of FPGAs. He led the group that developed the first die- stacked 3D FPGA prototype at Xilinx. He has served as Design Methods Chair for the Design Automation Conference\, Program Chair and General Chair for the ACM/SIGDA FPGA Symposium and on the technical programs of numerous Workshops and Symposia. He has authored five books and dozens of papers on design automation\, FPGA architectures and hardware security. He has more than 220 patents in IC design\, FPGA and ASIC architecture\, CAE\, hardware security and cryptography. His innovations appear today in nearly all commercial FPGA devices. He is a Fellow of the ACM and a Fellow of the IEEE. \nView Details Here \n  URL:https://www.cecs.uci.edu/event/hardware-security-in-the-zynq-all-programmable-soc/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20161104T150000 DTEND;TZID=America/Los_Angeles:20161104T160000 DTSTAMP:20231011T190622Z CREATED:20231011T190622Z LAST-MODIFIED:20231011T190622Z UID:14477-1478271600-1478275200@www.cecs.uci.edu SUMMARY:Adaptive Design: Tackling Variability Challenges in VLSI Circuits DESCRIPTION:Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”\nSpeaker: Professor Mingoo Seok\, Columbia University\, New York \nDate:  Friday\, April 22\, 2016 \nTime:  3:00PM \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Prof. Payam Heydari \nAbstract: In this talk\, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage\, chip temperature\, manufacturing process\, and transistor aging have imposed a large amount of pessimistic margins in clock frequency\, voltage\, and device size\, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead\, in-situ\, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage\, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing\, (3) self-testing circuits and frameworks for in-field & in-situ aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented. \nBio: \nMingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University\, South Korea\, in 2005\, and the MS and PhD degree from University of Michigan in 2007 and 2011\, respectively\, all in electrical engineering. He was a member of technical staff in Texas Instruments\, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems\, including ultra-low-power computing systems\, computing systems for machine learning\, adaptive circuits and architecture\, and non-conventional computing systems. \nHe received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies\, 2005 Doctoral Fellowship from the same organization\, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013\, and IEEE Transactions on VLSI Systems since 2015. URL:https://www.cecs.uci.edu/event/adaptive-design-tackling-variability-challenges-in-vlsi-circuits/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20161105T150000 DTEND;TZID=America/Los_Angeles:20161105T160000 DTSTAMP:20231011T190623Z CREATED:20231011T190623Z LAST-MODIFIED:20231011T190623Z UID:14478-1478358000-1478361600@www.cecs.uci.edu SUMMARY:Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow DESCRIPTION:Title:  “Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow”\nSpeaker: Christian Krieg\, Vienna University of Technology\, Vienna\, Austria \nDate and Time: Thursday\, November 17\, 2016 at 2:00 PM \nLocation: Donald Bren Hall 3011 \nHost:  Professor Nikil Dutt \nAbstract: We present a novel type of Trojan trigger targeted at the field-programmable gate array (FPGA) design flow. Traditional triggers base on rare events\, such as rare values or sequences. While in most cases these trigger circuits are able to hide a Trojan attack\, exhaustive functional simulation and testing will reveal the Trojan due to violation of the specification. Our trigger behaves functionally and formally equivalent to the hardware description language (HDL) specification throughout the entire FPGA design flow\, until the design is written by the place-and-route tool as bitstream configuration file. From then\, Trojan payload is always on. We implement the trigger signal using a 4-input lookup table (LUT)\, each of the inputs connecting to the same signal. This lets us directly address the least significant bit (LSB) and most significant bit (MSB) of the LUT. With the remaining 14 bits\, we realize a “magic” unary operation. This way\, we are able to implement 16 different Triggers. We demonstrate the attack with a simple example and discuss the effectiveness of the recent detection techniques unused circuit identification (UCI)\, functional analysis for nearly-unused circuit identification (FANCI) and VeriTrust in order to reveal our trigger. \nBiography: Christian Krieg received the bachelor’s and master’s degree in electrical engineering from TU Wien and is now pursuing his PhD studies on hardware security at TU Wien. His research focuses on design-level hardware Trojan design and detection. He also works on reasonable threat models for hardware Trojan attacks. Christian recently received the William McCalla best paper award for a novel hardware Trojan implementation. At a wider scope\, Christian’s research interests include cyber-physical systems security and IoT security. \nView Details URL:https://www.cecs.uci.edu/event/malicious-lut-a-stealthy-fpga-trojan-injected-and-triggered-by-the-design-flow/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20161105T150000 DTEND;TZID=America/Los_Angeles:20161105T160000 DTSTAMP:20231011T190623Z CREATED:20231011T190623Z LAST-MODIFIED:20231011T190623Z UID:14480-1478358000-1478361600@www.cecs.uci.edu SUMMARY:High Level Synthesis - Some Challenging Problems DESCRIPTION:Title: “High Level Synthesis – Some Challenging Problems”\nSpeaker: George A. Constantinides\, Imperial College London\, UK \nDate and Time: Wednesday\, November 16\, 2016 at 11:00 A.M. \nLocation: Engineering Hall 2430 \nHost: Professor Nikil Dutt \nAbstract: High Level Synthesis – synthesis of circuits from behavioral descriptions – is a long-standing problem\, but one that appears to now have come to age. Both the demand for\, and the supply of\, quality HLS tools is now in place. However\, there are still some hard problems to be overcome in order to make HLS fully general. My research focuses on two of these: customization of memory systems to algorithms\, and customization of number representation to algorithms. After briefly introducing the work at Imperial – and encouraging PhD and postdoc applications (!) – I will spend a little time on each of these problems. In particular\, I will look at the problem of customization of memory for heap manipulating programs\, the potential of parametric analysis for synthesis of lightweight run-time scheduling changes\, and automates code refactoring for rigorously controlled accuracy / latency / area optimization. I hope to inspire the audience to consider how you may be able to contribute to these problems. \nBiography: Prof George A. Constantinides holds the Royal Academy of Engineering / Imagination Technologies Chair in Digital Computation at Imperial College London\, where he leads the Circuits and Systems research group. He has been a member of staff at Imperial since 2001. Over this time he has been the proud supervisor of 25 graduated PhD students and chaired the FPGA\, FPT\, and FPL conferences. He enjoys hard problems and espresso. \nView more here URL:https://www.cecs.uci.edu/event/high-level-synthesis-some-challenging-problems/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20161107T150000 DTEND;TZID=America/Los_Angeles:20161107T160000 DTSTAMP:20231011T190616Z CREATED:20231011T190616Z LAST-MODIFIED:20231011T190616Z UID:14472-1478530800-1478534400@www.cecs.uci.edu SUMMARY:Low Energy\, a New Trend for Lightweight Cryptography DESCRIPTION:Title: “Low Energy\, a New Trend for Lightweight Cryptography”\nSpeaker: Dr. Francesco Regazzoni\, ALaRI Institute of Università della Svizzera italiana\, Lugano\, Switzerland \nDate and Time:  Wednesday\, February 1\, 2017 at 11:00 a.m. \nLocation: DBH 4011 \nHost: Prof. Nikil Dutt \nAbstract: In the last decade\, several lightweight block ciphers and hash functions have been proposed. One of the metrics\, so far largely unexplored\, which has to be used to identify a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers\, this operation is the encryption of one plaintext. \nThis talk will address several approaches for reducing the energy consumption of existing block ciphers\, touching the design space of the AES algorithm\, to which few algorithmic optimizations are applied. \nThe gained experience lead to the design of Midori\, the first block cipher designed to optimize the energy consumed per bit in encryption or decryption operation. Each component of the circuit\, as well as its entire architecture of the cipher\, have been optimized for energy\, and design choices leading to low energy consumption in an electrical circuit were taken. Achieved results demonstrate that the energy consumption of Midori64 and Midori128 is much lower that current stateof the art.\n \nBiography: Dr. Francesco Regazzoni is a senior researcher at the the ALaRI Institute of Universita’ della Svizzera italiana (Lugano\, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at the ALaRI Institute of Universita’ della Svizzera italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft\, and visiting researcher at several institutions\, including NEC Labs America\, Ruhr University of Bochum\, EPFL\, and NTU Singapore. His research interests are mainly focused on embedded systems security\, covering in particular side channel attacks\, electronic design automation for security\, hardware Trojans\, low energy cryptography\, and post quantum security. He has published more than 70 journal and conference papers in the area of security and design automation\, and has been in the technical program committed of top conferences of the area. Francesco is the principal investigator and project leader at Universita’ della Svizzera italiana of the projects (SAFECrypto\, exploring lattice-based constructions as building blocks for quantum resistant cryptography)\, and CERBERO (design tools for Cyber-Physical Systems). \nView Details Here URL:https://www.cecs.uci.edu/event/low-energy-a-new-trend-for-lightweight-cryptography/ LOCATION:CA CATEGORIES:Seminars at CECS ATTACH;FMTTYPE=image/png:https://cecs.uci.edu/files/2023/10/francescoreg-seminar-YBo8Ni.tmp_.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20170417T150000 DTEND;TZID=America/Los_Angeles:20170417T160000 DTSTAMP:20231011T190631Z CREATED:20231011T190631Z LAST-MODIFIED:20231011T190631Z UID:14484-1492441200-1492444800@www.cecs.uci.edu SUMMARY:Heterogeneous Chip Architectures for Big Data Analytics DESCRIPTION:Title: “Heterogeneous Chip Architectures for Big Data Analytics”\nSpeaker: Houman Homayoun\, George Mason University\, Virginia \nDate and Time: Friday\, April 28\, 2017 at 11:00AM \nLocation: 2430 Engineering Hall \n \nAbstract: \nThere is a fundamental shift underway now in various industry sectors to transport their big data to the clouds\, thus increasing their efficiency and improving cash flow. In addition to traditional web service sector\, this also includes sectors such as telecommunication (e.g.\,  software defined network  applications)\, and healthcare (e.g.\, GE Cloud Health and Cloud PACS ). Cloud servers to process big data are now aggregating multiple disparate workloads with heterogeneously structured and unstructured data (image\, text\, video\, graph) with varying performance goals (batch\, streaming\, real-time\, and near-real-time). Emerging analytics applications in these domains rely heavily on specific deep machine learning and mining algorithms\, and are running complex database software stack with significant interaction with I/O and OS and sharing many inherent characteristics that are fundamentally different from traditional CPU and parallel applications. Emerging big data applications require computing resources that can efficiently scale to manage massive amounts of diverse data. However\, the rapid growth in the data yields challenges to process them efficiently using current cloud server architectures such as high performance Xeon. Furthermore\, physical design constraints\, such as power and density\, have become the dominant limiting factor for scaling out servers. To respond to these challenges\, heterogeneous architectures which integrates big and little cores with FPGA accelerators has emerged as a promising solution. In this talk\, through methodical investigation of power and performance measurements\, and comprehensive system level and micro-architectural analysis\, I first show the characterization results of emerging big data applications on big Xeon and little Atom-based servers. The characterization results across a wide range of real-world big data applications and various software stacks demonstrate how the choice of big vs little core-based server for energy-efficiency is significantly influenced by the size of data\, performance constraints\, and presence of accelerator. Furthermore\, the microarchitecture-level analysis highlights where improvement is needed in big and little core servers. \nSecond\, I will show how in a heterogeneous architecture effective mapping of Hadoop and Spark MapReduce based applications to FPGA accelerator can significantly increase the energy-efficiency and performance. The real-system results show promising kernel speedup of more than 100X and significant energy-efficiency gains. \nBiography: \nHouman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University. He also holds a joint appointment with the Department of Computer Science as well as Information Science and Technology Department. He is the director of GMU’s Green Computing and Heterogeneous Architectures (GOAL) Laboratory. Prior to joining George Mason University\, Houman spent two years at the University of California\, San Diego\, as National Science Foundation Computing Innovation (CI) Fellow awarded by the Computing Research Association (CRA) and the Computing Community Consortium (CCC). \nHouman’s research is in big data computing\, heterogeneous computing\, hardware security and trust\, and spans the areas of computer design and embedded systems\, where he has published more than 70 technical papers in the most prestigious conferences and journals on the subject. He is currently leading a number of research projects\, including the design of next generation heterogeneous architectures for big data processing\, non-volatile STT logic to prevent design reverse engineering\, heterogeneous accelerator platforms for wearable biomedical computing\, and logical vanishable design to enhance hardware security which are all funded by National Science Foundation (NSF)\, General Motors Company (GM)\, National Institute of Standards and Technology (NIST)\, Defense Advanced Research Projects Agency (DARPA)\, and Air Force Research Laboratory(AFRL). He received the 2016 GLSVLSI conference best paper award. He is currently serving as an Associate Editor of IEEE Transactions on VLSI (TVLSI). \nHouman received his PhD degree from the Department of Computer Science at the University of California\, Irvine in 2010\, an MS degree in computer engineering in 2005 from University of Victoria\, Canada and his BS degree in electrical engineering in 2003 from Sharif University of Technology. URL:https://www.cecs.uci.edu/event/heterogeneous-chip-architectures-for-big-data-analytics/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20170605T150000 DTEND;TZID=America/Los_Angeles:20170605T160000 DTSTAMP:20231011T190636Z CREATED:20231011T190636Z LAST-MODIFIED:20231011T190636Z UID:14487-1496674800-1496678400@www.cecs.uci.edu SUMMARY:Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics DESCRIPTION:Title:  “Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics”\nSpeaker: Prof. Axel Jantsch\, TU Wien \nDate and Time:  Friday\,  June 16\, 2017 at 11 A.M. \nLocation: 2430 Engineering Hall \nHost: Prof. Nikil Dutt \nAbstract: In healthcare\, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs of deterioration exist as early as 24 hours prior having a serious impact on the health of a person. As hospitalization times have to be minimized\, in-home or remote early warning systems can fill the gap by allowing in-home care while having the potentially problematic conditions and their signs under surveillance and control. This walk presents a remote monitoring and diagnostic system that provides a holistic perspective of patients and their health conditions. It discusses how the concept of self-awareness can be used in various parts of the system such as information collection through wearable sensors\, confidence assessment of the sensory data\, the knowledge base of the patient’s health situation\, and automation of reasoning about the health situation. This approach to self-awareness provides \n(i) situation awareness to consider the impact of variations such as sleeping\, walking\, running\, and resting\, \n(ii) system personalization by reflecting parameters such as age\, body mass index\, and gender\, and \n(iii) the attention property of self-awareness to improve the energy efficiency and dependability of the system via adjusting the priorities of the sensory data collection.\nBiography: \n Axel Jantsch received the Dipl.Ing. and Dr. Tech. degrees from TU Wien\, Vienna\, Austria\, in 1988 and 1992\, respectively. He was with Siemens Austria\, Vienna\, Austria\, as a system validation engineer from 1995 to 1997. From 1997 to 2002 he was an associate professor and from 2002 to 2014 he was full professor of Electronic Systems Design at the Royal Institute of Technology (KTH)\, Stockholm\, Sweden. Since 2014 he has been professor of Systems on Chip at TU Wien. He has published about 300 papers in international conferences and journals and one book in the areas of Systems on chip\, networks on chip and embedded systems. He has served on a large number of technical program committees of international conferences\, such as FDL\, DATE\, CODES ISSS\, SOC\, NOCS\, and others. He has been the TPC Chair of SSDL/ FDL 2000\, the TPC Co-Chair of CODES ISSS 2004\, the General Chair of CODES ISSS 2005\, and the TPC Co-Chair of NOCS 2009. From 2002 to 2007\, he was a subject area editor for the Journal of System Architecture. He is on the editorial board for IEEE Design and Test and for the Leibniz Transactions on Embedded Systems. He is a member of the IEEE. His main research interest is on networks on chip and self-awareness in systems on chip and embedded systems.\n\n\nView Details Here URL:https://www.cecs.uci.edu/event/self-awareness-in-remote-health-monitoring-systems-using-wearable-electronics/ LOCATION:CA CATEGORIES:Seminars at CECS ATTACH;FMTTYPE=image/png:https://cecs.uci.edu/files/2023/10/axel_jantsch_seminar-iBdaHY.tmp_.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20170607T150000 DTEND;TZID=America/Los_Angeles:20170607T160000 DTSTAMP:20231011T190637Z CREATED:20231011T190637Z LAST-MODIFIED:20231011T190637Z UID:14488-1496847600-1496851200@www.cecs.uci.edu SUMMARY:Mobile and Emerging Computing Systems: challenges and research opportunities DESCRIPTION:Title: “Mobile and Emerging Computing Systems: challenges and research opportunities”\nSpeaker: Dr. Raid Ayoub\, Intel Strategic CAD Lab\, Portland\, Oregon\, USA \nDate and Time: Friday\, June 23\, 2017 at 11:00AM-12:00PM \nLocation: DBH 3011 \nAbstract: \nThe computing systems have been evolving at a fast pace and they are increasingly ubiquitous. This trend is driven by advancements in mobile technologies and emerging of Internet-of-Things (IoT) as well as new applications. However\, the complexity and diversity of these systems continue to rise\, which require transformative design automation solutions to meet stringent design metrics\, e.g. time-to-market. This talk will address research problems in mobile computing at the system level with some emphasis on energy efficiency and power budgeting of the CPU-GPU subsystem as well as user-experience related problems (e.g. skin temperature estimation and control). In addition\, this talk will discuss emerging challenges and future research problems in the domain of IoT systems with a focus on End-to-End system design. \nBiography: \nRaid Ayoub received his Ph.D. degree in computer engineering from the department of computer science and engineering\, University of California at San Diego in 2011.Currently he is a research scientist at the Strategic CAD Labs of Intel Corporation. He has published more than 30 journal and conference papers. His research interests include run-time optimizations\, dynamic control\, system modeling\, human cyber-physical systems/IoT\, dynamic power and thermal management\, machine learning\, and design automation. URL:https://www.cecs.uci.edu/event/mobile-and-emerging-computing-systems-challenges-and-research-opportunities/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20170614T150000 DTEND;TZID=America/Los_Angeles:20170614T160000 DTSTAMP:20231011T190708Z CREATED:20231011T190700Z LAST-MODIFIED:20231011T190708Z UID:14498-1497452400-1497456000@www.cecs.uci.edu SUMMARY:"Optimizing Private Local Memories in Heterogeneous Architectures" DESCRIPTION:Title: “Optimizing Private Local Memories in Heterogeneous Architectures”\nSpeaker: Christian Pilato\, Università della Svizzera italiana (USI)\, Lugano\, Switzerland \nDate and Time: Wednesday\, June 14\, 2017 at 11:00AM-12:00PM \nLocation: ICS 432 \nAbstract: \nModern Systems-on-Chip (SoC) architectures and state-of-the-art computing platforms that integrate CPUs with FPGAs are heterogeneous systems featuring an increasing number of hardware accelerators. Private local memories play a key role in the design of these components both with respect to performance optimization and because they are responsible for most of their area and power dissipation. Each local memory unit is usually implemented with a multibank microarchitecture based on the combined requirements of each hardware block accessing the corresponding data. However\, the creation of these multibank memory microarchitectures is not well supported by current design flows\, and the designers must perform this tedious and error-prone process manually. \nIn this talk\, I will present a system-level methodology for the generation of multi-bank memories in heterogeneous architectures. The methodology is supported by Mnemosyne\, an open-source prototype CAD tool that can be easily integrated into commercial design flows. Mnemosyneincludes various technology-aware optimizations to reduce the memory cost (area and power) by efficiently reusing the physical banks for storing different data. With Mnemosyne\,we can reduce the memory cost of single accelerators by up to 45%. Moreover\, when reusing memory IPs across accelerators\, we achieve area savings that range between 17% and 55% compared to the case where the memory elements are designed separately. \nBiography: \nChristian Pilato is a Postdoctoral Researcher at the ALaRi institute of Università della Svizzera italiana (USI)\, Lugano\, Switzerland. He received the Laurea degree in computer engineering and the Ph.D. degree in information technology from Politecnico di Milano\, Italy\, in 2007 and 2011\, respectively. From 2013 to 2016\, he was a Postdoctoral Research Scientist with the Department of Computer Science\, Columbia University\, USA. He has been visiting researcher at NanGate\, Chalmers University of Technology\, and Delft University of Technology. 
His current research interests include high-level synthesis\, reconfigurable systems and system-on-chip architectures\, with emphasis on memory aspects. He has actively participated in several projects sponsored by the European Union and DARPA\, as well as a research center supported by SRC. Dr. Pilato served as the Program Chair of the Embedded and Ubiquitous Conference (EUC) in 2014. He is currently involved in the program committees of many conferences on embedded systems\, CAD\, and reconfigurable architectures\, such as FPL\, DATE\, and CASES. He is a Member of IEEE and ACM.
 URL:https://www.cecs.uci.edu/event/optimizing-private-local-memories-in-heterogeneous-architectures/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20170731T150000 DTEND;TZID=America/Los_Angeles:20170731T160000 DTSTAMP:20231011T190638Z CREATED:20231011T190638Z LAST-MODIFIED:20231011T190638Z UID:14489-1501513200-1501516800@www.cecs.uci.edu SUMMARY:Accelerators and Enablement for Application-Specific Multicore Platforms DESCRIPTION:Title: “Accelerators and Enablement for Application-Specific Multicore Platforms”\n\nSpeaker: Dr. Andreas Herkersdorf\, Electrical & Computer Engineering\, Technische Universität München\n\nDate and Time: Monday\, July 31\, 2017 at 2:00PM-3:00PM \nLocation: DBH 3011 \nAbstract: Multicore technology plays a pivotal role in conquering key societal challenges. For example\, safe\, ecological mobility\, wide-spread rollout of eHealth\, smart industrial automation and the development of a secure\, high-bandwidth\, low-latency mobile communication infrastructure for Industry 4.0\, all these application domains are critically dependent on high-performance\, low power and dependable computing. However\, multicore technology also comes with a number of unique challenges for industry and academia. Today\, the efficient utilization of massively parallel computing resources largely depends on the experience of individual programmers. \nApplication-specific accelerators and generic enablement building blocks for Multicore System on Chip (MCSoC) platforms are research foci at the Chair for Integrated Systems at TU München. These building blocks support a more performant\, energy efficient\, easier to use and more resilient deployment of multicore processors by application programmers and system integrators. In my talk\, I will present current and past research projects on wire-speed traffic distribution among Software Defined Networking (SDN) nodes\, interconnect virtualization for Network on Chip and processing node resilience\, efficient multicore deployment in legacy automotive CAN networks and on-chip diagnosis for effective software debugging. \nBiography: Andreas Herkersdorf is a professor at the Department of Electrical and Computer Engineering and also adjunct to the Department of Informatics at Technische Universität München (TUM). He received the diploma degree from TUM in 1987 and the Dr. degree from ETH Zurich\, Switzerland\, in 1991\, both in electrical engineering. Between 1988 and 2003\, he has been a research staff member and manager at the IBM Zurich Research Laboratory in Rüschlikon\, Switzerland. \nSince 2003\, Dr. Herkersdorf is head of the Chair for Integrated Systems at TUM. He is a senior member of the IEEE\, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer\, Elsevier and deGruyter journals for design automation\, communications electronics and information technology. His research interests include application-specific multi-processor architectures\, IP network processing\, Network on Chip\, system level SoC modeling and design space exploration methods\, and self-aware fault-tolerant computing. URL:https://www.cecs.uci.edu/event/accelerators-and-enablement-for-application-specific-multicore-platforms/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20170807T150000 DTEND;TZID=America/Los_Angeles:20170807T160000 DTSTAMP:20231011T190642Z CREATED:20231011T190642Z LAST-MODIFIED:20231011T190642Z UID:14494-1502118000-1502121600@www.cecs.uci.edu SUMMARY:Part I: “Development of Low-End Embedded Processors for Some SoC Applications” Part II: “The Application-Specific Design for Signal Processing Applications” DESCRIPTION:Title: Part I: “Development of Low-End Embedded Processors for Some SoC Applications”Part II: “The Application-Specific Design for Signal Processing Applications” \nSpeaker: Prof. Fitzgerald Sungkyung Park\, Pusan National University\, Busan\, South Korea\nProf. Chester Park\, Konkuk University\, Seoul\, Korea \nDate and Time: Monday\, August 7\, 2017\, 2:00 PM – 3:00 PM \nLocation: Donald Bren Hall 3011 \nAbstract: \nLow-end processor cores can be utilized in various SoC applications including IoT\, wireless communication\, and machine learning.  In this short talk\, we will introduce how we designed some low-end integer cores applied to some applications such as deeply embedded IoT and WLAN MAC Soc\, and also introduce the basic design of embedded cores for neural networks. \nPart II: The application-specific design for signal processing applications tends to necessitate multi-disciplinary knowledge on system\, algorithm\, architecture and circuit levels.  In this talk\, we will introduce our application-specific design approaches for various signal processing applications.  In addition\, we discuss several design challenges involved in system-on-a-chip (SoC) design for neural networks\, regarding how to customize the on-chip bus architecture. \nBiography: \nProf. Fitzgerald Sungkyung Park took his Ph.D. degree in electronics engineering from Seoul National University\, Korea\, in 2002. He worked for Samsung Electronics from 2002 to 2004\, joined Electronics and Telecommunications Research Institute (ETRI) from 2004 to 2006\, and worked for Ericsson\, Inc.\, USA\, from 2006 to 2009\, where he developed mixed-signal circuits for radio transceivers. In 2009\, he joined the faculty of Pusan National University\, where he has worked on low-end processors and SoC for IoT and other applications. \nProf. Chester Park received his Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST)\, Korea\, in 2006. After about two years with Samsung Electronics Inc.\, Giheung\, Korea\, he joined Ericsson Research\, USA\, where he developed various signal processing algorithms for wireless communications. Since 2013\, he has been with Konkuk University\, Seoul\, Korea\, working on hardware accelerator design for signal processing algorithms. \n  URL:https://www.cecs.uci.edu/event/part-i-development-of-low-end-embedded-processors-for-some-soc-applications-part-ii-the-application-specific-design-for-signal-processing-applications/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20171003T150000 DTEND;TZID=America/Los_Angeles:20171003T160000 DTSTAMP:20231011T190642Z CREATED:20231011T190642Z LAST-MODIFIED:20231011T190642Z UID:14495-1507042800-1507046400@www.cecs.uci.edu SUMMARY:"Application Mapping Methodologies for NoC-Based MPSOCs" DESCRIPTION:Title: “Application Mapping Methodologies for NoC-Based MPSOCs”\nSpeaker: Jürgen Teich\, Friedrich-Alexander Universität Erlangen-Nürnberg (FAU) \nDate and Time: Tuesday\, November 14\, 2017 at 3:00PM-4:00PM \nLocation: DBH 4011 \nAbstract:  \nIn this talk\, we give an overview of novel techniques for systematically mapping applications to NoC-based multi-core architectures\n(MPSoCs). Complex applications requiring heterogenous processing resources are often described by task graphs\nwith data dependencies. Here\, the nodes represent actors or tasks which are typically activated periodically based on the\navailability of data. One prominent domain of applications fitting this model is stream processing. Here\, it is often important to guarantee\neither bandwidth or execution time requirements. But more recently\, also security\, energy and reliability aspects impose\nconstraints on the mapping of the tasks as well as their communication to cores\, respectively routes in the underlying NoC. \nConcerning mapping methodologies\, we first present a class of algorithms that perform “Self-Embedding”. The idea is here that\na source node issues a request to find appropriate resources to embed its sucessor tasks\, and so on.\nThe next class of techniques introduced is called “Hybrid Application Mapping (HAM)”. Here\, a careful analysis and\ncharacterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time)\nphase called “Design Space Exploration (DSE)”. At run-time\, the operating system then only needs to search within such\npre-analysed constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction.\nWe present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that\ndeadlines or throughput requirements will be automatically met for streaming applications.\nFinally\, we conclude with a discussion on resource constellations that may satisfy certain security requirements on an MPSoC. \nBiography: \nJürgen Teich is with Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)\, Germany\, where he is directing\nthe Chair for Hardware/Software Co-Design since 2003. He received the M.S. degree (Dipl.-Ing.; with honors)\nfrom the University of Kaiserslautern\, Germany in 1989 and the Ph.D. degree (Dr.-Ing.; summa cum laude)\nfrom the University of Saarland\, Saarbruecken\, Germany\, in 1993. In 1994\, he joined the DSP design group of Prof. E. A. Lee\nin the Department of Electrical Engineering and Computer Sciences (EECS)\, University of California at\nBerkeley (PostDoc). From 1995 to 1998\, he held a position at the Institute of Computer Engineering and\nCommunications Networks Laboratory (TIK)\, ETH Zurich\, Switzerland with his Habilitation\non the topic of `Synthesis and Optimization of Digital Hardware/Software Systems’ in 1996.\nFrom 1998 to 2002\, he was Full Professor in the Electrical Engineering and Information Technology\nDepartment\, University of Paderborn\, Germany. \nHis current research focuses on electronic design automation of embedded systems\nwith emphasis on hardware/software co-design\, reconfigurable computing and multi-core systems.\nProf. Teich has organized various ACM/IEEE conferences/symposia as Program Chair\nincluding CODES+ISSS´07\, FPL´08\, ASAP´10\, and DATE´2016.\nHe serves regularly as a TPC member of many program committees including DAC\, ASP-DAC\, ICCAD\, FPL\,\nASAP\, FPT\, FPGA\, RECONFIG\, ESTIMEDIA\, VLSI Design\, GECCO\, EMO\, RTSS\, etc.\nHe also serves in the editorial board of journals including ACM TODAES\, IEEE Design and Test and JES and has\nedited two text books on Hardware/Software Co-Design and recently a Handbook on this topic (Springer). \nProf. Teich is involved in many interdisciplinary projects on basic research as well as industrial projects.\nFrom 2003-2009\, he was an elected board member (Fachkollegiat) of the Deutsche Forschungsgemeinschaft (DFG)\nfor the area of Computer Architecture and Embedded Systems. He has been the initiator and\ncoordinator of the DFG priority programme 1148 on “Reconfigurable Computing”.\nSince 2010\, he has also been the principal coordinator of the Transregional\nResearch Center 89 “Invasive Computing” funded by the German Research Foundation (DFG).\nIn 2011\, he was elected member of the Academia Europaea. \n  URL:https://www.cecs.uci.edu/event/application-mapping-methodologies-for-noc-based-mpsocs/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20171003T150000 DTEND;TZID=America/Los_Angeles:20171003T160000 DTSTAMP:20231011T190642Z CREATED:20231011T190642Z LAST-MODIFIED:20231011T190642Z UID:14496-1507042800-1507046400@www.cecs.uci.edu SUMMARY:“Detecting Hardware Trojans Hidden in Unspecified Design Functionality” DESCRIPTION:Title: “Detecting Hardware Trojans Hidden in Unspecified Design Functionality”\nSpeaker: Dr. Nicole Fern\, University of California\, Santa Barbara \nDate and Time: Thursday\, November 16th\, 2017 at 2:00PM-3:00PM \nLocation: Donald Bren Hall 3011 \nAbstract: \nTraditional verification methods and metrics attempt to answer the question: does my design correctly perform the intended functionality?  This talk will look at hardware verification from a security perspective\, which demands the verification effort answer an additional question: does my design perform malicious functionality in addition to the intended functionality?  The talk will motivate through examples why Hardware Trojans modifying only unspecified design functionality are both powerful and stealthy.  RTL don’t cares and idle cycles in on-chip bus protocols are two examples of unspecified functionality vulnerable to malicious modification that this talk will explore in depth.  This talk will also detail how to formulate the Trojan detection problem as a satisfiability problem in order to leverage existing formal verification tools to highlight Trojans hidden in unspecified functionality. \nBiography:  \nNicole Fern received her undergraduate degree in Electrical Engineering from The Cooper Union for the Advancement of Science and Art and her PhD degree in the ECE department at UC Santa Barbara under the advisement of Professor Tim Cheng.  She is now a post-doc at UC Santa Barbara.  Her thesis work focused on developing techniques to verify the absence of Hardware Trojans in unspecified design functionality.  Her current research interests include investigating security issues in emerging memory technologies and at the hardware/software boundary. \n  \n  URL:https://www.cecs.uci.edu/event/detecting-hardware-trojans-hidden-in-unspecified-design-functionality/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20171106T150000 DTEND;TZID=America/Los_Angeles:20171106T160000 DTSTAMP:20231011T190708Z CREATED:20231011T190700Z LAST-MODIFIED:20231011T190708Z UID:14497-1509980400-1509984000@www.cecs.uci.edu SUMMARY:“ThirdEye: Visual Assist for Grocery Shopping” DESCRIPTION:Title: “ThirdEye: Visual Assist for Grocery Shopping”\nSpeaker: Prof. Vijaykrishnan Narayanan\, Pennsylvania State University\, USA \nDate and Time: Wednesday\, November 15\, 2017 at 11:00AM-12:00PM \nLocation: 2430 Engineering Hall \nAbstract: \nShopping is widely considered as a relaxing leisure activity. However\, grocery shopping can be a frustrating experience for those with visual impairment. While getting to a grocery shop itself is not as much of a challenge for them\, locating and picking the items in the grocery shelf becomes a task as challenging as picking a needle from the haystack. Imagine picking up five items for your dinner recipe from a typical grocery store in the US that carries around 35\,000 unique items and can have more than 30 aisles spanning 45\,000 square meters. This talk will showcase synergistic advances in algorithms\, architectures and interface design for assisting those with visual impairment to do shopping. We will specifically focus on new non-boolean hardware approaches to significantly impact the energy-efficiency of the overall system. \nBiography: \nVijay Narayanan is a Distinguished Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is the director of the NSF Expeditions-in-Computing Program on Visual Cortex on Silicon and a thrust leader for the DARPA-MARCO LEAST Center. He has published more than 400 papers and won several awards in recognition of his research in power-aware systems\, embedded systems and computer architecture. He is a fellow of IEEE and ACM. \n  URL:https://www.cecs.uci.edu/event/thirdeye-visual-assist-for-grocery-shopping/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20171107T150000 DTEND;TZID=America/Los_Angeles:20171107T160000 DTSTAMP:20231011T190708Z CREATED:20231011T190701Z LAST-MODIFIED:20231011T190708Z UID:14499-1510066800-1510070400@www.cecs.uci.edu SUMMARY:"Network Resource Management in Cyber-Physical Systems" DESCRIPTION:Title: “Network Resource Management in Cyber-Physical Systems”\nSpeaker: Dr. Xiabo Sharon Hu\, University of Notre Dame\, USA \nDate and Time: Friday\, November 17\, 2017 at 2:00PM-3:00PM \nLocation: ICS 432 \nAbstract: \nA cyber-physical system (CPS) is a system built from close integration of computational fabrics and physical components. Examples of such systems include avionic systems\, industrial control and civil infrastructure monitoring. In a CPS\, sensors and actuators are used to monitor and control the physical components while the computational fabrics determine the control values for the actuators based on the sensed data. All CPSs require timely delivery of sensed data from sensors to the computing fabrics and control signals from the computing fabrics to actuators. Managing the limited resources (e.g.\, computation power and communication bandwidth) to meet the timing requirements in a CPS is a challenging task. Even more challenging is that CPSs should degrade gracefully in the presence of various external disturbances such as failure in critical civil infrastructures and malicious attacks. \nIn this talk\, I first give a general introduction of WNCSs and the challenges that they present to network resource management. In particular\, I will discuss the complications due to external disturbances and the need for dynamic data-link layer scheduling. I then highlight our recent work that aims at tackling this challenge. Our work balances the scheduling effort between a gateway (or access points) and the rest of the nodes in a network. It paves the way towards decentralized network resource management in\norder to achieve scalability. Experimental implementation on a wireless test bed further validates the applicability of our proposed research. I will end the talk outlining our on-going effort in this exciting and growing area of research. \nXiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana\, USA. Her research interests include low-power system design\, real-time embedded systems\, circuit and architecture design with emerging technologies\, and hardware/software co-design. She has published more than 300 papers in these areas\, and received the Best Paper Award from the Design Automation Conference in 2001 and from the IEEE Symposium\non Nanoscale Architectures in 2009. She is the General Chair of Design Automation Conference in 2018. She is an Associate Editor for ACM Transactions on Cyber- Physical Systems\, and also served as Associate Editor for IEEE Transactions on VLSI\, etc. Sharon Hu is a Fellow of the IEEE. \nBiography: \nXiaobo Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana\, USA. She also holds a joint appointment in the department of Electrical Engineering at the same university. She received B.S. degree from Tianjin University\, China\, M.S. degree from Polytechnic University of New York\, and Ph.D. degree from Purdue University. She worked for General Motors Research Labs for almost 4 years before she started her academic career. Between 1993 and 1996\, she was an assitant professor in the department of Electrical and Computer Engineering at Western Michigan University\, Kalamazoo\, Michigan\, USA. \nHer research interests include analysis and design of low power\, real-time\, and embedded systems\, computing with emerging technologies\, and computational medicine. She has published more than 200 referred papers in these areas and received numerous research grants from both the U.S. government agencies and private industry. She received the CAREER award from U.S. National Science Foundation in 1997. She received the Best Paper Award from the ACM/IEEE Design Automation Conference in 2001 and from the IEEE Symposium on Nanoscale Architectures in 2009. Another paper of hers was named one of “The Most Influential Papers of 10 Years Design\, Automation\, and Test in Europe Conference (DATE)”. \nSharon is currently Associate Editor for ACM Transactions on Embedded Computing and Co-Chair of the Technical Program Committee of 2014 Design Automation Conference (DAC). She also served as Associate Editor for IEEE Transactions on VLSI and ACM Transactions on Design Automation of Electronic Systems. She has served as guest editors for several different journals/magazines such as the IEEE Computer Magazine and IEEE Transactions on Industrial Informatics. She was the Technical Program Co-Chair of the 9th International Symposium on Hardware/Software Codesign (CODES’2001) and the General Co-Chair of the same conference in 2002. She also served or is serving on the program committee of a number of conferences such as Design Automation Conference (DAC)\, International Conference on Computer-Aided Design (ICCAD)\, Design\, Automation and Test in Europe Conference )DATE)\, IEEE Real-Time Systems Symposium (RTSS)\, and IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)\, etc. \nAt the University of Notre Dame\, Sharon had been the Director of Graduate Studies for 10 years in the department of Computer Science and Engineering\, and was Senior Assistant Provost for ND International between 2012–2013. Currently\, she is the Associate Dean for Professional Development at the Graduate School. \n \n  URL:https://www.cecs.uci.edu/event/network-resource-management-in-cyber-physical-systems/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20171128T150000 DTEND;TZID=America/Los_Angeles:20171128T160000 DTSTAMP:20231011T190718Z CREATED:20231011T190718Z LAST-MODIFIED:20231011T190718Z UID:14510-1511881200-1511884800@www.cecs.uci.edu SUMMARY:"I/O Optimization for Mobile Flash Storage" DESCRIPTION:Title: “I/O Optimization for Mobile Flash Storage”\nSpeaker: Prof. Chun Jason Xue\, City University of Hong Kong \nDate and Time: Tuesday\, December 5\, 2017 at 10:00AM-11:00AM \nLocation: DBH 3011 \nAbstract: \nNAND flash memory is the primary choice of data storage for mobile devices due to its high performance\, shock resistance and low power consumption. However\, compared to high-end solid-state drives\, mobile flash storage does not have the luxury of sophisticated hardware and firmware features because of the resource-constraint limits. Instead\, mobile flash storage often equipped with scarce built-in RAM\, slow embedded processors and low-cost flash memories\, all of which make it a challenge to apply traditional techniques for I/O performance improvements. This talk presents a couple of work that we have done recently to optimize I/O for Mobile Flash Storage. First\, this talk will introduce a novel I/O scheduling approach to improve demand-based page-level mapping cache performance. This technique generates mapping cache friendly I/O workloads by strengthening I/O locality at host I/O scheduler. Both temporal locality and spatial localities are taken into consideration for I/O scheduling. Second\, this talk will present a lightweight data compression technique at the flash controller to reduce write pressure on mobile flash storage. It first characterizes data compressibility based on real smartphones\, and the analysis shows that write traffics bound to mobile storage volumes are highly compressible. This technique is the first to investigate firmware-based data compression for mobile flash storage without adding extra data compression hardware. Experimental results demonstrate the proposed techniques outperform state-of-the-art schemes in terms of I/O latency and flash memory lifespan. \nBiography: \nDr. Chun Jason Xue is an Associate Professor at City University of Hong Kong Computer Science Department. His research interests include non-volatile memories\, embedded and real time systems. He is currently Associate Editor for ACM Transaction on Embedded Computing Systems\, Associate Editor for ACM Transaction on CPS\, Associated Editor for ACM Transaction on Storage. He was the TPC co-chair for LCTES 2015\, TPC co-char for ISVLSI 2016\, and has served as TPC members in premiere conferences such as DAC\, DATE\, RTSS\, RTAS\, CODES\, EMSOFT and ISLPED. URL:https://www.cecs.uci.edu/event/i-o-optimization-for-mobile-flash-storage/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20171221T150000 DTEND;TZID=America/Los_Angeles:20171221T160000 DTSTAMP:20231011T190718Z CREATED:20231011T190718Z LAST-MODIFIED:20231011T190718Z UID:14513-1513868400-1513872000@www.cecs.uci.edu SUMMARY:“Hierarchial Non-Intrusive In-Situ Requirements Monitoring for Embedded Systems” DESCRIPTION:Title:“Hierarchial Non-Intrusive In-Situ Requirements Monitoring for Embedded Systems”\nSpeaker: PhD Candidate Minjun Seo\, University of Arizona\, Tuscon \nDate and Time: Thursday\, December 21\, 2017 at 2:00PM-3:00PM \nLocation:  Engineering Hall 2430 \nAbstract: \nAccounting for all operating conditions of a system at the design stage is typically infeasible for complex systems. In-situ runtime monitoring and verification can enable a system to introspectively ensure the system is operating correctly in the presence of dynamic environment\, to rapidly detect failures\, and to provide detailed execution traces to find the root cause thereof. Two key challenges faced in using in-situ runtime verification for embedded systems include 1) efficiently defining and automatically constructing a requirements model for embedded system software and 2) minimizing the runtime overhead of observing and verifying the runtime execution adheres to the requirements model. In this talk\, we present a methodology to construct a hierarchical runtime monitoring graph from system requirements specified us- ing multiple UML sequence diagrams\, which are already commonly used in software development. We further present the design of on-chip hardware that nonintrusively monitors the system at runtime to ensure the execution matches the requirements model. We evaluate the proposed methodology using a case study of a fail-safe autonomous vehicle subsystem and analyze the relationship between event coverage\, detection rate\, and hardware requirements. \nBiography: \nMinjun Seo is a Ph.D. Candidate in the Department of Electrical and Computer Engineering at the University of Arizona.  His current research focuses on efficient specification and implementation of in-situ requirements monitoring of embedded systems. His research interests also include design tools and optimization methods supporting efficient verification hardware\, FPGAs\, and HW/SW co-design. Mr. Seo received a B.S. in Computer Science and Engineering in 2006 and a M.S. in Computer Science in 2008 from Kyungnam University. URL:https://www.cecs.uci.edu/event/hierarchial-non-intrusive-in-situ-requirements-monitoring-for-embedded-systems/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20180118T150000 DTEND;TZID=America/Los_Angeles:20180118T160000 DTSTAMP:20231011T190718Z CREATED:20231011T190718Z LAST-MODIFIED:20231011T190718Z UID:14511-1516287600-1516291200@www.cecs.uci.edu SUMMARY:"Digital Early Warning Scoring – A Cognitive IoT based approach" DESCRIPTION:Title: “Digital Early Warning Scoring – A Cognitive IoT based approach”\nSpeaker: Prof. Pasi Liljeberg\, University of Turku \nDate and Time: Thursday\, January 25\, 2018 at 2:00PM-3:00PM \nLocation: Engineering Hall 2430 \nAbstract: \nIn healthcare\, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs of deterioration exist as early as 24 hours prior having a serious impact on the health of a person. As hospitalization times have to be minimized\, in-home or remote early warning systems can fill the gap by allowing in-home care while having the potentially problematic conditions and their signs under surveillance and control. \nEarly warning score (EWS) is an approach to detect the deterioration of a patient. It is based on a fact that there are several changes in the physiological parameters prior a clinical deterioration of a patient. Currently\, EWS procedure is mostly used for in-hospital clinical cases and is performed in a manual paper-based fashion. However\, it is possible to build an automated EWS health monitoring system to intelligently monitor vital signs and prevent health deterioration for in-home and hospitalized patients using Internet-of-Things technologies. \nBiography: \nPasi Liljeberg received the MSc and PhD degrees in electronics and information technology from the University of Turku\, Turku\, Finland\, in 1999 and 2005\, respectively. He received Adjunct professorship in embedded computing architectures in 2010. Currently he is working as full professor in University of  Turku in the field of Embedded Systems and Internet of Things. At the moment his research is focused on biomedical engineering and health technology. In that context he has established and leading the Internet-of-Things for Healthcare\, IoT4Health\, ( http://iot4health.utu.fi [1] ) research group. Liljeberg is the author of more than 270 peer-reviewed publications. URL:https://www.cecs.uci.edu/event/digital-early-warning-scoring-a-cognitive-iot-based-approach/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20180206T150000 DTEND;TZID=America/Los_Angeles:20180206T160000 DTSTAMP:20231011T190718Z CREATED:20231011T190718Z LAST-MODIFIED:20231011T190718Z UID:14512-1517929200-1517932800@www.cecs.uci.edu SUMMARY:“Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins” DESCRIPTION:Title: “Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins”\nSpeaker: Prof. Sergio Bampi\, Informatics Institute – Microelectronics Design – Federal University of Rio Grande do Sul\, Brazil \nDate and Time: Thursday\, February 15\, 2018 at 2:00PM-3:00PM \nLocation: ICS 432 \nAbstract: \nPromising opportunities for research on heterogeneous Internet-of- Things (IoT) devices lie at the energy-bottom floor\, where CMOS is still an unbeatable\, flexible technology to make the internet of “everything” possible and cost-effective. Near-threshold computing (NTC) in CMOS is a promising alternative for any application which can tolerate or benefit from very wide voltage-frequency scaling (VFS). The digital blocks of devices may operate at very different power-performance modes\, from sub-MHz to peaks of hundreds of MHz\, which requires CMOS design libraries targeted for NTC. The analog and RF content on IoT chips will be even more crucial\, from a power-savings standpoint. In IoT it is best to avoid using costlier CMOS\, and yet closer to an end\, two-dimensional transistor and IC scaling. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific logic design techniques to be applied in digital CMOS. This talk addresses a method to design CMOS digital circuits for a wide dynamic range of VFS\, and targets near-threshold for best energy-efficiency. Our work on 65nm CMOS has demonstrated 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their system operating modes. The results in CMOS were obtained using the minimal cycle time achievable at each supply voltage\, down to very low 200 mV supplies. The strategy for transistor sizing in digital cells and static noise margin maximization will be addressed in particular. The seminar seeks to stimulate system-level and circuit-level design approaches for IoT nodes\, as the presenter is available to discuss digital\, mixed-signal\, and even RF aspects of CMOS systems-on- IoT-devices. \nBiography: \nSergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS\, 1979)\, and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics design fields at the Informatics Institute\, member of the faculty since 1986. He is a member of the PPGC Computing Graduate Program since 1988\, and of the PGMICRO since its start in 2002. He served as Graduate Program Coordinator (2003-2007)\, head of research group and projects\, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff\, and a visiting research faculty at Stanford University (1998-99). His research interests are in the area of IC design\, nano-CMOS devices\, mixed signal and RF CMOS design\, ultra-low power digital design\, dedicated complex algorithms\, architectures\, and ASICs for image and video processing. He has co-authored more than 360 papers in these fields and in MOS devices and EDA. He is a senior member of IEEE. He was Technical Program Chair of IEEE SBCCI Symposium (1997\, 2005)\, SBMICRO (1989\, 1995)\, IEEE LASCAS (2013)\, VARI 2016 Conferences and Workshops. URL:https://www.cecs.uci.edu/event/near-threshold-computing-the-bottom-floor-for-energy-in-iot-devices-and-its-vanishing-design-noise-margins/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20180222T150000 DTEND;TZID=America/Los_Angeles:20180222T160000 DTSTAMP:20231011T190729Z CREATED:20231011T190724Z LAST-MODIFIED:20231011T190729Z UID:14514-1519311600-1519315200@www.cecs.uci.edu SUMMARY:”Cost and Power Efficient Deep Neural Network Acceleration” DESCRIPTION:Title: “Cost and Power Efficient Deep Neural Network Acceleration”\nSpeaker: Associate Prof. Jongeun Lee\, School of ECE\, UNIST\, Ulsan\, Korea \nDate and Time: Monday\, February 26\, 2018 at 11:00am – 12:00pm \nLocation: EH 2430 \nAbstract: \nDeep neural networks prove to be a right direction after all\, but the enormous computational complexity calls for new research into novel ways of making efficient implementations of the connectionist model for small\, mobile devices. \nIn this talk I will discuss two directions\, one based on FPGA and the other based on a new computing paradigm called stochastic computing (SC).  FPGA is a very capable device housing thousands of processing elements in a single chip with low power consumption.  However\, FPGAs are very different from GPUs\, and making it easy to program FPGAs for deep neural networks is one of the key challenges facing FPGAs today.  I will present a design space exploration approach to help find the best design for a given FPGA and for a specific deep neural network model. \nStochastic computing (SC) was first introduced in the 60’s when computing devices were not very reliable.  Unlike conventional binary number representations\, stochastic computing uses a bitstream to represent a number\, and is therefore inherently more error-resilient. \nIn addition\, SC shares some good qualities with analog computing such as low power dissipation and low cost while strictly operating in the digital domain.  At the same time\, error fluctuation and conversion overhead are the key challenges facing SC today.  I will present a new SC architecture for deep neural networks that is much more accurate and efficient than previous SC solutions. \nBiography: \nJongeun Lee received his B.S. and M.S. in Electrical Engineering\, and his Ph.D. in electrical engineering and computer science all from Seoul National University\, Korea. In 2009 he joined UNIST (Ulsan National Institute of Science and Technology)\, Ulsan\, Korea\, where he is now an Associate Professor of Electrical and Computer Engineering. Prior to joining UNIST\, he worked as a postdoctoral research associate at Arizona State University\, and previously worked for Samsung Electronics. His current research interests include reconfigurable architectures\, compilers\, stochastic computing\, and deep neural networks. URL:https://www.cecs.uci.edu/event/cost-and-power-efficient-deep-neural-network-acceleration/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20180402T150000 DTEND;TZID=America/Los_Angeles:20180402T160000 DTSTAMP:20231011T190729Z CREATED:20231011T190725Z LAST-MODIFIED:20231011T190729Z UID:14515-1522681200-1522684800@www.cecs.uci.edu SUMMARY:"ASSISTECH: Assistive Technology for the Visually Impaired" DESCRIPTION:Title: “ASSISTECH: Assistive Technology for the Visually Impaired”\nSpeaker: Professor Mayandiambalam Balakrishnan\, CSE\, Indian Institute of Technology\, Delhi\, India \nDate and Time: Monday\, March 26 at 3:00PM-4:00PM \nLocation: Donald Bren Hall 4011 \nAbstract:  \nMore than ten years back we started on the ASSISTECH journey – a laboratory dedicated to finding\ntechnology solutions for the mobility and education of the visually impaired. It has been a very challenging but deeply fulfilling journey. Globally there are many technology solutions available for addressing the mobility as well as education needs of the visually impaired. Unfortunately they fail to address the challenges of mobility and education in India and other developing countries and even if they do they are completely unaffordable. In this talk I would tell the story of development and dissemination of devices and technologies like SmartCane\, OnBoard and Tactile Diagrams. These started in the ASSISTECH laboratory as inter-disciplinary projects and are today slowly finding their way to the users. \nBiography: \nM Balakrishnan has a B.Tech.(EEE) from BITS Pilani and PhD(EE) from IIT Delhi. He has been\ninvolved in teaching and research in EDA\, VLSI and Embedded systems for more than three decades. He has published over 120 papers in leading journals and conferences\, supervised 13 PhD students and over 180 B.Tech. and M.Tech. student projects. He has held visiting positions in Canada\, US and Germany. He has founded the ASSISTECH laboratory at IIT Delhi which is engaged in finding affordable technology based solutions for education and mobility of visually impaired. He is a recipient of two national awards for his work in the disability space. He has been HoD(CSE)\, Dean(Post Graduate Studies & Research)\, Deputy Director(Faculty) and is currently Deputy Director(Strategy & Planning) at IIT Delhi. URL:https://www.cecs.uci.edu/event/assistech-assistive-technology-for-the-visually-impaired/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20180507T150000 DTEND;TZID=America/Los_Angeles:20180507T160000 DTSTAMP:20231011T190730Z CREATED:20231011T190725Z LAST-MODIFIED:20231011T190730Z UID:14518-1525705200-1525708800@www.cecs.uci.edu SUMMARY:"Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks" DESCRIPTION:Title: “Protocol-fuzzing mobile networks with open-source tools to enhance the security of LTE and 5G mobile networks”\nSpeaker: Roger Piqueras Jover\, Security Researcher at Bloomberg LP \nDate and Time: Tuesday\, May 15 at 10:00 a.m. \nLocation: Donald Bren Hall 3011 \nAbstract:  \nThe Long Term Evolution (LTE) is the latest mobile communications standard being deployed globally to provide connectivity to billions of mobile devices\, from personal cell-phones to all types of critical systems\, such as self-driving cars\, medical appliances and industrial IoT sensors. As such\, the security of this communication standard is of paramount importance. However\, there is concerning inherent protocol security threats in LTE due to the large amount of unauthenticated and unprotected messages exchanged between a base station and a mobile device prior to the authentication security handshake. \nOpen source implementations of the LTE standards rapidly matured within the last couple of years. This\, in combination with sophisticated yet low cost software radio hardware\, fueled a new wave of security research that identified numerous protocol security issues in LTE that could allow an adversary to deny the service of mobile endpoints and track the location of users. This talk will summarize an ongoing effort on protocol-fuzzing LTE mobile networks using open-software tools. The protocol exploits against mobile endpoints that were discovered two years ago will be discussed as an introduction to the new systematic approach to protocol-fuzz LTE networks\, introducing as well a series of new potential exploits in the uplink\, against the network infrastructure and mobile devices outside of the radio range of the adversary. \nFinally\, these LTE protocol exploits are analyzed in the context of the recently (December 2017) published first release of the 3GPP 5G specifications (3GPP Rel. 15) for the 5G Radio Access Network (5G New Radio) and Core Network (5G System). Unfortunately\, not only most protocol-aware radio jamming issues and LTE protocol exploits are still a potential threat\, but there is a large number of new pre-authentication messages and new fields to already existing messages that could open the doors to further 5G-specific exploits. \nBiography: \nRoger Piqueras Jover is a Wireless Security Research Scientist and Security Architect at the CTO Security Architecture team of Bloomberg LP\, where he leads projects on mobile/wireless security and is actively involved in hardware security\, network security\, machine learning and anomaly/fraud detection. Previous to Bloomberg\, he spent 5 years at the AT&T Security Research Center (AT&T SRC)\, where he led the research area on wireless and LTE mobile network security and received numerous awards for his work. \nRoger holds 17 issued patents on mobile and wireless security\, has co-authored manuscripts in numerous top communications and security conferences and is the Technical Co-Chair for the ongoing IEEE 5G Summit series. \nRoger holds a Dipl. Ing. from Politechnical University of Catalunya (Barcelona\, Spain)\, a Master’s in Electrical and Computer Engineering from University of California Irvine and a Master’s/MPhil and EBD (Everything But Dissertation) in Electrical Engineering from Columbia University. \nFor a much more detailed biography\, details on his wireless security work on LTE\, 5G\, LoRaWAN and other technologies\, one can refer to http://rogerpiquerasjover.net/ URL:https://www.cecs.uci.edu/event/protocol-fuzzing-mobile-networks-with-open-source-tools-to-enhance-the-security-of-lte-and-5g-mobile-networks/ LOCATION:CA CATEGORIES:Seminars at CECS END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20180516T150000 DTEND;TZID=America/Los_Angeles:20180516T160000 DTSTAMP:20231011T190732Z CREATED:20231011T190732Z LAST-MODIFIED:20231011T190732Z UID:14524-1526482800-1526486400@www.cecs.uci.edu SUMMARY:“Self-aware Computing: Combining Learning and Control to Manage Complex\, Dynamic Systems” DESCRIPTION: