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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040206T150000
DTEND;TZID=America/Los_Angeles:20040206T160000
DTSTAMP:20231011T183337Z
CREATED:20231011T183337Z
LAST-MODIFIED:20231011T183337Z
UID:14301-1076079600-1076083200@www.cecs.uci.edu
SUMMARY:Embedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond
DESCRIPTION:Lecture Slides \nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\nSpeakers\n\n\nJonathan R. Haigh and Michael W. Wilkerson\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Veidenbaum\nalexv@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, February 6\, 2004\nRefreshments at 10:30am\, Seminar begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOptimizing power consumption is a primary goal in the design of embedded microprocessors even as the push for higher performance continues.  Managing the microprocessor’s power dissipation while still striving to push the design into GHz speeds provides a significant challenge.  As designs move to 90 nm and beyond\, device scaling has reduced oxide thicknesses and V T to the point where standby leakage power is on the same order of magnitude as active power.  Today’s successful designs need to aggressively manage both active and standby currents.  A collection of methods to control both active and leakage power in Cache and Translation Lookaside Buffer (TLB) circuits\, while minimizing the impact to performance\, will be discussed.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nJonathan R. Haigh: \nJon is the lead L1 cache designer for the current generation of XScale products.  He began his EE career at GE in 1996 followed by the former Digital Semiconductor in 1998.  He joined Intel Corporation in 2000 and has been working on the XScale cache circuit design team since joining the company.  He received his B.S. degree in Electrical Engineering concentrating in VLSI design from the University of Cincinnati .Michael W. Wilkerson: \nMike received the B.S. and M.S. degrees in electrical engineering from the University of Florida in 1991 and 1997.  He was in the U.S. Navy from 1983 to 1996 and joined Intel Corporation in 1998.  He has worked in logic verification and VLSI circuit design for Itanium and XScale microprocessors while at Intel.  He most recently completed the physical design of the data path memory management unit\, which includes a TLB structure\, for a new XScale core.\n\n\n\nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\n\n\n\nclick on the thumbnails to view the full-sized images\n\n\n\n\n\n\nThe lecture was held at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh and Mike Wilkerson are members of the team designing the Intel XScale embedded processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon and Mike chatting with CECS students before delivering their talk. Professor Alex Veidenbaum\, left background\, hosted the event.  \nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nMike Wilkerson discussing embedded processor design challenges. At 90 nm\, it is important to employ architectural techniques that emphasize power reduction.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh explaining cache memory design strategies for the XScale processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nA lively Q & A session followed the presentation.\nview larger image
URL:https://www.cecs.uci.edu/event/embedded-microprocessor-cache-and-translation-lookaside-buffer-tlb-low-power-circuit-techniques-for-90nm-and-beyond/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040116T150000
DTEND;TZID=America/Los_Angeles:20040116T160000
DTSTAMP:20231011T183337Z
CREATED:20231011T183337Z
LAST-MODIFIED:20231011T183337Z
UID:14302-1074265200-1074268800@www.cecs.uci.edu
SUMMARY:System-Level Design: Only the Radical Will Survive
DESCRIPTION:  \nLecture Slides \nSystem-Level Design: Only the Radical Will Survive\n\n\n\n\nSpeaker\n\n\nDr. Reinaldo Bergamaschi\nIBM T. J. Watson Research Center\, Yorktown Heights \, NY\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, January 16\, 2004\nRefreshments served at 10:00 a.m.\, lecture begins at 10:30 a.m.\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe term “system-level design” has been defined\, used and abused countless times by designers\, cad developers and most of all\, tools sales people. By now we all know what is supposed to be\, and it ‘ain’t pretty` (despite the claims by cad vendors). In this talk\, I will argue that for the past 5 years (at least) we have tried to develop system-level tools by fattening the already beaten up ASIC design methodology\, by exaggerating the advantages of high-level languages\, by overblowing the benefits of software-related methodologies for designing hardware\, among other very incremental approaches. The design methodologies and tools currently used for system-on-chip design are an evolution of ASIC and board-level design tools. Such an incremental approach has been ineffective in closing the productivity design gap. I will analyze the current push to use high-level languages and software approaches for hardware design\, and try to convince the audience that such attempts\, while in the right direction\, are far from sufficient. I will argue that radical new approaches for system design are needed if we want to be able to design new products in shorter time-to-market. I will discuss some of the approaches we are developing at IBM Research and speculate on possible new research avenues.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nReinaldo Bergamaschi graduated in Electronics Engineering from the Aeronautics Institute of Technology\, Sao Jose dos Campos\, Brazil \, in 1982\, and in 1984 he received the M.E.E degree from the Philips International Institute\, Eindhoven\, The Netherlands. In 1989 he obtained the Ph.D. degree in Electronics and Computer Science from the University of Southampton\, Southampton\, England\, and joined the IBM T. J. Watson Research Center\, Yorktown Heights \, USA. He has worked extensively on RTL\, behavioral and system-level design tools and methodologies. He was the main architect of IBM’s high-level synthesis system and he is currently developing system-level modeling and synthesis tools for core-based\, platform-based designs. He has participated in numerous conference committees and given several tutorials and lectures on high-level and system-level design issues and tools.\n\n\n\nSystem-Level Design: Only the Radical Will Survive\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/system-level-design-only-the-radical-will-survive/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031209T150000
DTEND;TZID=America/Los_Angeles:20031209T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14303-1070982000-1070985600@www.cecs.uci.edu
SUMMARY:The Fundamentals: Moore's Law\, Microarchitecture\, and the Microprocessor of the Year 2014
DESCRIPTION:The Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\nSpeaker\n\n\nProfessor Yale Patt\nThe University of Texas at Austin\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Jean-Luc Gaudiot\ngaudiot@uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 9\, 2003\nRefreshments at 1:15pm\, Lecture begins at 1:30pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nMoore’s Law promises very soon more than a billion transistors on a chip processing at more than 10 GHz. But\, what else does Moore ‘s Law tell us about the future of high performance microprocessors. Is there anything left to do in the microarchitecture to make use of all this capability\, or should we fold our tents and go home? Many claim we have reached the end of our rope. In this talk\, I hope to spend a little time discussing the rationale of the naysayer and then move on to what we can do. Per usual\, I plan to tie my comments to the fundamentals\, because I believe it is always the fundamentals that provide the insights to new knowledge. Finally\, I will discuss what I think we will see in the microprocessor of the year 2014\, including the block-structured ISA\, stronger use of SSMT\, greater use of microcode\, dedicated infrequently used functional units\, and most importantly\, a stronger coupling with the compiler\, language\, and algorithm technologies. If time permits\, I will discuss some things I do not think we will see on the chip\, like qbits and machines that think.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nYale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell\, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He directs the Ph.D. research of 12 graduate students in computer architecture and teaches both the freshman introduction to computing and his graduate course in Microarchitecture. He has received the highest honors in his field for his research and teaching\, including the 1996 IEEE/ACM Eckert-Mauchly Award for his contributions to high performance microprocessor design and the 2000 ACM Karl V. Karlstrom Outstanding Educator Award for his contributions to education. He has had\, for the past 35 years\, an active consulting practice\, including long term associations with Intel\, Digital\, NCR\, Motorola\, and others. His freshman textbook “Introduction to Computing Systems: from bits and gates to C and beyond\,” has been adopted by more than 100 universities world-wide. It is co-authored with Professor Sanjay Patel of the University of Illinois . McGraw-Hill just released the second edition this fall. Yale Patt is a Fellow of both the IEEE and the ACM.\n\n\n\nThe Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\n\n\n\nMcDonnell Douglas Auditorium at Engineering Gateway.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nLecture began at 1:30pm at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nProfessor Yale Patt talking about microarchitecture.\nview larger image
URL:https://www.cecs.uci.edu/event/the-fundamentals-moores-law-microarchitecture-and-the-microprocessor-of-the-year-2014/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030722T150000
DTEND;TZID=America/Los_Angeles:20030722T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14304-1058886000-1058889600@www.cecs.uci.edu
SUMMARY:Smart Cameras as High Performance Embedded Systems
DESCRIPTION:by Professor Wayne Wolf\, Princeton University\,McDonnell Douglas Auditorium\, University of California\, Irvine\, CA\nDistinguished Lecture\, July 22\, 2003\nAbstract :: Lecture Slides :: Pictures 
URL:https://www.cecs.uci.edu/event/smart-cameras-as-high-performance-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030513T150000
DTEND;TZID=America/Los_Angeles:20030513T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14305-1052838000-1052841600@www.cecs.uci.edu
SUMMARY:Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems
DESCRIPTION:by Professor Kang Shin\, University of Michigan\,McDonnell Douglas Auditorium\, University of California\, Irvine\, CA\nDistinguished Lecture\, May 13\, 2003\nAbstract :: Lecture Slides :: Pictures
URL:https://www.cecs.uci.edu/event/real-time-dynamic-voltage-scaling-for-low-power-embedded-operating-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030509T100000
DTEND;TZID=America/Los_Angeles:20030509T120000
DTSTAMP:20231011T192949Z
CREATED:20231011T180419Z
LAST-MODIFIED:20231011T192949Z
UID:14228-1052474400-1052481600@www.cecs.uci.edu
SUMMARY:Statistical Tools and Methodologies for Delay Test and Timing Validation
DESCRIPTION:by Li-C. Wang\, UCSB\, ECE DepartmentMay 9\, 2003
URL:https://www.cecs.uci.edu/event/statistical-tools-and-methodologies-for-delay-test-and-timing-validation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020919T010000
DTEND;TZID=America/Los_Angeles:20020919T120000
DTSTAMP:20231011T192748Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T192748Z
UID:14219-1032397200-1032436800@www.cecs.uci.edu
SUMMARY:Reconfigurable Systems
DESCRIPTION:by Majid Sarrafzadeh\, UCLA\, Computer Science DepartmentSeptember 19\, 2002
URL:https://www.cecs.uci.edu/event/reconfigurable-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020823T020000
DTEND;TZID=America/Los_Angeles:20020823T120000
DTSTAMP:20231011T193148Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T193148Z
UID:14220-1030068000-1030104000@www.cecs.uci.edu
SUMMARY:Worst-Case Performance Analysis of Parallel Communicating Processors
DESCRIPTION:by Wolfgang Rosensteil\, University of Tuebingen\, GermanyAugust 23\, 2002
URL:https://www.cecs.uci.edu/event/worst-case-performance-analysis-of-parallel-communicating-processors/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020806T030000
DTEND;TZID=America/Los_Angeles:20020806T120000
DTSTAMP:20231011T192457Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T192457Z
UID:14221-1028602800-1028635200@www.cecs.uci.edu
SUMMARY:Low-Power Liquid Crystal Display Systems
DESCRIPTION:by Naehyuck Chang\, Seoul National UniversityAugust 6\, 2002
URL:https://www.cecs.uci.edu/event/low-power-liquid-crystal-display-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020802T050000
DTEND;TZID=America/Los_Angeles:20020802T120000
DTSTAMP:20231011T192041Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192041Z
UID:14223-1028264400-1028289600@www.cecs.uci.edu
SUMMARY:Design of a Hardware/Software RTOS for SoC
DESCRIPTION:by Vincent John Mooney III\, Gerogia Institute of TechnologyAugust 2\, 2002
URL:https://www.cecs.uci.edu/event/design-of-a-hardware-software-rtos-for-soc/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020802T040000
DTEND;TZID=America/Los_Angeles:20020802T120000
DTSTAMP:20231011T192054Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T192054Z
UID:14222-1028260800-1028289600@www.cecs.uci.edu
SUMMARY:Embedded Systems Research at IIT Delhi
DESCRIPTION:by M. Balahrishnan\, IIT Delhi\, IndiaAugust 2\, 2002
URL:https://www.cecs.uci.edu/event/embedded-systems-research-at-iit-delhi/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020724T060000
DTEND;TZID=America/Los_Angeles:20020724T120000
DTSTAMP:20231011T192654Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192654Z
UID:14224-1027490400-1027512000@www.cecs.uci.edu
SUMMARY:Polychrony for System Design
DESCRIPTION:by Dr. Jean-Pierre Talpin\, INRIA project ESPRESSO\, FranceJuly 24\, 2002
URL:https://www.cecs.uci.edu/event/polychrony-for-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020325T070000
DTEND;TZID=America/Los_Angeles:20020325T120000
DTSTAMP:20231011T192748Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192748Z
UID:14225-1017039600-1017057600@www.cecs.uci.edu
SUMMARY:Power Estimation and Optimization on Architectural Level
DESCRIPTION:by Achim Rettberg\, C-Lab\, Paderborn\, GermanyMarch 25\, 2002
URL:https://www.cecs.uci.edu/event/power-estimation-and-optimization-on-architectural-level/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020315T080000
DTEND;TZID=America/Los_Angeles:20020315T120000
DTSTAMP:20231011T192041Z
CREATED:20231011T180347Z
LAST-MODIFIED:20231011T192041Z
UID:14226-1016179200-1016193600@www.cecs.uci.edu
SUMMARY:Compiling with Code-Size Constraints
DESCRIPTION:by Jens Palsberg\, Purdue UniversityMarch 15\, 2002
URL:https://www.cecs.uci.edu/event/compiling-with-code-size-constraints/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20020221T090000
DTEND;TZID=America/Los_Angeles:20020221T120000
DTSTAMP:20231011T192254Z
CREATED:20231011T180348Z
LAST-MODIFIED:20231011T192254Z
UID:14227-1014282000-1014292800@www.cecs.uci.edu
SUMMARY:Heterogeneous Actor-oriented Modeling in Ptolemy II
DESCRIPTION:by Steven Neuendorffer\, University of California\, BerkeleyFebruary 21\, 2002
URL:https://www.cecs.uci.edu/event/heterogeneous-actor-oriented-modeling-in-ptolemy-ii/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010831T050000
DTEND;TZID=America/Los_Angeles:20010831T120000
DTSTAMP:20231011T192054Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192054Z
UID:14213-999234000-999259200@www.cecs.uci.edu
SUMMARY:Evaluation of VLSI Architectures
DESCRIPTION:by Dr. Walter Stechele\, Director of Research\, Institute for Integrated Circuits\,Munich University of Technology\, Munich\, Germany\nAugust 31\, 2001
URL:https://www.cecs.uci.edu/event/evaluation-of-vlsi-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010808T040000
DTEND;TZID=America/Los_Angeles:20010808T120000
DTSTAMP:20231011T192457Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192457Z
UID:14214-997243200-997272000@www.cecs.uci.edu
SUMMARY:Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis
DESCRIPTION:by Prof. Jihong Kim\, School of Computer Science & Engineering\,Seoul National University\, Korea\nAugust 8\, 2001
URL:https://www.cecs.uci.edu/event/low-energy-intra-task-voltage-scheduling-using-static-timing-analysis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010808T030000
DTEND;TZID=America/Los_Angeles:20010808T120000
DTSTAMP:20231011T192053Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192053Z
UID:14215-997239600-997272000@www.cecs.uci.edu
SUMMARY:Embedded System Design and Energy Optimization
DESCRIPTION:by Prof. Naehyuck Chang\, School of Computer Science & Engineering\,Seoul National University\, Korea\nAugust 8\, 2001
URL:https://www.cecs.uci.edu/event/embedded-system-design-and-energy-optimization/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010802T020000
DTEND;TZID=America/Los_Angeles:20010802T120000
DTSTAMP:20231011T192054Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192054Z
UID:14216-996717600-996753600@www.cecs.uci.edu
SUMMARY:FLYSIG - A Fast Re-Configurable Asynchronous Architecture  for Multimedia Applications
DESCRIPTION:by Achim Rettberg\, Cooperative Computing & Communication Laboratory (C-LAB)\, Paderborn\, GermanyAugust 2\, 2001
URL:https://www.cecs.uci.edu/event/flysig-a-fast-re-configurable-asynchronous-architecture-for-multimedia-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20010630T010000
DTEND;TZID=America/Los_Angeles:20010630T120000
DTSTAMP:20231011T192654Z
CREATED:20231011T180231Z
LAST-MODIFIED:20231011T192654Z
UID:14217-993862800-993902400@www.cecs.uci.edu
SUMMARY:ORINOCO-Low Power Algorithms\, Low Power Architectures
DESCRIPTION:by Prof. Wolfgang Nebel\, Computer Science Department\,Oldenburg University\, Germany\nJuly 30\, 2001
URL:https://www.cecs.uci.edu/event/orinoco-low-power-algorithms-low-power-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20261113T215740
DTEND;TZID=America/Los_Angeles:20010630T120000
DTSTAMP:20231011T192653Z
CREATED:20231011T180332Z
LAST-MODIFIED:20231011T192653Z
UID:14218-0-993902400@www.cecs.uci.edu
SUMMARY:OCAPI-xl: Uniform Design Refinement of Hardware/Software Platforms
DESCRIPTION:by Patrick Schaumont\, Digital Broadband Terminal Group IMEC\, BelgiumJuly 30\, 2001
URL:https://www.cecs.uci.edu/event/ocapi-xl-uniform-design-refinement-of-hardware-software-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR