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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T193148Z
UID:14238-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Transparent Acceleration of Data Dependent Instructions for General Purpose Processors
DESCRIPTION:Prof. Luigi Carro\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract 
URL:https://www.cecs.uci.edu/event/transparent-acceleration-of-data-dependent-instructions-for-general-purpose-processors/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T192031Z
UID:14239-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Adaptive Mechanisms for Meeting Energy and Real-Time Constraints in MPSoC Platforms
DESCRIPTION:Prof. Flavio R. Wagner\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/adaptive-mechanisms-for-meeting-energy-and-real-time-constraints-in-mpsoc-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070426T150000
DTEND;TZID=America/Los_Angeles:20070426T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192254Z
UID:14240-1177599600-1177603200@www.cecs.uci.edu
SUMMARY:High Level Systems Validation Using Hierarchical Message Sequence Charts
DESCRIPTION:Dr. Praveen Murthy\, Fujitsu Labs of AmericaCalit2 Auditorium\, University of California\, Irvine\nApril 26\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/high-level-systems-validation-using-hierarchical-message-sequence-charts/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070325T150000
DTEND;TZID=America/Los_Angeles:20070325T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14287-1174834800-1174838400@www.cecs.uci.edu
SUMMARY:Operating system kernel as a building block for scalable and fast network topology emulation
DESCRIPTION:Marko Zec\, University of Zagreb\, Croatia5251 California Ave.\, Suite 210 ( CECS Research Park Office)\, Unversity of California\, Irvine\nLecture\, May 25\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/operating-system-kernel-as-a-building-block-for-scalable-and-fast-network-topology-emulation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070316T150000
DTEND;TZID=America/Los_Angeles:20070316T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14241-1174057200-1174060800@www.cecs.uci.edu
SUMMARY:Embedded Control Software Engineering Methods and Tools Research at ISL\, Bangalore
DESCRIPTION:Dr. S. Ramesh\, Technical Fellow\, India Science Lab\, GM R&D Labs\, Bangalore\, IndiaCalit2 Auditorium\, University of California\, Irvine\nMarch 16\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/embedded-control-software-engineering-methods-and-tools-research-at-isl-bangalore/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070309T150000
DTEND;TZID=America/Los_Angeles:20070309T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14242-1173452400-1173456000@www.cecs.uci.edu
SUMMARY:Arithmetic Optimizations for System Design
DESCRIPTION:Dr. Farzan Fallah\, Fujitsu LaboratoriesCalit2 Auditorium\, University of Califonia\, Irvine\, CA\nLecture\, March 09\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/arithmetic-optimizations-for-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070222T150000
DTEND;TZID=America/Los_Angeles:20070222T160000
DTSTAMP:20231011T183308Z
CREATED:20231011T183308Z
LAST-MODIFIED:20231011T183308Z
UID:14288-1172156400-1172160000@www.cecs.uci.edu
SUMMARY:Automatic Parallelization with Hybrid Analysis
DESCRIPTION:Dr. Lawrence Rauchwerger\,Texas A&M UniversityCalit2\, Room 3008\, University of Califonia\, Irvine\, CA\nLecture\, February 22\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/automatic-parallelization-with-hybrid-analysis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070220T150000
DTEND;TZID=America/Los_Angeles:20070220T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14289-1171983600-1171987200@www.cecs.uci.edu
SUMMARY:Research Challenges in High Performance VLSI/SoC Circuits and Systems
DESCRIPTION:Professor. Eby G. Friedman\, University of RochesterMcDonnell Douglas Auditorium\, University of Califonia\, Irvine\, CA\nDistinguished Lecture\, February 20\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/research-challenges-in-high-performance-vlsi-soc-circuits-and-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070119T150000
DTEND;TZID=America/Los_Angeles:20070119T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14290-1169218800-1169222400@www.cecs.uci.edu
SUMMARY:From Service Composition to Gadget Composition: Enabling Process-Oriented Web
DESCRIPTION:Dr. Sinisa Srbljic\, University of Zagreb\, CroatiaMcDonnell Douglas Auditorium\, University of Califonia\, Irvine\, CA\nDistinguished Lecture\, January 19\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/from-service-composition-to-gadget-composition-enabling-process-oriented-web/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060714T150000
DTEND;TZID=America/Los_Angeles:20060714T160000
DTSTAMP:20231011T183309Z
CREATED:20231011T183309Z
LAST-MODIFIED:20231011T183309Z
UID:14291-1152889200-1152892800@www.cecs.uci.edu
SUMMARY:Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform
DESCRIPTION:Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform\n\n\n\n\nSpeaker\n\n\nDr. Youn-Long Steve Lin\nDepartment of Computer Science\nNational Tsing-Hua University\, Taiwan\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDouglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 14 \, 2006\nRefreshments at 10:30 am\, followed by Lecture at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHere in Tsing Hua\, we have developed a pure hardwired AMBA-compliant accelerator for H.264/AVC main profile. Integrated into the FPGA module of a multimedia SOC platform\, it can real-time decode CIF video running at just 10MHz. I will give a brief introduction to H.264/AVC\, the next generation video coding standard. Then I will describe the SOC platform and system design flow jointly developed by Tsing Hua and Global UniChip Corp. Finally\, I will present several architectural innovations in the decoder core that lead to high performance.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nYoun-Long Steve Lin received his B.S. degree in Electronics Engineering from National Taiwan University of Science and Technology\, Taipei\, Taiwan in 1982\, and Ph.D degree in Computer Science from the University of Illinois\, Urbana-Champaign\, IL.\, in 1987. Upon his graduation\, he joined National Tsing Hua University\, Hsin-Chu\, Taiwan\, where he established the THEDA Group (Tsing Hua EDA)\, served as Director of the University Computer and Communication Center\, Chairman of the Department of Computer Science\, Secretariat General of the University and Director of the University Library. Youn-Long Steve Lin is currently a Professor of Computer Science at the National Tsing Hua University\, Hsin-Chu\, Taiwan. He is also an Adjunct Professor at Peking University\, Beijing\, China. He is elected the president of Taiwan Integrated Circuit Design Society (TICD) for 2005-2006. \nProfessor Lin’s primary research interest is in computer-aided design (CAD) of very large-scale integrated circuits (VLSI) with emphasis on physical design automation and high-level synthesis. He co-authored the book “High Level Synthesis—Introduction to Chip and System Design.” He also spends great effort in promoting the VLSI design and CAD education in Taiwan. His current research focus is on design technology for System-on-a-Chips (SOC) employing reusable silicon intellectual properties (IPs). He is a senior member of the IEEE\, the IEEE Computer Society\, the IEEE Circuit and System Society\, the IEEE Solid State Circuit Society\, and the Association for Computer Machinery. He is a board member of the Taiwan IC Design Society. He is a nation-certified electrical engineer.
URL:https://www.cecs.uci.edu/event/development-of-an-h-264-avc-decoder-prototype-on-a-multimedia-soc-platform/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060501T150000
DTEND;TZID=America/Los_Angeles:20060501T160000
DTSTAMP:20231011T192054Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192054Z
UID:14235-1146495600-1146499200@www.cecs.uci.edu
SUMMARY:Emerging Challenges in Assuring Functional Correctness of VLSI Devices  for Mobile Applications
DESCRIPTION:Scott Runner\, Qualcomm CDMA TechnologiesMcDonnel Douglas Auditorium\, University of California\, Irvine\nMay 1\, 2006\nAbstract
URL:https://www.cecs.uci.edu/event/emerging-challenges-in-assuring-functional-correctness-of-vlsi-devices-for-mobile-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20060216T150000
DTEND;TZID=America/Los_Angeles:20060216T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14294-1140102000-1140105600@www.cecs.uci.edu
SUMMARY:Kilo-Instruction Processors: Overcoming the Memory Wall
DESCRIPTION:Kilo-Instruction Processors: Overcoming the Memory Wall\n\n\n\n\nSpeaker\n\n\nProfessor Mateo Valero\nComputer Architecture Dep. of the Polytechnical University of Catalunia\nCatalunia\, Spain\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nComputer Science 432\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFebruary 16\, 2006\nRefreshments at 10:30am\, followed by Lecture\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nToday’s systems have a very large and growing gap between processor and (DRAM) memory speeds\, which results in very long memory latency and loss of performance. Many different techniques have been proposed to address this problem: cache memories\, prefetching and other latency hiding techniques\, and multithreading\, to name a few. We proposed a different approach to solving this problem: a new type of out-of-order superscalar processor called the Kilo-Instruction Processor. Our design can have thousands of in-flight instructions using a scalable multi-check pointing mechanism. This allows memory access to be overlapped with the execution of a large number of other instructions and significantly improves performance. Kilo-Instruction Processors also offer advantages in multiprocessor systems\, where the average memory latency is even longer. They enable implementation of other very desirable features via their check-pointing mechanism. For example\, we can implement a multiprocessor transactional memory in hardware using checkpoints\, which enables an effective implementation of sequential consistency. This talk will describe the main ideas of our work on Kilo-instruction processors\, efficient\nimplementation options for this type of processors\, and their use in the design of multiprocessor systems.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nMateo Valero obtained his PhD at UPC in 1980. He is a Professor in the Computer Architecture Department of the Polytechnical University of Catalunia (UPC) in Spain and the director of the Barcelona Supercomputing Center\, the National Supercomputing Center of Spain. His research interests are in the area of high performance computer architecture. He has published over 400 papers in this field. Dr. Valero is a Fellow of the IEEE\, an Intel Distinguished Research Fellow and a Fellow of the ACM. He is a Correspondent Academic Member of the Spanish Royal Academy of Sciences. He is a winner of the “King Jaime I” award by the Generalitat Valenciana and the Spanish national award “Julio Rey Pastor” for his research in IT technologies. He is very proud that his home town of Alfamen named its Public College after him.
URL:https://www.cecs.uci.edu/event/kilo-instruction-processors-overcoming-the-memory-wall/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20051115T150000
DTEND;TZID=America/Los_Angeles:20051115T160000
DTSTAMP:20231011T192654Z
CREATED:20231011T180420Z
LAST-MODIFIED:20231011T192654Z
UID:14232-1132066800-1132070400@www.cecs.uci.edu
SUMMARY:PIE: Programmable Internet Environment
DESCRIPTION:Abstract \nPIE: Programmable Internet Environment\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/pie-programmable-internet-environment/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050617T150000
DTEND;TZID=America/Los_Angeles:20050617T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180434Z
LAST-MODIFIED:20231011T192041Z
UID:14233-1119020400-1119024000@www.cecs.uci.edu
SUMMARY:Cutpoints for Formal Equivalence Verification of Embedded Software
DESCRIPTION:Cutpoints for Formal Equivalence Verification of Embedded Software\n\n\n\n\nSpeaker\n\n\nDr. Alan Hu\nDepartment of Computer Science\nUniversity of British Colombia\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 432\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 17 \, 2005\nTalk begins at 9:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nLike hardware\, embedded software faces stringent design constraints\, undergoes extremely aggressive optimization\, and therefore has a similar need for verifying the functional equivalence of two versions of a design\, e.g.\, before and after an optimization. The concept of cutpoints was a breakthrough in the formal equivalence verification of combinational circuits and is the key enabling technology behind its successful commercialization. We introduce an analogous idea for formally verifying the equivalence of structurally similar\, “combinational” software\, i.e.\, software routines that compute a result and return/terminate\, rather than executing indefinitely. We have implemented a proof-of-concept cutpoint approach in our prototype verification tool for the TI C6x family of VLIW DSPs\, and our experiments show large improvements in runtime and memory usage.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nAlan Hu received his BS and PhD degrees from Stanford University . He is an associate professor and associate head of the Department of Computer Science at the University of British Columbia . For the past15 years\, his main research focus has been automated\, practical techniques for formal verification. He has served on the program committees of most major CAD and formal verification conferences\, and chaired or co-chaired CAV (1998)\, HLDVT (2003)\, and FMCAD (2004). He was also a Technical Working Group Key Contributor on the 2001 International Technology Roadmap for Semiconductors.
URL:https://www.cecs.uci.edu/event/cutpoints-for-formal-equivalence-verification-of-embedded-software/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050609T150000
DTEND;TZID=America/Los_Angeles:20050609T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14295-1118329200-1118332800@www.cecs.uci.edu
SUMMARY:VLSI Design Methodologies Considering Fabrication Variability
DESCRIPTION:VLSI Design Methodologies Considering Fabrication Variability\n\n\n\n\nSpeaker\n\n\nProfessor Shrivastava \nDepartment of Electrical and Computer Engineering\nUniversity of Maryland\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Elaheh Bozorgzadeh\neli@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 127\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 9\, 2005\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn the past few years\, it has become clear that fabrication variability is one of the most important challenge that needs to be addressed for keeping the semiconductor industry profitable. Fabrication variability imposes an underlying uncertainty on the design process of VLSI chips making several parameters random. Therefore\, the old way of doing design needs to be overhauled for considering this randomness. This implies that VLSI CAD needs to incorporate probabilistic models for capturing uncertainty and stochastic optimization for controlling the design decision variables. Several challenges need to be addressed before this is made possible…\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nAnkur Srivastava received the B.S. degree from the Indian Institute of Technology\, Delhi\, the M.S. degree from Northwestern University\, Evanston\, IL\, and the Ph.D. degree from the University of California Los Angeles (UCLA) in 1998\, 2000\, and 2002. Since fall 2002 he has been an Assistant Professor with the University of Maryland\, College Park. His research interests include all aspects of design automation including logic and high-level synthesis\, low-power issues and predictability\, and low-power issues pertaining to sensor networks. Dr. Srivastava received the outstanding Ph.D. Award from the Computer Science Department of UCLA in 2002. He is a member of ACM and IEEE.
URL:https://www.cecs.uci.edu/event/vlsi-design-methodologies-considering-fabrication-variability/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050513T150000
DTEND;TZID=America/Los_Angeles:20050513T160000
DTSTAMP:20231011T192748Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192748Z
UID:14234-1115996400-1116000000@www.cecs.uci.edu
SUMMARY:Practical Considerations for Power-Aware Real-Time Scheduling
DESCRIPTION:Continuous Compilation for Aggressive and Adaptive\nCode Transformation\n\n\n\n\nSpeaker\n\n\nDr. Bruce Childers\nDepartment of Computer Science\nUniversity of Pittsburgh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 127\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 13 \, 2005\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOver the past several decades\, the compiler research community has developed a number of sophisticated and powerful algorithms for a variety of code improvements. Although there are still promising directions for particular aspects of code optimization\, research on optimizations is nearing the point of diminishing returns and other approaches are needed to achieve further performance improvements. Our research aims to address this challenge by investigating and developing an innovative framework and system for continuously and adaptively applying code improvements. Our system\, the Continuous Compiler ( CoCo )\, determines “optimization plans” at compile-time that describe the best way in which to apply both static and dynamic code transformations. The plans consider program and machine context\, interaction among optimizations\, and performance profit. Through such planning\, CoCo can tailor and adapt its decisions to more synergistically apply a whole suite of code transformations.  \nThis talk will describe the Continuous Compilation approach and present initial results. These results include novel analytic models that can accurately predict the performance benefit (profit) of applying an optimization without actually doing it or running the resulting program code. Using the analytic models\, we have developed several planners that can guide a static optimizer. Initial results are very encouraging and show that optimizations can be effectively directed by planning. The talk will conclude with a brief discussion of CoCo ‘s run-time system\, including its dynamic code translator\, instrumentation optimizer\, and source-level debugger for dynamically translated code.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nBruce Childers is an Assistant Professor in the Department of Computer Science at the University of Pittsburgh. Dr. Childers received a BS degree (Computer Science\, 1991) from the College of William and Mary\, and a PhD degree (Computer Science\, 2000) from the University of Virginia. His research interests are compilers and software development tools\, computer architecture\, and embedded systems. Current projects include continuous compilation to synergistically apply both static and dynamic code optimizations\, debugging for dynamically translated code\, power-aware real-time systems\, and demand-driven software testing.
URL:https://www.cecs.uci.edu/event/practical-considerations-for-power-aware-real-time-scheduling-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050509T150000
DTEND;TZID=America/Los_Angeles:20050509T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14296-1115650800-1115654400@www.cecs.uci.edu
SUMMARY:Customizable Embedded Processor Architectures
DESCRIPTION:Customizable Embedded Processor Architectures\n\n\n\n\nSpeaker\n\n\nProfessor Orailoglu \nDepartment of Computer Science and Engineering\nUniversity of California\, San Diego\, CA\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Jean-Luc Gaudiot\ngaudiot@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 14\, 2005\nRefreshments at 3:30 pm\, Lecture begins at 4:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRecent advances in VLSI technology are resulting in ever more complex system-on-a-chip designs. Reduced time-to-market and low product cost requirements have been placing increased pressure upon designers to shift as much as possible of the system functionality onto a set of available microprocessor cores so as to reduce the hardware cost of the system and achieve faster time-to-market. Yet one of the fundamental difficulties in implementing larger parts of SOC functionality in software is the stringent timing constraints of the critical modules; methods need to be developed for matching such stringent constraints if embedded processor cores are to be widely used. Low-cost\, application-specific microarchitecture customizations promise to be an efficient solution to this problem. The basic advantage of microprocessor cores versus ASICs is the intrinsic reconfiguration capability of the processor by means of software. In order to preserve this fundamental advantage\, application-specific features added to the microarchitecture need to be implemented as reprogrammable hardware. Post-manufacturing customization capability can thus provide seamless migration to new applications possibly due to late specification changes or market requirements\, while delivering superior levels of performance. In this talk\, we outline the incorporation of application specific properties into the processor microarchitecture\, thus increasing performance and reducing power consumption. The fundamental approach is the identification of application properties during compile time and their dynamic exploitation during program execution by the processor. The basic characteristic of these properties is that their existence can be statically identifiable by the compiler\, and that they can lead to significant improvements in performance when exploiting their behavior dynamically. Such properties may consist of the control structure of the algorithm\, the run-time data values and the code manipulating some data structures; for example\, an array access\, its stride\, or its control structure. Microarchitectural features that can be enhanced with such application-specific information include the branch predictor\, the cache subsystem\, and the processor communication infrastructure; techniques aimed at all three are outlined in this talk.\ndownload pdf\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nAlex Orailoglu received his BS Degree cum laude from Harvard University in Applied Mathematics and his M.S. and Ph.D. degrees in Computer Science from the University of Illinois \, Urbana-Champaign. Alex Orailoglu is currently a Professor of Computer Science and Engineering at the University of California \, San Diego . His research interests include Embedded Systems and Processors\, digital and analog test\, fault tolerant computing\, Computer-Aided Design\, and nanoelectronics.\n\n\n\nCustomizable Embedded Processor Architectures\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/customizable-embedded-processor-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050414T150000
DTEND;TZID=America/Los_Angeles:20050414T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14297-1113490800-1113494400@www.cecs.uci.edu
SUMMARY:Multiple Objective Behavioural Synthesis
DESCRIPTION:Multiple Objective Behavioural Synthesis\n\n\n\n\nSpeaker\n\n\nProfessor Zwolinski \nSchool of Electronics and Computer Science\nUniversity of Southampton\, UK\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Ian Harris\nharris@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nICS 432\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 14\, 2005\nRefreshments at 10:30am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nFor a number of years\, the Electronic Systems Design Group in the School of Electronics and Computer Science\, University of Southampton has been working on a behavioral synthesis tool – MOODS (Multiple Objective Optimization in control and Data path Synthesis). Unlike many other high-level synthesis tools\, MOODS optimizes designs by a series of small\, localized transforms to the data and control paths. This approach has some significant advantages over other techniques\, most notably that a number of different objectives can be specified\, without knowing the relationship between those objectives. Initially\, optimization was performed in terms of area and critical path delay\, but this has been extended (through a succession of PhD projects) to include power\, testability and reconfigurability. In this talk\, the techniques used and results achieved will be discussed\, together with future research directions.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nDr. Mark Zwolinski is a Reader (Associate Professor) in the School of\nElectronics and Computer Science at the University of Southampton UK. He\ncompleted his BS in Electronic Engineering and PhD in Electronics at\nthe University of Southampton\, too. He was appointed as a lecturer\n(Assistant Professor) in 1990. His PhD was on the topic of electronic\ncircuit simulation\, but he has since developed research interests in\nanalog and mixed-signal test\, high-level synthesis and verification. He\nhas published over 100 refereed conference and journal papers and is the\nauthor of two books.
URL:https://www.cecs.uci.edu/event/multiple-objective-behavioural-synthesis/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20041209T150000
DTEND;TZID=America/Los_Angeles:20041209T160000
DTSTAMP:20231011T183336Z
CREATED:20231011T183336Z
LAST-MODIFIED:20231011T183336Z
UID:14298-1102604400-1102608000@www.cecs.uci.edu
SUMMARY:Technological Challenges to Computer Architecture Innovation
DESCRIPTION:Video Introduction (Windows Media Player) \n  \nTechnological Challenges to Computer Architecture Innovation\n\n\n\n\nSpeaker\n\n\nDr. Faye Briggs\nIntel Corporation\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nAlex Veidenbaum\nalexv@cecs.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 9 \, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nComputer architecture has evolved significantly over the last 30 years. With a major dependence on technology\, we have been able to keep up with Moore’s law. We are beginning to face enormous constraints in technology\, and these create significant challenges for computer architecture advancement. The goal of this talk is to provide an overview of many of the variables and constraints that will challenge traditional computer architecture innovations. The intent is to highlight these challenges with the expectation of triggering more research and potential breadkthroughs to sustain innovation in computer architecture.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\n \nDr. Faye Briggs is Sr. Principal Engineer and Director of Platform Performance Architecture\, Enterprise Products Group at Intel Corporation. Dr. Briggs led the architecture & engineering teams that develop the Intel AE 870 for 2-16P Itanium AE servers. He was a co-founder and CTO of Axil Computers. While at Sun Microsystems\, he coarchitected the first SPARC-V8\, and led the architecture team to develop multiprocessor SPARCserver2000. Faye Briggs also served on the faculties of Purdue and Rice Universities. He has co-authored a popular textbook on Computer Architecture and Parallel Processing\, and published over 40 technical papers. He received his MSEE from Stanford\, and Ph.D. ECE from the University of Illinois. \n\n\n\n\n\nTechnological Challenges to Computer Architecture Innovation\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/technological-challenges-to-computer-architecture-innovation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040817T150000
DTEND;TZID=America/Los_Angeles:20040817T160000
DTSTAMP:20231011T183336Z
CREATED:20231011T183336Z
LAST-MODIFIED:20231011T183336Z
UID:14299-1092754800-1092758400@www.cecs.uci.edu
SUMMARY:Taming Pointers – A Symbolic Approach
DESCRIPTION:Taming Pointers – A Symbolic Approach\n\n\n\n\nSpeaker\n\n\nProfessor Jianwen Zhu \nDepartment of Electrical and Computer Engineering\nUniversity of Toronto\, Canada\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Daniel Gajski\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nTuesday\, August 17\, 2004\nRefreshments at 2:30pm\, Seminar begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe silicon real estate available in systems-on-chip (SOC) has given hope for the massive-parallel\, high-performance implementation of complex applications. However\, new efforts in silicon compilers that synthesize applications in C into SOC cannot dodge an old problem\, called pointer analysis\, which has been actively pursued in the programming language and compiler community for two decades. The challenges of precise pointer analysis stem from the need to explore an exponential number of program execution paths\, and the need to maintain program state for every program point under all such paths. In this talk\, I will introduce a new method for constructing scalable graph algorithms (ICCAD’02\, PLDI’04)\, called superposition\, which solves different problem instances in an aggregate fashion. Applying this method to pointer analysis\, different program states under different execution paths are combined into a single Boolean function\, and solved together using the efficient\, BDD-based image computation operator developed by the formal verification community. Experimental results show that context-sensitive\, flow-insensitive analysis on programs with billions of different calling paths can be performed\, and benchmarks as large as GCC (200KLOC) can be completed in seconds. The subject of this talk can be of interest to researchers in CAD\, compiler\, software engineering and security.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\n \nJianwen Zhu received the B.S degree in electrical engineering from the Tsinghua University\, Beijing\, China\, and the M.S. and Ph.D. degrees in computer science from the University of California\, Irvine\, in 1993\, 1996 and 1999 respectively. He is currently an assistant professor in the Department of Electrical and Computer Engineering\, University of Toronto\, Canada. He is the coauthor of the book SpecC: Specification Language and Methodology (Kluwer-Academic\, 2000). His research interest includes hardware/software codesign\, high-level synthesis for high-performance circuits and retargetable compilation. \n\n\n\n\n\nTaming Pointers – A Symbolic Approach\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/taming-pointers-a-symbolic-approach/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040604T110000
DTEND;TZID=America/Los_Angeles:20040604T120000
DTSTAMP:20231011T192748Z
CREATED:20231011T180419Z
LAST-MODIFIED:20231011T192748Z
UID:14229-1086346800-1086350400@www.cecs.uci.edu
SUMMARY:Practical Considerations for Power-Aware Real-Time Scheduling
DESCRIPTION:Lecture Slides \nPractical Considerations for Power-Aware Real-Time Scheduling\n\n\n\n\nSpeaker\n\n\nProfessor Sharon Hu\nDepartment of Computer Science and Engineering\nUniversity of Notre Dame\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 4 \, 2004\nRefreshments at 10:30am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nReal-time embedded systems are prevalent in many applications such as computing and communication appliances\, various transportation vehicles\, and medical instruments. A common feature of these systems is that their performance is largely dependent on how well the timing constraints are met. Besides timing requirements\, power consumption is becoming a major consideration in real-time embedded system design as VLSI technology continues its remarkable advances. Techniques to minimize power/energy consumption while satisfying the stringent timing constraints are critical to successful deployment of such systems.The focus of this talk is on the scheduling aspect of hard real-time systems implemented on processors with dynamic voltage scaling (DVS) capabilities. Scheduling to guarantee real-time demands can be a difficult problem. DVS processors introduce a new dimension to the problem. Including realistic considerations\, such as the overhead of transitioning from one voltage level\nto another\, brings yet more challenges. Research results in this area have largely ignored the limitations of practical DVS processors. This talk will discuss several recent results on dealing with non-ideal features of DVS processors for hard real-time systems.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nXiaobo Sharon Hu is an associate professor in the department of Computer Science and Engineering at the University of Notre Dame\, Notre Dame\, Indiana. She also holds a joint appointment in the department of Electrical Engineering at the same university. Her research interests include hardware-software codesign\, real-time embedded systems\, low-power system design\, VLSI design algorithms\, and computer-aided radiation treatment planning. She has published more than 80 papers in these areas and obtained a number research grants from both government and private industry. She was the Technical Program Co-Chair of the 9th International Symposium on Hardware/Software Codesign (CODES’2001) and the General Co-Chair of the same conference in 2002. She has been invited to serve on the program committees of a number of conferences in the electronic design automation field such as DAC\, ICCAD\, DATE\, ICCD\, CODES\, CASES\, etc. In 1997\, she received the NSF’s Faculty Early Career Development (CAREER) Award. A paper co-authored by Sharon Hu and her student received the Best Paper Award from the 38th ACM/IEEE Design Automation Conference in 2001.\n\n\n\nPractical Considerations for Power-Aware Real-Time Scheduling\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/practical-considerations-for-power-aware-real-time-scheduling/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040524T150000
DTEND;TZID=America/Los_Angeles:20040524T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T180420Z
LAST-MODIFIED:20231011T193148Z
UID:14230-1085410800-1085414400@www.cecs.uci.edu
SUMMARY:Towards Better Compilers & Bug Finding for Sensor Networks
DESCRIPTION:Lecture Slides \nTowards Better Compilers & Bug Finding for Sensor Networks\n\n\n\n\nSpeaker\n\n\nProfessor Jens Palsberg\nComputer Science Department\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 24\, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nSensor-network programmers face tough challenges. They must maximize the network life time while managing resource tradeoffs among energy consumption\, stack space\, code size\, response time\, and throughput. For example\, a programmer can choose to inline a call and thereby decrease the response time and decrease the stack space\, but also increase the code size. \nAdditionally\, a programmer can choose to do more computation locally\non a sensor node and thereby decrease communication and the energy consumption\, but also increase the code size. Such tradeoffs make programming difficult and error prone. Most current compilers don’t help with making resource tradeoffs and there are few tools for finding resource bugs such as stack overflow. Can we design better compilers and bug-finding tools that will help out sensor-network programmers? \nIn this talk Jens Palsberg will examine the state of the art (TinyOS\, NesC\, TOSSIM)\, survey recent results on stack analysis and deadline analysis\, and give an overview of the UCLA compiler group’s project on building compiler and bug-finding tools for NesC and the Berkeley Mote sensor node platform.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nJens Palsberg is a Professor of Computer Science at UCLA. His research interests span the areas of compilers\, embedded systems\, programming languages\, software engineering\, and information security. He has authored over 70 technical papers\, co-authored the book Object-Oriented Type Systems\, and co-authored the 2002 revision of Appel’s textbook on Modern Compiler Implementation in Java. He is the recipient of National Science Foundation CAREER and ITR awards\, a Purdue University Faculty Scholar award\, and an Okawa Foundation research award. His research has also been supported by DARPA\, IBM\, Intel\, and British Telecom. He is an associate editor of ACM Transactions of Programming Languages and Systems\, a member of the editorial board of Information and Computation\, and a former member of the editorial board of IEEE Transactions on Software Engineering. He is serving as the general chair of the ACM Symposium on Principles of Programming Languages in 2005.\n\n\n\nTowards Better Compilers & Bug Finding for Sensor Networks\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/towards-better-compilers-bug-finding-for-sensor-networks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040513T150000
DTEND;TZID=America/Los_Angeles:20040513T160000
DTSTAMP:20231011T192253Z
CREATED:20231011T180420Z
LAST-MODIFIED:20231011T192253Z
UID:14231-1084460400-1084464000@www.cecs.uci.edu
SUMMARY:Frequent Value Locality and its Applications
DESCRIPTION:Lecture Slides \nFrequent Value Locality and its Applications\n\n\n\n\nSpeaker\n\n\nProfessor Rajiv Gupta\nComputer Science Department\nUniversity of Arizona\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 13\, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nBy studying the behavior of programs in the SPEC95 benchmark suite we have observed the frequent value phenomenon according to which a few values appear very frequently in memory locations and are therefore involved in a large fraction of memory accesses. Moreover we have observed that the set of frequent values remains stable over the execution of the program and these values are distributed fairly uniformly across the memory. In addition to describing the frequent value phenomenon I will describe two applications of the phenomenon. In the first application\, by transmitting values belonging to a dynamically changing set of frequent values in encoded form\, we greatly reduce the switching activity on a CPU’s external data bus. In the second application\, by storing values belonging to a fixed set of frequent values in compressed encoded form\, we significantly reduce energy consumed by the data cache.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nRajiv Gupta is a Professor of Computer Science at The University of Arizona. His areas of research interest include profile guided code optimization and program analysis; software tools; and performance\, power\, and memory issues in superscalar and embedded processors. Rajiv has published over 170 articles in refereed conferences and journals\, he holds 7 US patents\, and has supervised 12 PhD dissertations. Papers coauthored by him have been selected for: inclusion in 20 Years of PLDI (1979-1999)\, distinguished paper award in ICSE 2003\, most original paper award in ICPP 2003\, and outstanding paper award in ICECCS 1996. Rajiv received the NSF’s Presidential Young Investigator Award in 1991. He served as the Program Chair for PLDI’03 and HPCA’03 conferences. He has also been appointed as the Co-General Chair for CGO’05 and the Program Chair for LCTES’05 conferences. He serves as an Associate Editor for ACM Transactions on Architecture and Code Optimization\, Parallel Computing journal\, and Journal of Embedded Computing.\n\n\n\nFrequent Value Locality and its Applications\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/frequent-value-locality-and-its-applications/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040322T150000
DTEND;TZID=America/Los_Angeles:20040322T160000
DTSTAMP:20231011T183336Z
CREATED:20231011T183336Z
LAST-MODIFIED:20231011T183336Z
UID:14300-1079967600-1079971200@www.cecs.uci.edu
SUMMARY:Bluespec: Why chip design can't be left to EE's
DESCRIPTION:Lecture Slides \nBluespec: Why chip design can’t be left to EE’s\n\n\n\n\nSpeaker\n\n\nProfessor Arvind\nCSAIL (formerly LCS and AI Lab)\nMassachusetts Institute of Technology\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 22\, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHundred million-gate ASICs are possible by the end of the decade. However\, numerous problems related to process technology and design need to be solved before such large chips will become commonplace. Computer scientists are much better equipped to solve the new problems related to the design-in-the-large. Bluespec is a language/methodology that promotes correctness-by-construction. Its underlying execution model is based on atomic actions on state elements (such as flip-flops\, registers\, …)\, i.e.\, any legal behavior is explainable in terms of a sequence of atomic actions on the state. Expressiveness of Bluespec is achieved by keeping its static semantics orthogonal to its hardware execution semantics — the source program is turned into a flat interconnection of modules by “static elaboration” during the compile phase.This talk will present Bluespec via examples and show some of the designs done so far.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nArvind is the Johnson Professor of Computer Science and Engineering at the Massachusetts Institute of Technology. His work at MIT on high-level specification\, modeling\, synthesis and verification of architectures and protocols using Term Rewriting Systems (TRSs) laid the foundations for Sandburst and more recently Bluespec Inc. Previously\, he contributed to the development of dynamic dataflow architectures\, and together with Dr R.S.Nikhil published the book “Implicit Parallel Programming in pH”. Arvind is an IEEE Fellow and was awarded the Charles Babbage Outstanding Scientist Award in 1994. He has received the Distinguished Alumni Awards from the Indian Institute of Technology\, Kanpur\, and the University of Minnesota.\n\n\n\nBluespec: Why chip design can’t be left to EE’s\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/bluespec-why-chip-design-cant-be-left-to-ees/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040206T150000
DTEND;TZID=America/Los_Angeles:20040206T160000
DTSTAMP:20231011T183337Z
CREATED:20231011T183337Z
LAST-MODIFIED:20231011T183337Z
UID:14301-1076079600-1076083200@www.cecs.uci.edu
SUMMARY:Embedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond
DESCRIPTION:Lecture Slides \nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\nSpeakers\n\n\nJonathan R. Haigh and Michael W. Wilkerson\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Veidenbaum\nalexv@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, February 6\, 2004\nRefreshments at 10:30am\, Seminar begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOptimizing power consumption is a primary goal in the design of embedded microprocessors even as the push for higher performance continues.  Managing the microprocessor’s power dissipation while still striving to push the design into GHz speeds provides a significant challenge.  As designs move to 90 nm and beyond\, device scaling has reduced oxide thicknesses and V T to the point where standby leakage power is on the same order of magnitude as active power.  Today’s successful designs need to aggressively manage both active and standby currents.  A collection of methods to control both active and leakage power in Cache and Translation Lookaside Buffer (TLB) circuits\, while minimizing the impact to performance\, will be discussed.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nJonathan R. Haigh: \nJon is the lead L1 cache designer for the current generation of XScale products.  He began his EE career at GE in 1996 followed by the former Digital Semiconductor in 1998.  He joined Intel Corporation in 2000 and has been working on the XScale cache circuit design team since joining the company.  He received his B.S. degree in Electrical Engineering concentrating in VLSI design from the University of Cincinnati .Michael W. Wilkerson: \nMike received the B.S. and M.S. degrees in electrical engineering from the University of Florida in 1991 and 1997.  He was in the U.S. Navy from 1983 to 1996 and joined Intel Corporation in 1998.  He has worked in logic verification and VLSI circuit design for Itanium and XScale microprocessors while at Intel.  He most recently completed the physical design of the data path memory management unit\, which includes a TLB structure\, for a new XScale core.\n\n\n\nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\n\n\n\nclick on the thumbnails to view the full-sized images\n\n\n\n\n\n\nThe lecture was held at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh and Mike Wilkerson are members of the team designing the Intel XScale embedded processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon and Mike chatting with CECS students before delivering their talk. Professor Alex Veidenbaum\, left background\, hosted the event.  \nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nMike Wilkerson discussing embedded processor design challenges. At 90 nm\, it is important to employ architectural techniques that emphasize power reduction.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh explaining cache memory design strategies for the XScale processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nA lively Q & A session followed the presentation.\nview larger image
URL:https://www.cecs.uci.edu/event/embedded-microprocessor-cache-and-translation-lookaside-buffer-tlb-low-power-circuit-techniques-for-90nm-and-beyond/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040116T150000
DTEND;TZID=America/Los_Angeles:20040116T160000
DTSTAMP:20231011T183337Z
CREATED:20231011T183337Z
LAST-MODIFIED:20231011T183337Z
UID:14302-1074265200-1074268800@www.cecs.uci.edu
SUMMARY:System-Level Design: Only the Radical Will Survive
DESCRIPTION:  \nLecture Slides \nSystem-Level Design: Only the Radical Will Survive\n\n\n\n\nSpeaker\n\n\nDr. Reinaldo Bergamaschi\nIBM T. J. Watson Research Center\, Yorktown Heights \, NY\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, January 16\, 2004\nRefreshments served at 10:00 a.m.\, lecture begins at 10:30 a.m.\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe term “system-level design” has been defined\, used and abused countless times by designers\, cad developers and most of all\, tools sales people. By now we all know what is supposed to be\, and it ‘ain’t pretty` (despite the claims by cad vendors). In this talk\, I will argue that for the past 5 years (at least) we have tried to develop system-level tools by fattening the already beaten up ASIC design methodology\, by exaggerating the advantages of high-level languages\, by overblowing the benefits of software-related methodologies for designing hardware\, among other very incremental approaches. The design methodologies and tools currently used for system-on-chip design are an evolution of ASIC and board-level design tools. Such an incremental approach has been ineffective in closing the productivity design gap. I will analyze the current push to use high-level languages and software approaches for hardware design\, and try to convince the audience that such attempts\, while in the right direction\, are far from sufficient. I will argue that radical new approaches for system design are needed if we want to be able to design new products in shorter time-to-market. I will discuss some of the approaches we are developing at IBM Research and speculate on possible new research avenues.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nReinaldo Bergamaschi graduated in Electronics Engineering from the Aeronautics Institute of Technology\, Sao Jose dos Campos\, Brazil \, in 1982\, and in 1984 he received the M.E.E degree from the Philips International Institute\, Eindhoven\, The Netherlands. In 1989 he obtained the Ph.D. degree in Electronics and Computer Science from the University of Southampton\, Southampton\, England\, and joined the IBM T. J. Watson Research Center\, Yorktown Heights \, USA. He has worked extensively on RTL\, behavioral and system-level design tools and methodologies. He was the main architect of IBM’s high-level synthesis system and he is currently developing system-level modeling and synthesis tools for core-based\, platform-based designs. He has participated in numerous conference committees and given several tutorials and lectures on high-level and system-level design issues and tools.\n\n\n\nSystem-Level Design: Only the Radical Will Survive\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/system-level-design-only-the-radical-will-survive/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20031209T150000
DTEND;TZID=America/Los_Angeles:20031209T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14303-1070982000-1070985600@www.cecs.uci.edu
SUMMARY:The Fundamentals: Moore's Law\, Microarchitecture\, and the Microprocessor of the Year 2014
DESCRIPTION:The Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\nSpeaker\n\n\nProfessor Yale Patt\nThe University of Texas at Austin\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Jean-Luc Gaudiot\ngaudiot@uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 9\, 2003\nRefreshments at 1:15pm\, Lecture begins at 1:30pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nMoore’s Law promises very soon more than a billion transistors on a chip processing at more than 10 GHz. But\, what else does Moore ‘s Law tell us about the future of high performance microprocessors. Is there anything left to do in the microarchitecture to make use of all this capability\, or should we fold our tents and go home? Many claim we have reached the end of our rope. In this talk\, I hope to spend a little time discussing the rationale of the naysayer and then move on to what we can do. Per usual\, I plan to tie my comments to the fundamentals\, because I believe it is always the fundamentals that provide the insights to new knowledge. Finally\, I will discuss what I think we will see in the microprocessor of the year 2014\, including the block-structured ISA\, stronger use of SSMT\, greater use of microcode\, dedicated infrequently used functional units\, and most importantly\, a stronger coupling with the compiler\, language\, and algorithm technologies. If time permits\, I will discuss some things I do not think we will see on the chip\, like qbits and machines that think.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nYale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell\, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He directs the Ph.D. research of 12 graduate students in computer architecture and teaches both the freshman introduction to computing and his graduate course in Microarchitecture. He has received the highest honors in his field for his research and teaching\, including the 1996 IEEE/ACM Eckert-Mauchly Award for his contributions to high performance microprocessor design and the 2000 ACM Karl V. Karlstrom Outstanding Educator Award for his contributions to education. He has had\, for the past 35 years\, an active consulting practice\, including long term associations with Intel\, Digital\, NCR\, Motorola\, and others. His freshman textbook “Introduction to Computing Systems: from bits and gates to C and beyond\,” has been adopted by more than 100 universities world-wide. It is co-authored with Professor Sanjay Patel of the University of Illinois . McGraw-Hill just released the second edition this fall. Yale Patt is a Fellow of both the IEEE and the ACM.\n\n\n\nThe Fundamentals: Moore’s Law\, Microarchitecture\, and the Microprocessor of the year 2014\n\n\n\n\n\n\n\nMcDonnell Douglas Auditorium at Engineering Gateway.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nLecture began at 1:30pm at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nProfessor Yale Patt talking about microarchitecture.\nview larger image
URL:https://www.cecs.uci.edu/event/the-fundamentals-moores-law-microarchitecture-and-the-microprocessor-of-the-year-2014/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030722T150000
DTEND;TZID=America/Los_Angeles:20030722T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14304-1058886000-1058889600@www.cecs.uci.edu
SUMMARY:Smart Cameras as High Performance Embedded Systems
DESCRIPTION:by Professor Wayne Wolf\, Princeton University\,McDonnell Douglas Auditorium\, University of California\, Irvine\, CA\nDistinguished Lecture\, July 22\, 2003\nAbstract :: Lecture Slides :: Pictures 
URL:https://www.cecs.uci.edu/event/smart-cameras-as-high-performance-embedded-systems/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030513T150000
DTEND;TZID=America/Los_Angeles:20030513T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14305-1052838000-1052841600@www.cecs.uci.edu
SUMMARY:Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems
DESCRIPTION:by Professor Kang Shin\, University of Michigan\,McDonnell Douglas Auditorium\, University of California\, Irvine\, CA\nDistinguished Lecture\, May 13\, 2003\nAbstract :: Lecture Slides :: Pictures
URL:https://www.cecs.uci.edu/event/real-time-dynamic-voltage-scaling-for-low-power-embedded-operating-systems/
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20030509T100000
DTEND;TZID=America/Los_Angeles:20030509T120000
DTSTAMP:20231011T192949Z
CREATED:20231011T180419Z
LAST-MODIFIED:20231011T192949Z
UID:14228-1052474400-1052481600@www.cecs.uci.edu
SUMMARY:Statistical Tools and Methodologies for Delay Test and Timing Validation
DESCRIPTION:by Li-C. Wang\, UCSB\, ECE DepartmentMay 9\, 2003
URL:https://www.cecs.uci.edu/event/statistical-tools-and-methodologies-for-delay-test-and-timing-validation/
CATEGORIES:Seminars at CECS
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