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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100430T150000
DTEND;TZID=America/Los_Angeles:20100430T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14273-1272639600-1272643200@www.cecs.uci.edu
SUMMARY:Customizable Domain-Specific Computing
DESCRIPTION:Customizable Domain-Specific Computing\n\n\n\n\nSpeaker\n\n\nDr. Jason Cong\,\nCenter for Domain-Specific Computing\,\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 6011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 30\, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n\n \nIn order to meet ever-increasing computing needs and overcome power density limitations\, the computing industry has halted simple processor frequency scaling and entered the era of parallelization\, with tens to hundreds of computing cores integrated in a single processor\, and hundreds to thousands of computing servers connected in a warehouse-scale data center. However\, such highly parallel\, general-purpose computing systems still face serious challenges in terms of performance\, power\, heat dissipation\, space\, and cost. We believe that we need to look beyond parallelization and focus on domain-specific customization as the next opportunity to bring orders-of-magnitude power-performance efficiency improvement to important classes of applications. This challenge requires a great deal of innovation in architecture\, compilation\, and runtime system design\, and offers many exciting and challenging research opportunities. \nI shall talk about the ongoing work at the newly established Center for Domain-Specific Computing supported by the NSF Expeditions in Computing award. Our proposed domain-specific customizable computing platform includes: \n1) a wide range of customizable computing elements\, from heterogeneous fixed cores to coarse-grain customizable cores\, and to fine-grain field-programmable circuit fabrics; \n2) customizable high-performance radio frequency interconnects; \n3) highly automated compilation tools and runtime management software systems for application development; \nand \n4) a general\, reusable methodology for customizable computing applicable across different domains. \nBy combining these critical capabilities\, we aim to provide a supercomputer-in-a-box that is customized to a particular application domain with much higher performance/power efficiency. We choose application domains in healthcare to demonstrate our approach.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nShort biography available at Dr. Jason Cong’s Web Site.
URL:https://www.cecs.uci.edu/event/customizable-domain-specific-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100422T150000
DTEND;TZID=America/Los_Angeles:20100422T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14274-1271948400-1271952000@www.cecs.uci.edu
SUMMARY:Wireless Health Systems
DESCRIPTION:Wireless Health Systems\n\n\n\n\nSpeaker\n\n\nDr. Ani Nehapetian\,\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 22\, 2010\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOne of the most urgent and daunting tasks of our time is providing quality health care in the face of increasing incidence of disease\, aging populations\, and soaring costs. The proliferation of lightweight and heterogeneous embedded systems holds the promise of revolutionizing the accessibility\, quality\, financing\, and delivery of healthcare in much the same way that low-cost cellular phone technology dramatically changed telecommunications worldwide. However\, significant research challenges must be addressed before this wireless health model can reach its full potential.  \nThe talk will include an overview of various devices and systems under development at the UCLA Wireless Health Institute. Additionally\, it will consider important research issues\, including security and and data management.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Ani Nahapetian is currently a researcher with the UCLA Wireless Health Institute and a visiting assistant professor with the UCLA Computer Science department. She received her Ph.D and M.S. in Computer Science\, and B.S. in Computer Science and Engineering\, all from UCLA. Her research interests include embedded systems with health applications\, algorithm design for reconfigurable and low-power embedded systems\, and hardware security.
URL:https://www.cecs.uci.edu/event/wireless-health-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091214T150000
DTEND;TZID=America/Los_Angeles:20091214T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14246-1260802800-1260806400@www.cecs.uci.edu
SUMMARY:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases
DESCRIPTION:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases\n\n\n\n\nSpeaker\n\n\nDr. Masato Motomura\,\nSystem IP Core Research Laboratories\, NEC Corporation\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 14\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nStream Transpose (STP) Engine is a programmable HW core to accelerate stream processing in modern system LSIs. It is composed of an array of numerous numbers of processing and memory elements as well as an intelligent data streaming HW mechanism. Key differentiation from other many-core type parallel architectures lies in its programming model: i.e.\, a design tool based on high-level HW synthesis technology compiles a C source code into a set of pseudo HW configurations which are spatially and temporally mapped onto the array. The STP engine is productized in 90nm-generation system LSIs\, and is targeted for wider-range use in forthcoming generations beyond 40nm.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Motomura received EE doctorial degree from Kyoto University in 1996. He has been engaged in research of various LSI architectures\, such as functional memories\, parallel processors\, and reconfigurable arrays in NEC research laboratories since 1987. From 2002 to 2009\, he led technology and business development of STP Engine in NEC Electronics. He was also the winner of 1992 IEEE JSSC Best Paper Award.
URL:https://www.cecs.uci.edu/event/stp-engine-a-c-based-programmable-hw-core-featuring-massively-parallel-and-reconfigurable-pe-array-its-architecture-tool-and-real-system-usecases/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091118T150000
DTEND;TZID=America/Los_Angeles:20091118T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14275-1258556400-1258560000@www.cecs.uci.edu
SUMMARY:Concurrency and Communication: Lessons from the SHIM Project
DESCRIPTION:Concurrency and Communication: Lessons from the SHIM Project\n\n\n\n\nSpeaker\n\n\nDr. Stephen A. Edwards\,\nColumbia University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Tony Givargis\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 18\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDescribing parallel hardware and software is difficult\, especially in an embedded setting. Five years ago\, we started the SHIM project to address this challenge by developing a programming language for hardware/software systems. The resulting language describes asynchronously running processes that has the useful property of scheduling-independence: the I/O of a SHIM program is not affected by any scheduling choices. I will present a history of the SHIM project with a focus on the key things we have learned along the way.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nStephen A. Edwards received the B.S. degree in Electrical Engineering from the California Institute of Technology in 1992\, and the M.S. and Ph.D degrees\, also in Electrical Engineering\, from the University of California\, Berkeley in 1994 and 1997 respectively. He is currently an associate professor in the Computer Science Department of Columbia University in New York\, which he joined in 2001 after a three-year stint with Synopsys\, Inc.\, in Mountain View\, California. His research interests include embedded system design\, domain-specific languages\, and compilers.
URL:https://www.cecs.uci.edu/event/concurrency-and-communication-lessons-from-the-shim-project/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091117T150000
DTEND;TZID=America/Los_Angeles:20091117T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14276-1258470000-1258473600@www.cecs.uci.edu
SUMMARY:Advanced SoC Architectures for Multiple DRAMs (Enabled by 3D Die Stacking)
DESCRIPTION:Advanced SoC Architectures for Multiple DRAMs\n(Enabled by 3D Die Stacking)\n\n\n\n\nSpeaker\n\n\nDr. Sungjoo Yoo\nPOSTECH\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 17 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe performance of data-intensive applications is mostly determined by the bandwidth and latency of off-chip DRAM. In order to improve the bandwidth and latency characteristics\, multiple memory-based solutions (enabled by 3D stacking of memory dies on top of LSI dies) are being actively investigated. With multiple DRAMs\, we come to face new architectural problems\, especially\, in memory controllers and on-chip network. In this talk\, we will discuss the architectural problems caused by multiple memories and present our solutions (request parallelizer\, in-network reorder buffer\, etc.) to address the problems. We will summarize this talk with some speculations on future SoC architectures with multiple memories.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Sungjoo Yoo received B.S.\, M.S.\, and Ph.D. at Seoul National University\, Korea\, in 1992\, 1995\, and 2000\, respectively. He worked at TIMA laboratory\, Grenoble\, France from 2000 to 2004 and worked as principal engineer at System LSI Division\, Samsung Electronics from 2004 to 2008. At Samsung\, he led a team which developed AMBA3-based on-chip bus architectures for mobile SoCs\, and low power design solutions such as dynamic voltage and frequency scaling (DVFS) algorithms and performed hardware/software co-optimization of solid state disk products. He joined POSTECH (Pohang university of science and technology) in August 2008. His current research interests include memory hierarchy and network-on-chip for many-core SoC\, low power design based on runtime-distribution and temperature-aware DVFS\, and power efficiency/performance/reliability improvement of solid state disk.
URL:https://www.cecs.uci.edu/event/advanced-soc-architectures-for-multiple-drams-enabled-by-3d-die-stacking/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091116T150000
DTEND;TZID=America/Los_Angeles:20091116T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14277-1258383600-1258387200@www.cecs.uci.edu
SUMMARY:Energy Efficient Computing
DESCRIPTION:Energy Efficient Computing\n\n\n\n\nSpeaker\n\n\nProf. Tajana Simunic Rosing\,\nDepartment of CSE\,\nUC San Diego\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Daniel Gajski\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 16 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk\, we will present the algorithms we have developed at UCSD for lowering the energy consumption in computing systems. We derived optimal power management strategies for stationary workloads that have been implemented both in HW and SW. Run-time adaptation can be done via an online learning algorithm that selects among a set of policies. We generalized the algorithm to include thermal management since we found that minimizing the power consumption does not necessarily reduce the overall energy costs. To reduce the performance costs typically associated with state of the art thermal management techniques\, we also developed a new set of proactive management policies. The experimental results using real datacenter workloads on an actual multicore system show that our proactive technique is able to dramatically reduce the adverse effects of temperature by over 60%. Most recently we have shown that symbiotic scheduling of workloads in virtualized environments can lead to average 15% energy savings with 20% performance benefit in high utilization scenarios.We will also present some of the recent work that address the energy savings in battery powered systems\, as demonstrated in a new kind of “citizen infrastructure”\, an end-to-end health and environmental information system with near real-time data streams and feedback loops from the system to the sensing\, processing\, and actuation infrastructure. We have developed adaptive algorithms to tradeoff accuracy of computation versus the available energy for such systems\, while taking into account the energy harvesting capabilities.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nTajana Simunic Rosing is currently an Assistant Professor in Computer Science Department at UCSD\, a director of System Energy Efficiency Lab at UCSD and a head of the Energy efficient datacenter thrust as a part of the MuSyC center. Her research interests are energy efficient computing\, embedded and wireless systems. She finished her PhD at Stanford University. Prior to pursuing the PhD\, she worked as a Senior Design Engineer at Altera Corporation. She has served at a number of Technical Paper Committees\, and is currently an Associate Editor of IEEE Transactions on Mobile Computing.
URL:https://www.cecs.uci.edu/event/energy-efficient-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091112T150000
DTEND;TZID=America/Los_Angeles:20091112T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T180836Z
LAST-MODIFIED:20231011T192457Z
UID:14247-1258038000-1258041600@www.cecs.uci.edu
SUMMARY:NEC's Manycore Platforms for Low-Power Embedded System
DESCRIPTION:NEC’s Manycore Platforms for Low-Power Embedded System\n\n\n\n\nSpeaker\n\n\nNaoki Nishi\nGM\, NEC Central Research Labs\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 12\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAfter short introduction of NEC’s R&D vision related to future ICT system handling real world in real time\, two examples of NEC’s manycore research activities will be presented. First example is an in-vehicle vision processor IMAPCAR-2 which supports SIMD-MIMD morphing\, and the second is a fine grain manycore architecture called STP (Stream TransPoser) engine which is a kind of dynamically reconfigurable hardware with C level language SDK support.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nNaoki Nishi is a general manager at central research labs.\, NEC. He jointed NEC in 1984\, where he worked in research on micro-architectures and LSI development of the NEC SX vector supercomputer\, After the development of CMOS vector supercomputer SX-4 in 1996\, he has been conducting research on high-performance\, low-power multi-/many-cores. Naoki Nishi received his B.E. and M.E. degrees in system engineering from Hiroshima University\, Japan.
URL:https://www.cecs.uci.edu/event/necs-manycore-platforms-for-low-power-embedded-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091022T150000
DTEND;TZID=America/Los_Angeles:20091022T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192031Z
UID:14248-1256223600-1256227200@www.cecs.uci.edu
SUMMARY:A Virtualization-Based Software Architecture for Real-Time Embedded Systems
DESCRIPTION:A Virtualization-Based Software Architecture for Real-Time Embedded Systems\n\n\n\n\nSpeaker\n\n\nDr. Sung-Soo Lim\nAssistant Professor\,\nSchool of Computer Science\,\nKookmin University\,\nSeoul\, Korea\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 22 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThis talk introduces an on-going work in Embedded Systems Laboratory\, Kookmin University to build next generation software architecture for mobile phones cooperating with Samsung Electronics. Future mobile phones need to accommodate both legacy applications and hard real-time communication protocols regardless of the underlying hardware organization. Such support for flexibility and reconfigurability should be accompanied with guarantee of reliability and security.  \nWe design and implement a light-weight hypervisor based on L4 microkernel for real-time embedded systems accommodating both general-purpose and hard real-time operating systems. The virtualization-based software architecture based on our hypervisor could have the reliability with zero-down feature and safety during dynamic software upgrade. We built a prototype smartphone platform running both Linux and uCOS-II on a single ARM11 core using the proposed software architecture. The structure and core techniques used in our software architecture will be introduced in the talk.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nSung-Soo Lim received BS\, MS\, and PhD degrees in Computer Engineering from Seoul National University in 1993\, 1995\, and 2002\, respectively. From 2000 to 2001\, he was a visiting researcher in University of Illinois at Urbana-Champaign. From 2001 to 2004\, he was the CTO of PalmPalm Technology\, Inc. in Korea (a smartphone development company). He is currently an assistant professor in School of Computer Science\, Kookmin University. His research area includes real-time operating systems\, real-time performance analysis\, low-power technology\, and mobile phone architecture.
URL:https://www.cecs.uci.edu/event/a-virtualization-based-software-architecture-for-real-time-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091019T150000
DTEND;TZID=America/Los_Angeles:20091019T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14249-1255964400-1255968000@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 19 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091009T150000
DTEND;TZID=America/Los_Angeles:20091009T160000
DTSTAMP:20231011T192654Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192654Z
UID:14250-1255100400-1255104000@www.cecs.uci.edu
SUMMARY:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA
DESCRIPTION:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA\n\n\n\n\nSpeaker\n\n\nProf. Lei He\nElectrical Engineering Department\,\nUCLA\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Eli Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 9\, 2009\nRefreshments at 10:30am; Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAs devices become smaller\, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired\, especially if no extra area\, power and delay and little change of the existing design flow are introduced. Using FPGA and internet router as a testbed\, this talk first presents fault tolerance techniques applying (1) logic don’t care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both increase MTTF by 2X with little or no overhead. Particularly\, IPR does not change circuit placement and routing\, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. Finally\, I will briefly discuss my ongoing research on cyber-physical systems involving renewal energy storage and environment/water monitoring.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Lei He is an associate professor at electrical engineering department\, UCLA\, and was a faculty member at University of Wisconsin\, Madison between 1999 and 2001. He also held visiting or consulting positions with Intel\, Hewlett-Package\, Cadence and Synopsys\, was a technical advisory board member for Rio Design Automation\, and Apache Design Solutions\, and is a guest professor at Fudan University (China) and China National Laboratory for Optoelectronics.  \nHis research interests include electronic design automation\, VLSI circuits and systems\, and cyber-physical systems. He has published one book and over 200 technical papers and has been a technical program committee member for a number of conferences including Design Automation Conference\, International Conference on Computer-Aided Design\, International Symposium on Low Power Electronics and Design\, International Symposium on Field Programmable Gate Array\, and International Symposium on Physical Design. Dr. He obtained Ph.D. degree in computer science from UCLA in 1999. He was granted National Science Foundation CAREER award in 2000\, UCLA Chancellor’s faculty career development award in 2003\, IBM Faculty Award in 2003\, Northrop Grumman Excellence in Teaching award in 2005\, best paper award at the 2006 International Symposium on Physical Design\, and multiple best paper nominations at Design Automation Conference and International Conference on Computer-Aided Design.
URL:https://www.cecs.uci.edu/event/power-efficient-and-fault-tolerant-circuits-and-systems-using-commodity-fpga/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090805T150000
DTEND;TZID=America/Los_Angeles:20090805T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14279-1249484400-1249488000@www.cecs.uci.edu
SUMMARY:Portable Direct Methanol Fuel Cell System for Green Computing
DESCRIPTION:Portable Direct Methanol Fuel Cell System for Green Computing\n\n\n\n\nSpeaker\n\n\nDr. Naehyuck Chang\nSeoul National University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nCalIT2 Room 3008\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nAugust 5 \, 2009\nRefreshments at 10:00 am\, Lecture begins at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe introduce a hybrid portable direct methanol fuel cell (DMFC) system\nwhich includes a li-ion battery. We demonstrate a hybrid operation of\nthe DMFC stack and the li-ion battery to maintain a constant stack\noutput current regardless of the load current to maximize the\nperformance. We describe the balance of plant (BOP) control system\,\nincluding a 32-bit microprocessor\, and electronics to drive motors\,\nactuators and sensors for reliable operation and protection of a DMFC\nsystem. The dynamics of BOP control is taken into account to design\nmultiple cascaded feedback control loops. We demonstrate robust\noperation of a DMFC system together with introduction of a DMFC system\ndesign. This talk includes a working prototype system demonstration of a\ncomplete DMFC and battery hybrid power source.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nNaehyuck Chang received his BS\, MS and PhD degrees all from Seoul National University\, in 1989\, 1992 and 1996\, respectively. He was a research associate at Dept. of Electrical Engineering and Computer Science at University of Michigan in Ann Arbor in 1997. He joined Seoul National University in Dept. of Computer Science and Engineering in 1997 as a faculty member and now is an Associate Professor in Dept. of Electrical Engineering and Computer Science. He was also a Visiting Associate Professor at Arizona State University in 2005. He has been with Sindoricoh\, Co. Ltd.\, as a Technical Advisor since 2001. He has published more than 70 technical papers in low-power and embedded systems area.
URL:https://www.cecs.uci.edu/event/portable-direct-methanol-fuel-cell-system-for-green-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090722T150000
DTEND;TZID=America/Los_Angeles:20090722T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14281-1248274800-1248278400@www.cecs.uci.edu
SUMMARY:Compiler-enabled Power-efficient Register File Protection
DESCRIPTION:Compiler-enabled Power-efficient Register File Protection\n\n\n\n\nSpeaker\n\n\nDr. Jongeun Lee\nEECS\, Ulsan National Institute of Science and Technology\,Korea\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 22\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRegister file (RF) is extremely vulnerable to soft errors\, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor\, but also since it is one of the hottest blocks on the chip\, and therefore adding any extra circuitry to it is not desirable. Software approaches would be ideal in this case\, but previous approaches that are based on program duplication have very significant runtime overheads\, and others based on instruction scheduling are only moderately effective due to local scope.  \nThis talk will be about how compiler alone and in conjunction with microarchitecture can power-efficiently protect the RF. What we have observed is that a significant portion of the RF vulnerability is contributed by long lifetime variables. Protecting only these can result in power-efficient RF protection. Thus the task of the compiler is to identify program variables that have long lifetimes and protect them. Our experiments demonstrate pure compiler techniques can reduce the vulnerability of the RF by 33-37% on average and up to 66%\, with a small (2%) runtime overhead. As compared to hardware protection mechanisms\, compiler analysis can achieve the same level of protection but at up to 75% lesser RF energy consumption.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nJongeun Lee received a BS and an MS in Electrical Engineering and a PhD in Electrical Engineering and Computer Science all from Seoul National University. Previously he was with Samsung SoC R&D Center in Korea\, and is currently a postdoctoral associate at Arizona State University\, working with Dr. Aviral Shrivastava. He is joining Ulsan National Institute of Science and Technology\, Korea\, as an Assistant Professor of EECS. His research interests include configurable/reconfigurable processor architecture design\, compilation for energy and reliability\, and compilation for multicore processors and GPUs.
URL:https://www.cecs.uci.edu/event/compiler-enabled-power-efficient-register-file-protection/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090504T150000
DTEND;TZID=America/Los_Angeles:20090504T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14251-1241449200-1241452800@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n  \n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 4\, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm (Lecture Cancelled)\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090309T150000
DTEND;TZID=America/Los_Angeles:20090309T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T181037Z
LAST-MODIFIED:20231011T192457Z
UID:14252-1236610800-1236614400@www.cecs.uci.edu
SUMMARY:Nonlinear Symbolic Program Analysis for Increased Parallelization
DESCRIPTION:Nonlinear Symbolic Program Analysis for Increased Parallelization\n\n\n\n\nSpeaker\n\n\nProfessor Kleanthis Psarris \nDepartment of Computer Science\nThe University of Texas at San Antonio\, TX\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Nicolau\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 9\, 2009\nRefreshments at 2:30 pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHigh end parallel and multi-core processors rely on compilers to perform the necessary optimizations and exploit concurrency in order to achieve higher performance. However\, source code for high performance computers is extremely complex to analyze and optimize. In particular\, program analysis techniques often do not take into account complex expressions during the data dependence analysis phase. Most data dependence tests are only able to analyze linear expressions\, even though non-linear expressions occur very often in practice. Therefore\, considerable amounts of potential parallelism remain unexploited. In this talk we propose new data dependence analysis techniques to handle such complex instances of the dependence problem and increase program parallelization. Our method is based on a set of polynomial time techniques that can prove or disprove dependences in source codes with non-linear and symbolic expressions\, complex loop bounds\, arrays with coupled subscripts\, and if-statement constraints. In addition our algorithm can produce accurate and complete direction vector information\, enabling the compiler to apply further transformations. To validate our method we performed an experimental evaluation and comparison against the I-Test\, the Omega test and the Range test in the Perfect and SPEC benchmarks. The experimental results indicate that our dependence analysis tool is accurate\, efficient and more effective in program parallelization than the other dependence tests. The improved parallelization results into higher speedups and better program execution performance in several benchmarks.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nKleanthis Psarris is Professor and Chair of the Department of Computer Science at the University of Texas at San Antonio. His research interests are in the areas of Parallel and Distributed Systems\, Compilers and Programming Languages. He received his B.S. degree in Mathematics from the National University of Athens\, Greece in 1984. He received his M.S. degree in Computer Science in 1987\, his M.Eng. degree in Electrical Engineering in 1989 and his Ph.D. degree in Computer Science in 1991\, all from Stevens Institute of Technology in Hoboken\, New Jersey. He has published extensively in top journals and conferences in the field and his research has been funded by the National Science Foundation and Department of Defense agencies. He is an Editor of the Parallel Computing journal. He has served on the Program Committees of several international conferences including the ACM International Conference on Supercomputing (ICS) in 1995\, 2000\, 2006 and 2008\, the IEEE International Conference on High Performance Computing and Communications (HPCC) in 2008 and 2009\, and the ACM Symposium on Applied Computing (SAC) in 2003\, 2004\, 2005 and 2006.
URL:https://www.cecs.uci.edu/event/nonlinear-symbolic-program-analysis-for-increased-parallelization/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081119T150000
DTEND;TZID=America/Los_Angeles:20081119T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14282-1227106800-1227110400@www.cecs.uci.edu
SUMMARY:My Work and My Life
DESCRIPTION:by Prof. Leonard KleinrockDepartment of Computer Science\nUniversity of California\, Los Angeles\nMcDonnell Douglas Auditorium\nDistinguished Lecture\, November 19\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/my-work-and-my-life/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081104T150000
DTEND;TZID=America/Los_Angeles:20081104T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192254Z
UID:14243-1225810800-1225814400@www.cecs.uci.edu
SUMMARY:Geppeto*: Consumer’s Approach to Programming
DESCRIPTION:Prof. Sinisa Srbljic\, School of Electrical Engineering and Computing\, University of Zagreb\, CroatiaNovember 4\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/geppeto-consumers-approach-to-programming/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14244-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models
DESCRIPTION:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models\n\n\n\n\nSpeaker\n\n\nDr. Christian Haubelt\nUniversity of Erlangen-Nuremberg\, Germany\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Tower\, Room 331\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 13 \, 2008\nTalk begins 11:00am\nRefreshments at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n80% of all design decisions are made in the first 20% of the design time. Thus\, a substantiated knowledge about possible solutions is mandatory in early design phases in order to design high quality products. SystemCoDesigner is a software tool for automatic design space exploration at the electronic system level and for platform-based prototyping of hardware/software systems. By exploring the design space\, a designer becomes more confident in decisions to be done. Starting from a behavioral SystemC description different solutions are generated automatically by using software synthesis techniques and Forte Design Systems’ Cynthesizer for behavioral hardware synthesis. In order to allow such a degree of automation\, SystemCoDesigner requires the behavioral SystemC model to be representable in a well-defined Model of Computation\, called FunState. As a case study\, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput\, ranging from software only solutions up to pure hardware implementations which reach real-time performance for QCIF streams on a 50MHz FPGA. In this talk\, the SystemCoDesigner overall design flow\, the FunState Model of Computation\, and some automatic transformation are presented using the Motion-JPEG case study.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nChristian Haubelt received his diploma degree in Electrical Engineering from the University of Paderborn\, Germany\, in 2001. He received his Ph.D. in Computer Science from the University of Erlangen-Nuremberg\, Germany\, in 2005. Since 2004\, he is head of the System-Level Design Automation Group at the Chair of Hardware/Software Co-Design\, University of Erlangen-Nuremberg\, Germany. Dr. Haubelt’s research interests include electronic system level design\, system level design automation\, and multi-objective optimization.\n\n\n\n\n\n\n\n\n\n\nWeb Site\n\n\nhttp://www12.informatik.uni-erlangen.de/people/haubelt/
URL:https://www.cecs.uci.edu/event/systemcodesigner-automatic-design-space-exploration-and-rapid-prototyping-from-behavioral-models/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080429T150000
DTEND;TZID=America/Los_Angeles:20080429T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14283-1209481200-1209484800@www.cecs.uci.edu
SUMMARY:Hardware-Accelerated Formal Verification
DESCRIPTION:by Prof. Masahiro FujitaVLSI Design and Education Center\nUniversity of Tokyo\, Tokyo\, Japan\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, April 29\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/hardware-accelerated-formal-verification/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080324T150000
DTEND;TZID=America/Los_Angeles:20080324T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14284-1206370800-1206374400@www.cecs.uci.edu
SUMMARY:On Numerical Modeling of Large Strain Elastoplastic Structural Responses
DESCRIPTION:By Jurica Sori?Institute of Applied Mechanics\nFaculty of Mechanical Engineering and Naval Architecture\, University of Zagreb\, Croatia\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, Mar 24\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/on-numerical-modeling-of-large-strain-elastoplastic-structural-responses/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080306T150000
DTEND;TZID=America/Los_Angeles:20080306T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14245-1204815600-1204819200@www.cecs.uci.edu
SUMMARY:Tiptoe: A Compositional Real-Time Operating System
DESCRIPTION:Prof. Christoph Kirsch\, Dept. of Computer Sciences\, University of SalzburgDonald Bren Hall (DBH) 3011\, University of California\, Irvine\nMarch 06\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/tiptoe-a-compositional-real-time-operating-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080110T150000
DTEND;TZID=America/Los_Angeles:20080110T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14285-1199977200-1199980800@www.cecs.uci.edu
SUMMARY:Opportunities for Power and Performance Optimization in Digital Feedback-Controllers
DESCRIPTION:By Prof. Forrest Brewer\, Deptment of Electrical & Computer EngineeringUniversity of California\, Santa Barbara\nEngineering Gateway\, Room 3161\, University of California\, Irvine\nLecture\, Jan 10\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/opportunities-for-power-and-performance-optimization-in-digital-feedback-controllers/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20071229T150000
DTEND;TZID=America/Los_Angeles:20071229T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14286-1198940400-1198944000@www.cecs.uci.edu
SUMMARY:Passive Supply Voltage And Frequencey Scaling (PVS)
DESCRIPTION:By Prof. Naehyuck Chang\, EECS Department\, Seoul National UniversityBren Hall Room. 3011\, Unversity of California\, Irvine\nLecture\, Dec 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/passive-supply-voltage-and-frequencey-scaling-pvs/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070615T150000
DTEND;TZID=America/Los_Angeles:20070615T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192949Z
UID:14236-1181919600-1181923200@www.cecs.uci.edu
SUMMARY:The ADRES & DRESC dynamically reconfigurable architecture and ANSI C compiler
DESCRIPTION:Dr. Bjorn De Sutter\, IMEC Research Labs\, Belgium Calit2 Room 3008\, University of California\, Irvine\nJune 15\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/the-adres-dresc-dynamically-reconfigurable-architecture-and-ansi-c-compiler/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070608T150000
DTEND;TZID=America/Los_Angeles:20070608T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192031Z
UID:14237-1181314800-1181318400@www.cecs.uci.edu
SUMMARY:A Methodology for Creating Application Specific Processor Architectures
DESCRIPTION:Prof. Anshul Kumar\, Indian Institute of Technology\, Delhi Calit2 Room 3008\, University of Califonria\, Irvine\nJune 08\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/a-methodology-for-creating-application-specific-processor-architectures/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T193148Z
UID:14238-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Transparent Acceleration of Data Dependent Instructions for General Purpose Processors
DESCRIPTION:Prof. Luigi Carro\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract 
URL:https://www.cecs.uci.edu/event/transparent-acceleration-of-data-dependent-instructions-for-general-purpose-processors/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070529T150000
DTEND;TZID=America/Los_Angeles:20070529T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T180634Z
LAST-MODIFIED:20231011T192031Z
UID:14239-1180450800-1180454400@www.cecs.uci.edu
SUMMARY:Adaptive Mechanisms for Meeting Energy and Real-Time Constraints in MPSoC Platforms
DESCRIPTION:Prof. Flavio R. Wagner\, Federal University of Rio Grande do SulCalit2 Auditorium\, University of California\, Irvine\nMay 29\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/adaptive-mechanisms-for-meeting-energy-and-real-time-constraints-in-mpsoc-platforms/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070426T150000
DTEND;TZID=America/Los_Angeles:20070426T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192254Z
UID:14240-1177599600-1177603200@www.cecs.uci.edu
SUMMARY:High Level Systems Validation Using Hierarchical Message Sequence Charts
DESCRIPTION:Dr. Praveen Murthy\, Fujitsu Labs of AmericaCalit2 Auditorium\, University of California\, Irvine\nApril 26\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/high-level-systems-validation-using-hierarchical-message-sequence-charts/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070325T150000
DTEND;TZID=America/Los_Angeles:20070325T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14287-1174834800-1174838400@www.cecs.uci.edu
SUMMARY:Operating system kernel as a building block for scalable and fast network topology emulation
DESCRIPTION:Marko Zec\, University of Zagreb\, Croatia5251 California Ave.\, Suite 210 ( CECS Research Park Office)\, Unversity of California\, Irvine\nLecture\, May 25\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/operating-system-kernel-as-a-building-block-for-scalable-and-fast-network-topology-emulation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070316T150000
DTEND;TZID=America/Los_Angeles:20070316T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14241-1174057200-1174060800@www.cecs.uci.edu
SUMMARY:Embedded Control Software Engineering Methods and Tools Research at ISL\, Bangalore
DESCRIPTION:Dr. S. Ramesh\, Technical Fellow\, India Science Lab\, GM R&D Labs\, Bangalore\, IndiaCalit2 Auditorium\, University of California\, Irvine\nMarch 16\, 2007 \nAbstract
URL:https://www.cecs.uci.edu/event/embedded-control-software-engineering-methods-and-tools-research-at-isl-bangalore/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20070309T150000
DTEND;TZID=America/Los_Angeles:20070309T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180635Z
LAST-MODIFIED:20231011T192041Z
UID:14242-1173452400-1173456000@www.cecs.uci.edu
SUMMARY:Arithmetic Optimizations for System Design
DESCRIPTION:Dr. Farzan Fallah\, Fujitsu LaboratoriesCalit2 Auditorium\, University of Califonia\, Irvine\, CA\nLecture\, March 09\, 2007\nAbstract
URL:https://www.cecs.uci.edu/event/arithmetic-optimizations-for-system-design/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR