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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110712T150000
DTEND;TZID=America/Los_Angeles:20110712T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14263-1310482800-1310486400@www.cecs.uci.edu
SUMMARY:Hybrid Electrical Energy Storage Systems
DESCRIPTION:Hybrid Electrical Energy Storage Systems\n\n\n\n\nSpeaker\n\n\nProf. Naehyuck Chang\nSeoul National University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEH 2111\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 12 \, 2011\nLecture begins at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nElectrical energy is a high-quality form of energy in the sense that it can be easily and efficiently converted into other forms of energy\, and furthermore it can be used to control other forms of energy. Unfortunately\, electricity supply and demand are typically not balanced with each other. Storage of excessive energy and compensation of the energy shortage can significantly mitigate the over-investment in the generation facilities.  \nLike memory devices\, no single type of electrical energy storage (EES) element can fulfill all the desirable requirements. Despite active research on the new EES technologies\, it is not likely to have an ultimate high-efficiency\, high- power/energy capacity\, low-cost\, and long-cycle life EES element in the near future. We propose an hybrid electrical energy storage (HEES) system that consists of two or more heterogeneous EES elements\, thereby realizing the advantages of each EES element while hiding their weaknesses. \nCompared with the conventional homogeneous EES systems\, HEES systems provide high output power and energy density as well as high power conversion efficiency and low self-discharge at a low capital cost. Cycle efficiency of a HEES system\, which is defined as the ratio of energy which is delivered by the HEES system to the load device to energy which is supplied by the power source to the HEES system\, is one of the most important factors in determining the overall operational cost of the system. \nWe formulate the HEES management problems and project them into computer memory system design and management. We break the HEES management problems into charge allocation into different banks of EES elements\, charge replacement (i.e.\, discharge) from different banks of EES elements\, and charge migration from one bank to another bank of EES elements. Even a hybrid EES system cannot achieve high cycle efficiency if their storage banks have a fixed power and voltage rating because the optimal power capacity and voltage rating varies by the application and the state of charge (SoC) of the storage bank. Bank reconfiguration dynamically changes the array structure of an EES bank and maximizes the efficiency. \nIn this talk\, we start from introduction to the concept of HEES systems including EES element characteristics and power converter characteristics. The main body of this talk is charge allocation\, migration\, optimization\, and bank reconfiguration. The HEES research is recently brought up\, and thus there are a lot of important open problems. We will conclude this talk with remarks on the future work.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nNaehyuck Chang is a Full Professor in Dept. of Electrical Engineering and Computer Science\, Seoul National University\, Korea. He was a Visiting Associate Professor at Arizona State University in 2005\, and a Visiting Professor at University of Southern California in 2009-2010. He serves (and served) as Technical Program Committee of major EDA and embedded systems conferences and symposia including DAC\, ICCAD\, ISLPED\, DATE\, ASP-DAC\, GLS-VLSI\, ISQED\, PATMOS\, ESTIMedia\, ICCD\, and so on.  He served as the TPC Co-Chair of RTCSA in 2007\, ISLPED in 2009\, and ESTIMedia in 2009 and 2010. He was Vice GC of ISLPED 2010 and is General Co-Chair of ISLPED 2011. He is also General Chair of ESTIMedia in 2011. He will serve as a TPC Co-Chair of CODES+ISSS 2012. He is an Associate Editor of IEEE TCAD and ACM TODAES\, and editorial board members of JOLPE and JEC. He is a guest editor of ACM TODAES in 2011 and TECS for low-power design and embedded multi-media systems in 2010 and 2011. He also serves as the Chair of ACM SIGDA Low-Power Technical Committee\, ASP-DAC SIGDA Representative and ACM SIGDA Executive Committee (Technical Activity Chair). He is a Senior Member of ACM and IEEE.
URL:https://www.cecs.uci.edu/event/hybrid-electrical-energy-storage-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110603T150000
DTEND;TZID=America/Los_Angeles:20110603T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T192031Z
UID:14256-1307113200-1307116800@www.cecs.uci.edu
SUMMARY:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund
DESCRIPTION:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund\n\n\n\n\nSpeaker\n\n\nPeter Marwedel\nChair for Embedded Systems\nTU Dortmund/Informatik 12 + ICD\nDortmund\, Germany\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nRainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 3\, 2011\nRefreshments at 9:30 am\, Lecture begins at 10:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe group headed by Dr. Marwedel focuses on the design of efficient embedded systems. The talk will provide an overview of the research performed in this group:  \n\nEmbedded systems connected to the physical environment must meet timing constraints. Typically\, timing verification is performed after software generation\, possibly leading to many design iterations until timing constraints are finally met. In order to avoid such loops\, compilers can be made timing-aware. An approach for such integration will be presented together with some results.\nThe next part of the talk will be about addressing the memory wall problem. In particular\, the use of energy-efficient and timing-predictable scratchpad memories will be presented. Results on the worst-case execution time aware compilation for an automotive application using scratchpad memories will be included.\nThe final part will cover other research projects in the DAES group. These include two projects of the collaborative research project on resource constrained machine learning (SFB 876). In the first project\, resource-efficient image analysis for an advanced real-time virus detector is the subject for design space exploration. The second project aims at speeding up the execution of programs written in R (a language frequently used for statistical analyses) by about two orders of magnitude\, thereby enabling more comprehensive statistical analyses\, particularly in life sciences. Another project addresses the problem of guaranteeing timeliness for systems based on unreliable hardware.
URL:https://www.cecs.uci.edu/event/an-overview-over-research-activities-at-the-design-automation-for-embedded-systems-daes-group-at-tu-dortmund/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110602T150000
DTEND;TZID=America/Los_Angeles:20110602T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14264-1307026800-1307030400@www.cecs.uci.edu
SUMMARY:GoldMine: Automatic Assertion Generation and Achieving Test Coverage Closure
DESCRIPTION:GoldMine: Automatic Assertion Generation and Achieving Test Coverage Closure\n\n\n\n\nSpeaker\n\n\nProf. Shobha Vasudevan\nECE\, University of Illinois at Urbana-Champaign\nUrbana\, Illinois\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 2\, 2011\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAssertions are ubiquitous in the modern system design cycle. They are used in pre-Silicon verification\, post-Silicon validation and debug\, emulation\, reliability checking\, and many related functional assurance phases. Assertion generation is an intensely manual\, time-intensive task. GoldMine\, developed by my group in UIUC\, is an assertion generation software that uses a combination of data mining and static analysis of the design. GoldMine uses formal verification to guide the data mining algorithms. GoldMine assertions are attested by designers\, as adding value to the verification process. In the first part of my talk\, I will present the function and working of this engine\, as well as its recent application at the specification level.  \nCounterexample feedback from formal verification of an assertion can be used to grow the size of the data set that is mined by GoldMine. When iteratively applied\, this data set eventually captures the entire behavior. This data set now forms a test suite where coverage closure can be achieved. This algorithm for monotonically increasing coverage of validation inputs is presented in the second part of my talk. I will also discuss how GoldMine can be applied in the context of soft error detection and emulation.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nShobha Vasudevan is an assistant professor of Computer Engineering in the ECE Department\, at the Univ of Illinois. She obtained her PhD and MS degrees from the University of Texas at Austin. Her research interests are in design verification\, validation\, reliability\, software testing\, data mining and formal verification. She is a recepient of the 2010 NSF CAREER award and the YWCA leadership in Science award.
URL:https://www.cecs.uci.edu/event/goldmine-automatic-assertion-generation-and-achieving-test-coverage-closure/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110309T150000
DTEND;TZID=America/Los_Angeles:20110309T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14265-1299682800-1299686400@www.cecs.uci.edu
SUMMARY:Multi-Agent Automated Negotiation and its Application to Collective Collaboration Systems
DESCRIPTION:Multi-Agent Automated Negotiation and its Application to Collective Collaboration Systems\n\n\n\n\nSpeaker\n\n\nDr. Takayuki Ito\nNagoya Institute of Technology\, The University of Tokyo and Japan Science and Technology Agency\nNagoya\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nKwei-Jay Lin\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 9 \, 2011\nRefreshments at 1:00 pm\, Lecture begins at 1:30pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nMulti-agent system is a system which cooperatively or competitively solve shared or distributedproblems. While agents could be acting on behalf of human users\, agents could be intelligent entities in the virtual world. In this talk\, I would like to introduce what is “multi-agent systems”\, and show the state of the art of theoretical researches and practical results. Also\, I would like to mention about the application to cloud computing and collective intelligence.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Takayuki ITO received the B.E.\, M.E\, and Doctor of Engineering from the Nagoya Institute of Technology in 1995\, 1997\, and 2000\, respectively. From 1999 to 2001\, he was a research fellow of the Japan Society for the Promotion of Science (JSPS). From 2000 to 2001\, he was a visiting researcher at USC/ISI (University of Southern California/Information Sciences Institute). From April 2001 to March 2003\, he was an associate professor of Japan Advanced Institute of Science and Technology (JAIST).  He joined Nagoya Institute of Technology as an associate professor of Graduate School of Engineering in April 2003. From 2005 to 2006\, he is a visiting researcher at Division of Engineering and Applied Science\, Harvard University and a visiting researcher at Sloan School of Management\, Massachusetts Institute of Technology. From 2008 to 2010\, he was\, again\, a visiting researcher at Sloan School of Management\, Massachusetts Institute of Technology. From 2010\, he is a senior researcher of the Policy Alternatives Research Institute\, University of Tokyo. \nFrom 2010\, he is a researcher selected for the most advanced and next generation research development program (1\,850\,000USD) by the Japan Cabinet Office. From 2009 to 2010\, he was the JST PREST (Sakigake fund 490\,000USD\, Big Challenge Type) Researcher. He resigned the JST PREST researcher because of the Cabinet office program. He received several Grants-in-Aid for Science Research funds from the Japan Society for the Promotion of Science (JSPS). The amounts are 212\,500USD(2005-2008) and 226\,500USD(2006-2009)\, for example\, and other national funds. \nHe received the Young Scientists’ Prize\, The Commendation for Science and Technology by the Minister of Education\, Culture\, Sports\, Science\, and Technology\, 2007\, the Nagao Special Research Award of the Information Processing Society of Japan\, 2007\, the Best Paper Award of AAMAS2006\, the 2005 Best Paper Award from Japan Society for Software Science and Technology\, the Best Paper Award in the 66th annual conference of 66th Information Processing Society of Japan\, and the Super Creator Award of 2004 IPA Exploratory Software Creation Projects. \nHe edited and is editing 5 Books. He published over 35 Journal papers\, over 100 conference/workshop papers\, and over 100 other papers. He is a board member of the International Foundation of Autonomous Agents and Multi-Agent Systems (IFAAMAS)\, Steering Committee Member\, International Conference on Principles and Practice of Multi-Agent Systems (PRIMA)\, the Editor-In-Chief of Journal of Information Processing Society of Japan\, and the editor of Journal of Japanese Society of Artificial Intelligence (JSAI). \nHe was SPC of the International Joint Conference on Artificial Intelligence (IJCAI2009\,2001)\, a SPC of the 8th International Joint Conference on Autonomous Agents and Multi-Agent Systems(AAMAS2007\,2008\,2011)\,  SPC of The 25th AAAI Conference on Artificial Intelligence (AAAI-11) \, 2011. Senior Program Committee\, the Publications Chair of the 6th International Joint Conference on Autonomous Agents and Multi-Agent Systems (AAMAS2006)\, PC member of The 19th European Conference on Artificial Intelligence (ECAI2010)\, the Organizing Chair of the International Workshop on Rational\, Robust\, and Secure Negotiations among Multiple Agents (RRS 2005 to 2007)\, Agent-based Complex Automated Negotiations (ACAN2008 to 2011)\, Program Committee member of the ACM Conference on Electronic Commerce(ACM-EC2007)\, the Program Chair of the International Workshop on the Pacific Rim International Workshop on Electronic Commerce (PRIWEC2006)\, the Program Committee of the International Conference of Industrial & Engineering Applications of Artificial Intelligence & Expert Systems (IEA/AIE 2003 to 2008)\, the Program Committee of International Workshop on Data Engineering Issues in E-Commerce (DEEC 2005 to 2006)\, and other Committees. His main research interestsinclude multi-agent systems\, intelligent agents\, group decision support systems\, agent-mediated electronic commerce\, and softwareengineering on offshoring.
URL:https://www.cecs.uci.edu/event/multi-agent-automated-negotiation-and-its-application-to-collective-collaboration-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110210T150000
DTEND;TZID=America/Los_Angeles:20110210T160000
DTSTAMP:20231011T182452Z
CREATED:20231011T182452Z
LAST-MODIFIED:20231011T182452Z
UID:14266-1297350000-1297353600@www.cecs.uci.edu
SUMMARY:Worst Case Execution Time Estimation
DESCRIPTION:Worst Case Execution Time Estimation\n\n\n\n\nSpeaker\n\n\nDr. Y.N. Srikant\,\nDepartment of Computer Science and Automation\nIndian Institute of Science\nBangalore\, India\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFebruary 10\, 2011\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nEstimation of worst case execution time of programs is extremely important in the context of real time systems where the correctness of the system depends not only on the computations performed\, but also on the timing of such computations. For task scheduling on such systems\, it is necessary to know whether the task can execute to completion within a predetermined time interval. Thus\, given a program and a target architecture\, the WCET problem is to estimate a bound on the maximum execution time taken by the program for any input data set.  \nWCET estimation is usually required to be safe and tight. Static analysis based techniques for WCET estimation use micro-architectural models for the target architecture and abstract interpretation for program analysis. Their results are safe but are not very tight. Measurement based techniques estimate the execution time for basic blocks by actual execution\, and then combine the results using integer linear programming. These results are tighter but not safe. \nIn this talk\, an overview of a probabilistic scheme for WCET estimation\, which is a hybrid of static and measurement based methods is presented. Preliminary results on a novel measurement based technique using program phases will also be presented.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nY.N. Srikant received his B.E in Electronics from Bangalore University\, and M.E and Ph.D in Computer Science from the Computer Science and Automation department of the Indian Institute of Science. He was the recipient of Young Scientist medal of the Indian National Science Academy in 1988. Srikant is currently a Professor in the Department of Computer Science and Automation at the Indian Institute of Science in Bangalore. He was the chair of the CSA department from 2000-05. \nHis area of interest is compiler design. He is the editor of a handbook on advanced compiler design published by CRC Press in 2002 and 2008 (2nd ed.). His most recent research includes compiler and runtime optimizations for reducing energy consumption in embedded systems and performance estimation of programs through program analysis.
URL:https://www.cecs.uci.edu/event/worst-case-execution-time-estimation/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20101025T150000
DTEND;TZID=America/Los_Angeles:20101025T160000
DTSTAMP:20231011T182453Z
CREATED:20231011T182453Z
LAST-MODIFIED:20231011T182453Z
UID:14267-1288018800-1288022400@www.cecs.uci.edu
SUMMARY:Component-Based Design of Embedded Systems
DESCRIPTION:Component-Based Design of Embedded Systems\n  \n\n\n\n\nSpeaker\n\n\nProf. Hermann Kopetz\,\nUniversity of Vienna\, Austria\n\n\n\n\n\n\n\n\n\n\nCECS Hosts\n\n\nKane Kim\, Rainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nCalIT2 Room 3008\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 25 \, 2010\nLecture begins at 10:30 AM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn many engineering disciplines\, large systems are built from prefabricated components with known and validated properties. Components are connected via stable\, understandable\, and standardized interfaces. The system engineer has knowledge about the global properties of the components–as they relate to the system functions– and of the detailed specification of the component interfaces. Knowledge about the internal design and implementation of the components is neither needed\, nor available in many cases. Component-based design refers to a meet-in-the middle design methodology\, where\, starting from a purpose and requirements on one side and a set of available components on the other side a new design is produced that tries to satisfy the requirements by a proper interconnection of available and newly developed components. In this lecture we introduce the recursive component concept and the integration framework of the time- triggered architecture and demonstrate how the component-based design of embedded systems can be realized within this framework\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nHermann Kopetz received his PhD in physics sub auspiciis praesidentis from the University of Vienna\, Austria in 1968. After eight years in Industry he accepted in 1978 an appointment as a Professor for Computer Process Control at the Technical University of West-Berlin\, moving to the Technical University of Vienna in 1992. Kopetz is a full member of the Austrian Academy of Science\, Fellow of the IEEE\, and is a member of the Information Society Advisory Group (ISTAG)\, advising the European Commission in Brussels in the domain of Information Technology since 2008. In June 2007 he received the honorary degree of Dr. honoris causa from the University Paul Sabatier in Toulouse\, France. Kopetz is the chief architect of the Time-Triggered Architecture for dependable Embedded Systems and a co-founder of the company TTTech that has industrialized the time-triggered technology in many reputable projects\, among others in the Boeing 787 Dreamliner and the Audi A8 premium car.
URL:https://www.cecs.uci.edu/event/component-based-design-of-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20101006T150000
DTEND;TZID=America/Los_Angeles:20101006T160000
DTSTAMP:20231011T192748Z
CREATED:20231011T181235Z
LAST-MODIFIED:20231011T192748Z
UID:14253-1286377200-1286380800@www.cecs.uci.edu
SUMMARY:Programming FPGA in C using ROCCC
DESCRIPTION:Programming FPGA in C using ROCCC\n\n\n\n\nPresenters\n\n\nJason Villarreal\, Adrian Park\, Roby Atadero\, and Walid Najjar\n\n\n\n \n\n\n \n\n\n\nCECS Host\n\n\nProfessor Fadi Kurdahi\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nCALit2 3008\, University of California\, Irvine\n\n\n\n \n\n\n \n\n\n\nDate & Time\n\n\nOctober 6\, 2010\nLight refreshments at 9:30am\, Tutorial begins 10:00am\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nROCCC (Riverside Optimizing Compiler for Configurable Computing) is a C to VHDL compilation framework specifically focused on FPGA-based code acceleration. Its focus is on compile time transformations and optimizations aimed at generating an efficient circuit from a loop nest. Its objectives are to maximize parallelism within the constraints of the target device\, optimize clock cycle time by efficient pipelining and minimize the area utilized. Furthermore\, ROCCC relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory. ROCCC 2.0 is a free and open source tool that supports a modular bottom-up approach to the programming of FPGA accelerators\, supporting code reuse at multiple levels while maintaining full compatibility with C. It has been ported to several platforms including Xilinx development boards and the Convey Computers HC-1.
URL:https://www.cecs.uci.edu/event/programming-fpga-in-c-using-roccc/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100803T150000
DTEND;TZID=America/Los_Angeles:20100803T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14268-1280847600-1280851200@www.cecs.uci.edu
SUMMARY:Towards Practical High-Level Synthesis from Large Behavioral Descriptions
DESCRIPTION:Towards Practical High-Level Synthesis from Large Behavioral Descriptions\n\n\n\n\nSpeaker\n\n\nDr. Yuko Hara-Azumi\nNagoya University\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nAugust 3\, 2010\nLecture begins at 3:00PM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDue to the continuously increasing size and complexity of LSIs\, the traditional Register-Transfer Level (RTL) design with Hardware Design Languages (HDLs) is approaching its limit on design productivity. High-level synthesis\, which automatically synthesizes an RTL circuit from a behavioral description\, is expected as a promising solution to improve design productivity. However\, the LSI design has not been completely shifted from the traditional RTL design with HDLs to high-level synthesis yet since the quality of automatically synthesized RTL circuits through high-level synthesis can be inferior to that of human-designed ones\, which is especially serious for large designs.  \nThe goal of my work is to develop practical technologies of “high-level synthesis from large behavioral descriptions”. In this talk\, first\, one of my thesis works\, which revealed some problems in current technologies of high-level synthesis\, is briefly presented. Then\, previous/ongoing works which tackle with the problems are presented.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nYuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. Currently she is a research fellow of the Japan Society for the Promotion and Science at Nagoya University. Also\, she serves as a visiting researcher at Ritsumeikan University and University of California\, Irvine. Her research interests include high-level synthesis and compiler techniques.
URL:https://www.cecs.uci.edu/event/towards-practical-high-level-synthesis-from-large-behavioral-descriptions/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100617T150000
DTEND;TZID=America/Los_Angeles:20100617T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14269-1276786800-1276790400@www.cecs.uci.edu
SUMMARY:Location and Time in Sensor Networks
DESCRIPTION:Automatic Design Space Exploration for Chip Multi-Processors\n\n\n\n\nSpeaker\n\n\nDr. Cristina Silvano\,\nPolitecnico di Milano\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nAlex Veidenbaum\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 17 \, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nGiven the increasing complexity of Chip Multi-Processors\, a wide range of architecture parameters (number of processors\, processor issue width\, L1 & L2 cache size\, etc.) must be tuned to find the best trade-off in terms of multiple metrics (energy\, delay\, bandwidth\, area\, etc.). Multi-Objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. Automatic Design Space Exploration is necessary to support systematically the exploration and the quantitative comparison in terms of multiple objectives. This talk addresses these problems by presenting MULTICUBE Explorer\, an open-source tool to support an automatic and fast optimization of configurable system-on-chip architectures towards a set of objective functions such as energy and delay. MULTICUBE Explorer provides a set of innovative sampling and optimization techniques to help finding the multi-objective Pareto points. Design of Experiments techniques are used to identify the experimentation plan where the set of tunable design parameters can vary. Response Surface Modeling techniques are used to obtain a response surface of the system behavior based on the set of data generated by DoE. MULTICUBE Explorer can also provide some support for run-time management of system resources.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nShe is an Associate Professor in Computer Engineering at Politecnico di Milano (Italy). Her primary research interests are in the area of Computer Architectures and Electronic Design Automation\, with particular emphasis on design space exploration techniques and low- power design techniques for multi-processor systems-on-chip. She is co-author of more than seventy scientific papers on international journals and conferences\, collecting one best paper award. She was co-author of the book: Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems\, published by Kluwer Academic Publisher (2003). She also holds some international patents. She participated to a number of national and international research projects. She is currently the European Coordinator of the on-going project FP7-MULTICUBE-216693 “Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications” (Jan. 2008 – June 2010). >From 2010\, she is also the Project Coordinator of the project FP7-2PARMA-248716 on “Parallel paradigms and run-time management techniques for many-core architectures.”
URL:https://www.cecs.uci.edu/event/location-and-time-in-sensor-networks/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100615T150000
DTEND;TZID=America/Los_Angeles:20100615T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14270-1276614000-1276617600@www.cecs.uci.edu
SUMMARY:Secure VLSI Test Methods
DESCRIPTION:Secure VLSI Test Methods\n\n\n\n\nSpeaker\n\n\nDr. Ramesh Karri\nPolytechnic University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nIan Harris\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 15 \, 2010\nRefreshments at 10:30 am; Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDesign for Test (DFT) techniques improve access to the internal state of hardware either by improving control of internal nodes from the primary inputs or by improving observation of values on internal nodes at the primary outputs or both. On the other hand\, from a security perspective\, hardware should minimize controllability and observability of the internal state to a minimum. In this talk we will discuss our research on secure DFT architectures that reconcile Testability and Security.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nRamesh Karri is an Associate Professor in the Department of Electrical and Computer Engineering. Prof. Karri’s research interests are in the areas of secure hardware design\, computer-aided secure hardware design\, high-speed architectures for network protocols and encryption\, and computer-aided design of fault-tolerant nanoscale systems. \nProf. Karri is the recipient of an NSF CAREER award\, an Alexander Humboldt Fellowship and several grants including from the National Science Foundation\, the Air Force Research Labs and Army. Most recently\, Prof. Karri has been a co-PI with Program Director Nasir Memon on the just-awarded $2.124 million NSF grant from the National Science Foundation research and teaching of security and privacy issues on the Internet and other critical information infrastructure and is a founding member of the Center for Research in Interdisciplinary Studies in Security and Privacy at NYU. \nProfessor Karri received his MS in Computer Engineering at the University of California (1992)\, and his PhD in Computer Science also at the University of California (1993).
URL:https://www.cecs.uci.edu/event/secure-vlsi-test-methods/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100611T150000
DTEND;TZID=America/Los_Angeles:20100611T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14271-1276268400-1276272000@www.cecs.uci.edu
SUMMARY:The Inevitable Use of High Level Synthesis in Complex SoC Designs
DESCRIPTION:The Inevitable Use of High Level Synthesis in Complex SoC Designs\n\n\n\n\nSpeaker\n\n\nDr. Benjamin Schaefer\,\nNEC Research Lab\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 413\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 11 \, 2010\nLecture begins at 11:00 am (Lecture Cancelled)\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nESL is becoming main stream when modeling complete SoCs in order to evaluate different architectural trade-offs and get some early performance estimates. These models are mainly described in SystemC. The central question that remains is if these models can ultimately be synthesized in order to further reduce the development cycle or if these models need to be manually described and integrated at the RT-level. This talk addresses how complete SoCs can be fully designed in C.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nBenjamin received his Ph.D from the University of Birmingham\, UK in 2003 \, where he investigated the acceleration of numerical intensive algorithms on reconfigurable computing platforms. He then moved to UCLA as a postdoctoral researcher working in the area of High Level synthesis and then moved to Seoul National University\, Korea where he worked on thermal estimation and reduction issues in VLSI circuits. Since 2007 he is with NEC’s Central Research Laboratory in Japan\, working on System and High Level Synthesis.
URL:https://www.cecs.uci.edu/event/the-inevitable-use-of-high-level-synthesis-in-complex-soc-designs/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100527T150000
DTEND;TZID=America/Los_Angeles:20100527T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14272-1274972400-1274976000@www.cecs.uci.edu
SUMMARY:Location and Time in Sensor Networks
DESCRIPTION:Location and Time In Sensor Networks\n\n\n\n\nSpeaker\n\n\nDr. Ryo Sugihara\,\nUniversity of California\, San Diego\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 30\, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk I will present two of my projects related to location and time in sensor networks. First is location-based job scheduling. Specifically I will talk about the use of controlled mobility for data collection in sensor networks. As controllable mobile nodes (called “data mules”) travel across the sensor field to bring the data back to the base station\, how the data mules choose their paths\, change speed\, and schedule communication are important problems for minimizing the data collection latency. We formulated the problem as a scheduling problem called data mule scheduling (DMS) problem. This is an interesting extension to traditional job scheduling problem: each job has release and deadline on the location axis instead of the time axis. We have analyzed the complexity for several different mobility models and designed optimal and approximate algorithms. I will also talk about the similarity with dynamic voltage scaling problem.  \nIn the second part\, I will introduce our recent work on clock synchronization protocol in sensor networks. Although clock synchronization has been studied for a long time in sensor networks as well as in distributed systems\, recent synchronization protocols for sensor networks have been mostly focused on achieving good average accuracy. While these protocols achieve microsecond-order accuracy\, many of them do not have any guarantees on the worst case. However\, as sensor networks become used more widely or incorporated into larger systems in the form of CPS (cyber-physical system)\, the notion of guaranteed performance increases importance much more than ever. To deal with this\, our work is focused on providing guaranteed accuracy in clock synchronization. Based on observation of the characteristics of crystal oscillators on sensor nodes\, our synchronization protocol achieves much tighter accuracy guarantee than the classical methods (sometimes called “interval-based clock synchronization algorithms”) can provide.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nRyo Sugihara received the BE and ME degrees in mechanical engineering from the University of Tokyo\, Japan\, in 1997 and 1999\, respectively. He received the PhD degree in computer science in 2009 from the University of California\, San Diego\, where he is currently working as a postdoctoral researcher. Previously\, he worked at the IBM Tokyo Research Laboratory\, where he was engaged in research and development on video digital watermarking and large-scale video streaming. His current research interests include sensor networks and mobile ad hoc networks. He was a recipient of the Best Paper Award of the Systems track at IEEE DCOSS 2008.
URL:https://www.cecs.uci.edu/event/location-and-time-in-sensor-networks-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100430T150000
DTEND;TZID=America/Los_Angeles:20100430T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14273-1272639600-1272643200@www.cecs.uci.edu
SUMMARY:Customizable Domain-Specific Computing
DESCRIPTION:Customizable Domain-Specific Computing\n\n\n\n\nSpeaker\n\n\nDr. Jason Cong\,\nCenter for Domain-Specific Computing\,\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 6011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 30\, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n\n \nIn order to meet ever-increasing computing needs and overcome power density limitations\, the computing industry has halted simple processor frequency scaling and entered the era of parallelization\, with tens to hundreds of computing cores integrated in a single processor\, and hundreds to thousands of computing servers connected in a warehouse-scale data center. However\, such highly parallel\, general-purpose computing systems still face serious challenges in terms of performance\, power\, heat dissipation\, space\, and cost. We believe that we need to look beyond parallelization and focus on domain-specific customization as the next opportunity to bring orders-of-magnitude power-performance efficiency improvement to important classes of applications. This challenge requires a great deal of innovation in architecture\, compilation\, and runtime system design\, and offers many exciting and challenging research opportunities. \nI shall talk about the ongoing work at the newly established Center for Domain-Specific Computing supported by the NSF Expeditions in Computing award. Our proposed domain-specific customizable computing platform includes: \n1) a wide range of customizable computing elements\, from heterogeneous fixed cores to coarse-grain customizable cores\, and to fine-grain field-programmable circuit fabrics; \n2) customizable high-performance radio frequency interconnects; \n3) highly automated compilation tools and runtime management software systems for application development; \nand \n4) a general\, reusable methodology for customizable computing applicable across different domains. \nBy combining these critical capabilities\, we aim to provide a supercomputer-in-a-box that is customized to a particular application domain with much higher performance/power efficiency. We choose application domains in healthcare to demonstrate our approach.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nShort biography available at Dr. Jason Cong’s Web Site.
URL:https://www.cecs.uci.edu/event/customizable-domain-specific-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100422T150000
DTEND;TZID=America/Los_Angeles:20100422T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14274-1271948400-1271952000@www.cecs.uci.edu
SUMMARY:Wireless Health Systems
DESCRIPTION:Wireless Health Systems\n\n\n\n\nSpeaker\n\n\nDr. Ani Nehapetian\,\nUniversity of California\, Los Angeles\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 22\, 2010\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOne of the most urgent and daunting tasks of our time is providing quality health care in the face of increasing incidence of disease\, aging populations\, and soaring costs. The proliferation of lightweight and heterogeneous embedded systems holds the promise of revolutionizing the accessibility\, quality\, financing\, and delivery of healthcare in much the same way that low-cost cellular phone technology dramatically changed telecommunications worldwide. However\, significant research challenges must be addressed before this wireless health model can reach its full potential.  \nThe talk will include an overview of various devices and systems under development at the UCLA Wireless Health Institute. Additionally\, it will consider important research issues\, including security and and data management.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Ani Nahapetian is currently a researcher with the UCLA Wireless Health Institute and a visiting assistant professor with the UCLA Computer Science department. She received her Ph.D and M.S. in Computer Science\, and B.S. in Computer Science and Engineering\, all from UCLA. Her research interests include embedded systems with health applications\, algorithm design for reconfigurable and low-power embedded systems\, and hardware security.
URL:https://www.cecs.uci.edu/event/wireless-health-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091214T150000
DTEND;TZID=America/Los_Angeles:20091214T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14246-1260802800-1260806400@www.cecs.uci.edu
SUMMARY:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases
DESCRIPTION:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases\n\n\n\n\nSpeaker\n\n\nDr. Masato Motomura\,\nSystem IP Core Research Laboratories\, NEC Corporation\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 14\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nStream Transpose (STP) Engine is a programmable HW core to accelerate stream processing in modern system LSIs. It is composed of an array of numerous numbers of processing and memory elements as well as an intelligent data streaming HW mechanism. Key differentiation from other many-core type parallel architectures lies in its programming model: i.e.\, a design tool based on high-level HW synthesis technology compiles a C source code into a set of pseudo HW configurations which are spatially and temporally mapped onto the array. The STP engine is productized in 90nm-generation system LSIs\, and is targeted for wider-range use in forthcoming generations beyond 40nm.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Motomura received EE doctorial degree from Kyoto University in 1996. He has been engaged in research of various LSI architectures\, such as functional memories\, parallel processors\, and reconfigurable arrays in NEC research laboratories since 1987. From 2002 to 2009\, he led technology and business development of STP Engine in NEC Electronics. He was also the winner of 1992 IEEE JSSC Best Paper Award.
URL:https://www.cecs.uci.edu/event/stp-engine-a-c-based-programmable-hw-core-featuring-massively-parallel-and-reconfigurable-pe-array-its-architecture-tool-and-real-system-usecases/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091118T150000
DTEND;TZID=America/Los_Angeles:20091118T160000
DTSTAMP:20231011T182854Z
CREATED:20231011T182854Z
LAST-MODIFIED:20231011T182854Z
UID:14275-1258556400-1258560000@www.cecs.uci.edu
SUMMARY:Concurrency and Communication: Lessons from the SHIM Project
DESCRIPTION:Concurrency and Communication: Lessons from the SHIM Project\n\n\n\n\nSpeaker\n\n\nDr. Stephen A. Edwards\,\nColumbia University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Tony Givargis\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 18\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDescribing parallel hardware and software is difficult\, especially in an embedded setting. Five years ago\, we started the SHIM project to address this challenge by developing a programming language for hardware/software systems. The resulting language describes asynchronously running processes that has the useful property of scheduling-independence: the I/O of a SHIM program is not affected by any scheduling choices. I will present a history of the SHIM project with a focus on the key things we have learned along the way.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nStephen A. Edwards received the B.S. degree in Electrical Engineering from the California Institute of Technology in 1992\, and the M.S. and Ph.D degrees\, also in Electrical Engineering\, from the University of California\, Berkeley in 1994 and 1997 respectively. He is currently an associate professor in the Computer Science Department of Columbia University in New York\, which he joined in 2001 after a three-year stint with Synopsys\, Inc.\, in Mountain View\, California. His research interests include embedded system design\, domain-specific languages\, and compilers.
URL:https://www.cecs.uci.edu/event/concurrency-and-communication-lessons-from-the-shim-project/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091117T150000
DTEND;TZID=America/Los_Angeles:20091117T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14276-1258470000-1258473600@www.cecs.uci.edu
SUMMARY:Advanced SoC Architectures for Multiple DRAMs (Enabled by 3D Die Stacking)
DESCRIPTION:Advanced SoC Architectures for Multiple DRAMs\n(Enabled by 3D Die Stacking)\n\n\n\n\nSpeaker\n\n\nDr. Sungjoo Yoo\nPOSTECH\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 17 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe performance of data-intensive applications is mostly determined by the bandwidth and latency of off-chip DRAM. In order to improve the bandwidth and latency characteristics\, multiple memory-based solutions (enabled by 3D stacking of memory dies on top of LSI dies) are being actively investigated. With multiple DRAMs\, we come to face new architectural problems\, especially\, in memory controllers and on-chip network. In this talk\, we will discuss the architectural problems caused by multiple memories and present our solutions (request parallelizer\, in-network reorder buffer\, etc.) to address the problems. We will summarize this talk with some speculations on future SoC architectures with multiple memories.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nDr. Sungjoo Yoo received B.S.\, M.S.\, and Ph.D. at Seoul National University\, Korea\, in 1992\, 1995\, and 2000\, respectively. He worked at TIMA laboratory\, Grenoble\, France from 2000 to 2004 and worked as principal engineer at System LSI Division\, Samsung Electronics from 2004 to 2008. At Samsung\, he led a team which developed AMBA3-based on-chip bus architectures for mobile SoCs\, and low power design solutions such as dynamic voltage and frequency scaling (DVFS) algorithms and performed hardware/software co-optimization of solid state disk products. He joined POSTECH (Pohang university of science and technology) in August 2008. His current research interests include memory hierarchy and network-on-chip for many-core SoC\, low power design based on runtime-distribution and temperature-aware DVFS\, and power efficiency/performance/reliability improvement of solid state disk.
URL:https://www.cecs.uci.edu/event/advanced-soc-architectures-for-multiple-drams-enabled-by-3d-die-stacking/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091116T150000
DTEND;TZID=America/Los_Angeles:20091116T160000
DTSTAMP:20231011T182855Z
CREATED:20231011T182855Z
LAST-MODIFIED:20231011T182855Z
UID:14277-1258383600-1258387200@www.cecs.uci.edu
SUMMARY:Energy Efficient Computing
DESCRIPTION:Energy Efficient Computing\n\n\n\n\nSpeaker\n\n\nProf. Tajana Simunic Rosing\,\nDepartment of CSE\,\nUC San Diego\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Daniel Gajski\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 16 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00 pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn this talk\, we will present the algorithms we have developed at UCSD for lowering the energy consumption in computing systems. We derived optimal power management strategies for stationary workloads that have been implemented both in HW and SW. Run-time adaptation can be done via an online learning algorithm that selects among a set of policies. We generalized the algorithm to include thermal management since we found that minimizing the power consumption does not necessarily reduce the overall energy costs. To reduce the performance costs typically associated with state of the art thermal management techniques\, we also developed a new set of proactive management policies. The experimental results using real datacenter workloads on an actual multicore system show that our proactive technique is able to dramatically reduce the adverse effects of temperature by over 60%. Most recently we have shown that symbiotic scheduling of workloads in virtualized environments can lead to average 15% energy savings with 20% performance benefit in high utilization scenarios.We will also present some of the recent work that address the energy savings in battery powered systems\, as demonstrated in a new kind of “citizen infrastructure”\, an end-to-end health and environmental information system with near real-time data streams and feedback loops from the system to the sensing\, processing\, and actuation infrastructure. We have developed adaptive algorithms to tradeoff accuracy of computation versus the available energy for such systems\, while taking into account the energy harvesting capabilities.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nTajana Simunic Rosing is currently an Assistant Professor in Computer Science Department at UCSD\, a director of System Energy Efficiency Lab at UCSD and a head of the Energy efficient datacenter thrust as a part of the MuSyC center. Her research interests are energy efficient computing\, embedded and wireless systems. She finished her PhD at Stanford University. Prior to pursuing the PhD\, she worked as a Senior Design Engineer at Altera Corporation. She has served at a number of Technical Paper Committees\, and is currently an Associate Editor of IEEE Transactions on Mobile Computing.
URL:https://www.cecs.uci.edu/event/energy-efficient-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091112T150000
DTEND;TZID=America/Los_Angeles:20091112T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T180836Z
LAST-MODIFIED:20231011T192457Z
UID:14247-1258038000-1258041600@www.cecs.uci.edu
SUMMARY:NEC's Manycore Platforms for Low-Power Embedded System
DESCRIPTION:NEC’s Manycore Platforms for Low-Power Embedded System\n\n\n\n\nSpeaker\n\n\nNaoki Nishi\nGM\, NEC Central Research Labs\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nNovember 12\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAfter short introduction of NEC’s R&D vision related to future ICT system handling real world in real time\, two examples of NEC’s manycore research activities will be presented. First example is an in-vehicle vision processor IMAPCAR-2 which supports SIMD-MIMD morphing\, and the second is a fine grain manycore architecture called STP (Stream TransPoser) engine which is a kind of dynamically reconfigurable hardware with C level language SDK support.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nNaoki Nishi is a general manager at central research labs.\, NEC. He jointed NEC in 1984\, where he worked in research on micro-architectures and LSI development of the NEC SX vector supercomputer\, After the development of CMOS vector supercomputer SX-4 in 1996\, he has been conducting research on high-performance\, low-power multi-/many-cores. Naoki Nishi received his B.E. and M.E. degrees in system engineering from Hiroshima University\, Japan.
URL:https://www.cecs.uci.edu/event/necs-manycore-platforms-for-low-power-embedded-system/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091022T150000
DTEND;TZID=America/Los_Angeles:20091022T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192031Z
UID:14248-1256223600-1256227200@www.cecs.uci.edu
SUMMARY:A Virtualization-Based Software Architecture for Real-Time Embedded Systems
DESCRIPTION:A Virtualization-Based Software Architecture for Real-Time Embedded Systems\n\n\n\n\nSpeaker\n\n\nDr. Sung-Soo Lim\nAssistant Professor\,\nSchool of Computer Science\,\nKookmin University\,\nSeoul\, Korea\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 22 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThis talk introduces an on-going work in Embedded Systems Laboratory\, Kookmin University to build next generation software architecture for mobile phones cooperating with Samsung Electronics. Future mobile phones need to accommodate both legacy applications and hard real-time communication protocols regardless of the underlying hardware organization. Such support for flexibility and reconfigurability should be accompanied with guarantee of reliability and security.  \nWe design and implement a light-weight hypervisor based on L4 microkernel for real-time embedded systems accommodating both general-purpose and hard real-time operating systems. The virtualization-based software architecture based on our hypervisor could have the reliability with zero-down feature and safety during dynamic software upgrade. We built a prototype smartphone platform running both Linux and uCOS-II on a single ARM11 core using the proposed software architecture. The structure and core techniques used in our software architecture will be introduced in the talk.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nSung-Soo Lim received BS\, MS\, and PhD degrees in Computer Engineering from Seoul National University in 1993\, 1995\, and 2002\, respectively. From 2000 to 2001\, he was a visiting researcher in University of Illinois at Urbana-Champaign. From 2001 to 2004\, he was the CTO of PalmPalm Technology\, Inc. in Korea (a smartphone development company). He is currently an assistant professor in School of Computer Science\, Kookmin University. His research area includes real-time operating systems\, real-time performance analysis\, low-power technology\, and mobile phone architecture.
URL:https://www.cecs.uci.edu/event/a-virtualization-based-software-architecture-for-real-time-embedded-systems/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091019T150000
DTEND;TZID=America/Los_Angeles:20091019T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14249-1255964400-1255968000@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 19 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091009T150000
DTEND;TZID=America/Los_Angeles:20091009T160000
DTSTAMP:20231011T192654Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192654Z
UID:14250-1255100400-1255104000@www.cecs.uci.edu
SUMMARY:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA
DESCRIPTION:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA\n\n\n\n\nSpeaker\n\n\nProf. Lei He\nElectrical Engineering Department\,\nUCLA\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Eli Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 9\, 2009\nRefreshments at 10:30am; Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAs devices become smaller\, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired\, especially if no extra area\, power and delay and little change of the existing design flow are introduced. Using FPGA and internet router as a testbed\, this talk first presents fault tolerance techniques applying (1) logic don’t care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both increase MTTF by 2X with little or no overhead. Particularly\, IPR does not change circuit placement and routing\, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. Finally\, I will briefly discuss my ongoing research on cyber-physical systems involving renewal energy storage and environment/water monitoring.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Lei He is an associate professor at electrical engineering department\, UCLA\, and was a faculty member at University of Wisconsin\, Madison between 1999 and 2001. He also held visiting or consulting positions with Intel\, Hewlett-Package\, Cadence and Synopsys\, was a technical advisory board member for Rio Design Automation\, and Apache Design Solutions\, and is a guest professor at Fudan University (China) and China National Laboratory for Optoelectronics.  \nHis research interests include electronic design automation\, VLSI circuits and systems\, and cyber-physical systems. He has published one book and over 200 technical papers and has been a technical program committee member for a number of conferences including Design Automation Conference\, International Conference on Computer-Aided Design\, International Symposium on Low Power Electronics and Design\, International Symposium on Field Programmable Gate Array\, and International Symposium on Physical Design. Dr. He obtained Ph.D. degree in computer science from UCLA in 1999. He was granted National Science Foundation CAREER award in 2000\, UCLA Chancellor’s faculty career development award in 2003\, IBM Faculty Award in 2003\, Northrop Grumman Excellence in Teaching award in 2005\, best paper award at the 2006 International Symposium on Physical Design\, and multiple best paper nominations at Design Automation Conference and International Conference on Computer-Aided Design.
URL:https://www.cecs.uci.edu/event/power-efficient-and-fault-tolerant-circuits-and-systems-using-commodity-fpga/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090805T150000
DTEND;TZID=America/Los_Angeles:20090805T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14279-1249484400-1249488000@www.cecs.uci.edu
SUMMARY:Portable Direct Methanol Fuel Cell System for Green Computing
DESCRIPTION:Portable Direct Methanol Fuel Cell System for Green Computing\n\n\n\n\nSpeaker\n\n\nDr. Naehyuck Chang\nSeoul National University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Pai Chou\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nCalIT2 Room 3008\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nAugust 5 \, 2009\nRefreshments at 10:00 am\, Lecture begins at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe introduce a hybrid portable direct methanol fuel cell (DMFC) system\nwhich includes a li-ion battery. We demonstrate a hybrid operation of\nthe DMFC stack and the li-ion battery to maintain a constant stack\noutput current regardless of the load current to maximize the\nperformance. We describe the balance of plant (BOP) control system\,\nincluding a 32-bit microprocessor\, and electronics to drive motors\,\nactuators and sensors for reliable operation and protection of a DMFC\nsystem. The dynamics of BOP control is taken into account to design\nmultiple cascaded feedback control loops. We demonstrate robust\noperation of a DMFC system together with introduction of a DMFC system\ndesign. This talk includes a working prototype system demonstration of a\ncomplete DMFC and battery hybrid power source.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nNaehyuck Chang received his BS\, MS and PhD degrees all from Seoul National University\, in 1989\, 1992 and 1996\, respectively. He was a research associate at Dept. of Electrical Engineering and Computer Science at University of Michigan in Ann Arbor in 1997. He joined Seoul National University in Dept. of Computer Science and Engineering in 1997 as a faculty member and now is an Associate Professor in Dept. of Electrical Engineering and Computer Science. He was also a Visiting Associate Professor at Arizona State University in 2005. He has been with Sindoricoh\, Co. Ltd.\, as a Technical Advisor since 2001. He has published more than 70 technical papers in low-power and embedded systems area.
URL:https://www.cecs.uci.edu/event/portable-direct-methanol-fuel-cell-system-for-green-computing/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090722T150000
DTEND;TZID=America/Los_Angeles:20090722T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14281-1248274800-1248278400@www.cecs.uci.edu
SUMMARY:Compiler-enabled Power-efficient Register File Protection
DESCRIPTION:Compiler-enabled Power-efficient Register File Protection\n\n\n\n\nSpeaker\n\n\nDr. Jongeun Lee\nEECS\, Ulsan National Institute of Science and Technology\,Korea\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJuly 22\, 2009\nRefreshments at 10:30 am\, Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRegister file (RF) is extremely vulnerable to soft errors\, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor\, but also since it is one of the hottest blocks on the chip\, and therefore adding any extra circuitry to it is not desirable. Software approaches would be ideal in this case\, but previous approaches that are based on program duplication have very significant runtime overheads\, and others based on instruction scheduling are only moderately effective due to local scope.  \nThis talk will be about how compiler alone and in conjunction with microarchitecture can power-efficiently protect the RF. What we have observed is that a significant portion of the RF vulnerability is contributed by long lifetime variables. Protecting only these can result in power-efficient RF protection. Thus the task of the compiler is to identify program variables that have long lifetimes and protect them. Our experiments demonstrate pure compiler techniques can reduce the vulnerability of the RF by 33-37% on average and up to 66%\, with a small (2%) runtime overhead. As compared to hardware protection mechanisms\, compiler analysis can achieve the same level of protection but at up to 75% lesser RF energy consumption.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nJongeun Lee received a BS and an MS in Electrical Engineering and a PhD in Electrical Engineering and Computer Science all from Seoul National University. Previously he was with Samsung SoC R&D Center in Korea\, and is currently a postdoctoral associate at Arizona State University\, working with Dr. Aviral Shrivastava. He is joining Ulsan National Institute of Science and Technology\, Korea\, as an Assistant Professor of EECS. His research interests include configurable/reconfigurable processor architecture design\, compilation for energy and reliability\, and compilation for multicore processors and GPUs.
URL:https://www.cecs.uci.edu/event/compiler-enabled-power-efficient-register-file-protection/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090504T150000
DTEND;TZID=America/Los_Angeles:20090504T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14251-1241449200-1241452800@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n  \n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 4\, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm (Lecture Cancelled)\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design-2/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090309T150000
DTEND;TZID=America/Los_Angeles:20090309T160000
DTSTAMP:20231011T192457Z
CREATED:20231011T181037Z
LAST-MODIFIED:20231011T192457Z
UID:14252-1236610800-1236614400@www.cecs.uci.edu
SUMMARY:Nonlinear Symbolic Program Analysis for Increased Parallelization
DESCRIPTION:Nonlinear Symbolic Program Analysis for Increased Parallelization\n\n\n\n\nSpeaker\n\n\nProfessor Kleanthis Psarris \nDepartment of Computer Science\nThe University of Texas at San Antonio\, TX\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Nicolau\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 9\, 2009\nRefreshments at 2:30 pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHigh end parallel and multi-core processors rely on compilers to perform the necessary optimizations and exploit concurrency in order to achieve higher performance. However\, source code for high performance computers is extremely complex to analyze and optimize. In particular\, program analysis techniques often do not take into account complex expressions during the data dependence analysis phase. Most data dependence tests are only able to analyze linear expressions\, even though non-linear expressions occur very often in practice. Therefore\, considerable amounts of potential parallelism remain unexploited. In this talk we propose new data dependence analysis techniques to handle such complex instances of the dependence problem and increase program parallelization. Our method is based on a set of polynomial time techniques that can prove or disprove dependences in source codes with non-linear and symbolic expressions\, complex loop bounds\, arrays with coupled subscripts\, and if-statement constraints. In addition our algorithm can produce accurate and complete direction vector information\, enabling the compiler to apply further transformations. To validate our method we performed an experimental evaluation and comparison against the I-Test\, the Omega test and the Range test in the Perfect and SPEC benchmarks. The experimental results indicate that our dependence analysis tool is accurate\, efficient and more effective in program parallelization than the other dependence tests. The improved parallelization results into higher speedups and better program execution performance in several benchmarks.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nKleanthis Psarris is Professor and Chair of the Department of Computer Science at the University of Texas at San Antonio. His research interests are in the areas of Parallel and Distributed Systems\, Compilers and Programming Languages. He received his B.S. degree in Mathematics from the National University of Athens\, Greece in 1984. He received his M.S. degree in Computer Science in 1987\, his M.Eng. degree in Electrical Engineering in 1989 and his Ph.D. degree in Computer Science in 1991\, all from Stevens Institute of Technology in Hoboken\, New Jersey. He has published extensively in top journals and conferences in the field and his research has been funded by the National Science Foundation and Department of Defense agencies. He is an Editor of the Parallel Computing journal. He has served on the Program Committees of several international conferences including the ACM International Conference on Supercomputing (ICS) in 1995\, 2000\, 2006 and 2008\, the IEEE International Conference on High Performance Computing and Communications (HPCC) in 2008 and 2009\, and the ACM Symposium on Applied Computing (SAC) in 2003\, 2004\, 2005 and 2006.
URL:https://www.cecs.uci.edu/event/nonlinear-symbolic-program-analysis-for-increased-parallelization/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081119T150000
DTEND;TZID=America/Los_Angeles:20081119T160000
DTSTAMP:20231011T183051Z
CREATED:20231011T183051Z
LAST-MODIFIED:20231011T183051Z
UID:14282-1227106800-1227110400@www.cecs.uci.edu
SUMMARY:My Work and My Life
DESCRIPTION:by Prof. Leonard KleinrockDepartment of Computer Science\nUniversity of California\, Los Angeles\nMcDonnell Douglas Auditorium\nDistinguished Lecture\, November 19\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/my-work-and-my-life/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20081104T150000
DTEND;TZID=America/Los_Angeles:20081104T160000
DTSTAMP:20231011T192254Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192254Z
UID:14243-1225810800-1225814400@www.cecs.uci.edu
SUMMARY:Geppeto*: Consumer’s Approach to Programming
DESCRIPTION:Prof. Sinisa Srbljic\, School of Electrical Engineering and Computing\, University of Zagreb\, CroatiaNovember 4\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/geppeto-consumers-approach-to-programming/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080613T150000
DTEND;TZID=America/Los_Angeles:20080613T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14244-1213369200-1213372800@www.cecs.uci.edu
SUMMARY:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models
DESCRIPTION:SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models\n\n\n\n\nSpeaker\n\n\nDr. Christian Haubelt\nUniversity of Erlangen-Nuremberg\, Germany\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Tower\, Room 331\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 13 \, 2008\nTalk begins 11:00am\nRefreshments at 10:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\n80% of all design decisions are made in the first 20% of the design time. Thus\, a substantiated knowledge about possible solutions is mandatory in early design phases in order to design high quality products. SystemCoDesigner is a software tool for automatic design space exploration at the electronic system level and for platform-based prototyping of hardware/software systems. By exploring the design space\, a designer becomes more confident in decisions to be done. Starting from a behavioral SystemC description different solutions are generated automatically by using software synthesis techniques and Forte Design Systems’ Cynthesizer for behavioral hardware synthesis. In order to allow such a degree of automation\, SystemCoDesigner requires the behavioral SystemC model to be representable in a well-defined Model of Computation\, called FunState. As a case study\, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput\, ranging from software only solutions up to pure hardware implementations which reach real-time performance for QCIF streams on a 50MHz FPGA. In this talk\, the SystemCoDesigner overall design flow\, the FunState Model of Computation\, and some automatic transformation are presented using the Motion-JPEG case study.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nChristian Haubelt received his diploma degree in Electrical Engineering from the University of Paderborn\, Germany\, in 2001. He received his Ph.D. in Computer Science from the University of Erlangen-Nuremberg\, Germany\, in 2005. Since 2004\, he is head of the System-Level Design Automation Group at the Chair of Hardware/Software Co-Design\, University of Erlangen-Nuremberg\, Germany. Dr. Haubelt’s research interests include electronic system level design\, system level design automation\, and multi-objective optimization.\n\n\n\n\n\n\n\n\n\n\nWeb Site\n\n\nhttp://www12.informatik.uni-erlangen.de/people/haubelt/
URL:https://www.cecs.uci.edu/event/systemcodesigner-automatic-design-space-exploration-and-rapid-prototyping-from-behavioral-models/
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080429T150000
DTEND;TZID=America/Los_Angeles:20080429T160000
DTSTAMP:20231011T183251Z
CREATED:20231011T183251Z
LAST-MODIFIED:20231011T183251Z
UID:14283-1209481200-1209484800@www.cecs.uci.edu
SUMMARY:Hardware-Accelerated Formal Verification
DESCRIPTION:by Prof. Masahiro FujitaVLSI Design and Education Center\nUniversity of Tokyo\, Tokyo\, Japan\nMcDonnell Douglas Auditorium\, University of California\, Irvine\nDistinguished Lecture\, April 29\, 2008\nAbstract
URL:https://www.cecs.uci.edu/event/hardware-accelerated-formal-verification/
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR