BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CECS
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20220313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20221106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20230312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20231105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20240310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20241103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20230926T140000
DTEND;TZID=America/Los_Angeles:20230926T150000
DTSTAMP:20241014T182326Z
CREATED:20231010T222422Z
LAST-MODIFIED:20241014T182326Z
UID:13934-1695736800-1695740400@www.cecs.uci.edu
SUMMARY:Pareto Exploration Methodology for Future Logic Technology Options in Domain-Specific Processors
DESCRIPTION:Speaker: Dr. Francky Catthoor \nDate and Time: Tuesday\, September 26th\, 2:00 pm \nLocation: EH 2430 \nAbstract:   \nScaling of Si-CMOS based logic processor circuits is hitting limits on application-level performance (throughput and latency)\, dynamic and leakage power\, and even cost characteristics. For that reason\, several researchers have started to study alternatives based on so-called beyond CMOS devices. Many emerging devices have been studied in the last decade\, especially in academia. And some of these looks promising for specific figures of-merit\, like only dynamic power (but not energy)\, only leakage (but not dynamic power) and so on. Hence\, they are almost never simultaneously improving several axes (the desirable figures-of-merit) in the Pareto trade-off space. And as a result\, they rarely improve the true Pareto front in that space. A need exists to better compare potential options in a systematic way\, with emphasis on their system-level impact\, and as much as possible in a future-proof way\, including the link to the processor architecture design and hence to the overall processing platform. In this talk\, a systematic approach will be advocated to characterize these options in a multi-dimensional Pareto exploration space\, and a few interesting directions will be positioned in this space to highlight the potential of this approach. The main architecture context will be domain-specific processor instances. \nBiography: \nFrancky Catthoor received a Ph.D. in EE from the Katholieke Univ. Leuven\, Belgium in 1987. Between 1987 and 2000\, he has headed several research domains in the area of synthesis techniques and architectural methodologies. Since 2000 he is strongly involved in other activities at IMEC including deep submicron technology aspects\, IoT and biomedical platforms\, and smart photovoltaic modules\, all at IMEC Leuven\, Belgium. Currently\, he is an IMEC fellow. He is also a part-time full professor at the EE department of the KULeuven. He has been associate editor for several IEEE and ACM journals and was elected IEEE fellow in 2005. \nHosted By: Prof. Nikil Dutt \nMore Information
URL:https://www.cecs.uci.edu/event/pareto-exploration-methodology-for-future-logic-technology-options-in-domain-specific-processors/
LOCATION:EH 2430\, Engineering Hall\, University of California\, Irvine\, Irvine\, CA\, 92697\, United States
CATEGORIES:Seminars at CECS
ATTACH;FMTTYPE=image/webp:https://cecs.uci.edu/files/2023/09/Francky_Catthoor_1-e1728930196231.webp
END:VEVENT
END:VCALENDAR