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SUMMARY:“Securing Hardware for Designing Trustworthy Systems”
DESCRIPTION:Speaker: Prabhat Mishra\nDate and Time: Tuesday\, August 2\, 2:00 pm \nLocation: DBH 4011 OR Zoom Link \nAbstract: \nSystem-on-Chip (SoC) is the brain behind computing and communication in a wide variety of embedded systems. Reusable hardware Intellectual Property (IP) based SoC design has emerged as a pervasive design practice in the industry to dramatically reduce SoC design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs\, often gathered from untrusted third-party vendors\, severely affects the security and trustworthiness of computing platforms. It is crucial to evaluate the integrity and trustworthiness of third-party IPs for designing trustworthy systems. In this talk\, I will introduce a wide variety of hardware security vulnerabilities\, design-for-security solutions\, and possible attacks and countermeasures. I will briefly describe how the complementary abilities of simulation-based validation\, formal verification as well as side channel analysis can be effectively utilized for comprehensive SoC security and trust validation. \nBiography: \nPrabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering and a UF Research Foundation Professor at the University of Florida. He received his Ph.D. in Computer Science from the University of California at Irvine in 2004. His research interests include embedded and cyber-physical systems\, hardware security and trust\, energy-aware computing\, system-on-chip validation\, machine learning\, and quantum computing. He has published 8 books\, 35 book chapters\, and more than 200 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award\, IBM Faculty Award\, three best paper awards\, and EDAA Outstanding Dissertation Award. He currently serves as an Associate Editor of IEEE Transactions on VLSI Systems and ACM Transactions on Embedded Computing Systems. He is an IEEE Fellow and an ACM Distinguished Scientist. \nHosted By: Prof. Nikil Dutt \n 
URL:https://www.cecs.uci.edu/event/securing-hardware-for-designing-trustworthy-systems/
LOCATION:DBH 4011\, Donald Bren Hall\, University of California\, Irvine\, Irvine\, CA\, 92617\, United States
CATEGORIES:Seminars at CECS
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CREATED:20231011T032346Z
LAST-MODIFIED:20231011T032348Z
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SUMMARY:"DRAC: Designing RISC-V-based Accelerators for next generation Computers"
DESCRIPTION:Speaker: Miquel Moreto\nDate and Time: Wednesday\, August 10\, 11:00 am \nLocation: DBH 3011 OR Zoom Link \nAbstract: \nDesigning RISC-V-based Accelerators for next-generation Computers (DRAC) is a 3-year project (2019-2022) funded by the ERDF Operational Program of Catalonia 2014-2020. DRAC will design\, verify\, implement and fabricate a high-performance general purpose processor that will incorporate different accelerators based on the RISC-V technology\, with specific applications in the field of post-quantum security\, genomics\, and autonomous navigation. In this talk\, we will provide an overview of the main achievements in the DRAC project\, including the fabrication of Lagarto\, the first RISC-V processor developed in Spain. \nBiography: \nMiquel Moreto is a Ramon y Cajal Fellow at the Computer Architecture Departament (DAC) at the Universitat Politècnica de Catalunya (UPC)\, and he leads the High Performance Domain Specific Architectures team at the Barcelona Supercomputing Center (BSC). Miquel received his Ph.D. from UPC in 2010. After finishing the PhD\, he spent 15 months at the International Computer Science Institute (ICSI)\, affiliated with UC Berkeley\, as a Fulbright Postdoctoral Research Fellowship Holder during 2011 and 2012. In 2013\, he returned to Barcelona to work on multiple European projects (RoMoL\, Mont-Blanc\, EPI\, DeepHealth\, eProcessor) and industrial projects (Arm\, IBM\, Lenovo). In 2019\, he led the design and fabrication of Lagarto\, the first processor developed in Spain based on the open source RISC-V instruction set architecture. Currently\, he coordinates the DRAC project\, which is promoting the Lagarto initiative with new generations of the Lagarto processor and accelerators. \nHosted By: Prof. Veidenbaum \n 
URL:https://www.cecs.uci.edu/event/drac-designing-risc-v-based-accelerators-for-next-generation-computers/
LOCATION:DBH 3011\, Donald Bren Hall University of California\, Irve\, Irvine\, CA\, 92617\, United States
CATEGORIES:Seminars at CECS
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