BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20190310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20191103T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20200308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20201101T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20190129T150000
DTEND;TZID=America/Los_Angeles:20190129T160000
DTSTAMP:20231011T190843Z
CREATED:20231011T190827Z
LAST-MODIFIED:20231011T190843Z
UID:14547-1548774000-1548777600@www.cecs.uci.edu
SUMMARY: Partial logic synthesis and its application to automatic generation of parallel/distributed algorithms
DESCRIPTION:Name: Masahiro Fujita\nDate and Time: Thursday\, January 14 at 3:00 p.m. \nLocation:Engineering Hall 3206 \nAbstract: In this talk first we review the partial logic synthesis problem and its associated\nalgorithm based on QBF (Quantified Boolean Formula) formulation. Partial logic synthesis\nis to generate appropriate sub-circuits for the missing portions in the target design so that\nthe entire circuit becomes equivalent to the specification which is separately given. Then\nwe show the problem to automatically generate distributed/parallel computing for the\ngiven specification can be defined as partial logic synthesis problem. Taking matrix-vector\nproduct computation as an example\, we show how theoretical optimum distributed/parallel\ncomputation can be automatically generated targeting many cores/chips which are\nconnected through a ring connection. \nBiography: Masahiro Fujita receivedh is Ph.D. in Information Engineering from the\nUniversity of Tokyo in 1985 on his work on model checking of hardware designs by using\nlogic programming languages. In 1985\, he joined Fujitsu as a researcher and started to\nwork on hardware automatic synthesis as well as formal verification methods and tools\,\nincluding enhancements of BDD/SAT-based techniques. Since March 2000\, he has been a\nprofessor at VLSI Design and Education Center of the University of Tokyo. He has been\ninvolved in a Japanese governmental research project for dependable system designs and\nhas developed a formal verifier for C programs that could be used for both hardware and\nembedded software designs. He has authored and co-authored 10 books\, and has more\nthan 200 publications.
URL:https://www.cecs.uci.edu/event/partial-logic-synthesis-and-its-application-to-automatic-generation-of-parallel-distributed-algorithms/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR