BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20190310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20191103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14532-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:“Regional Coherence and Near Memory Acceleration in Distributed-Shared-Memory Architectures”
DESCRIPTION:Name: Andreas Herkersdorf\nDate and Time: Thursday\, July 26 at 11:00 a.m. – 12:00 p.m. \nLocation: Donald Bren Hall 3011 \nAbstract:  \nData access latencies and bandwidth bottlenecks frequently represent major limiting factors for the computational effectiveness of many-core processor architectures. This presentation introduces two\nconceptually complementary approaches to reduce the synchronization overheads for coherence\nmaintenance and to improve the locality between computing resources and data: Region-based cache\ncoherence and near memory acceleration. \nA 2D array of compute tiles with multiple\, heterogeneous RISC cores\, two levels of caches and a tile-local\nSRAM memory serves as reference processing platform. These compute tiles\, various I/O tiles and a globally shared DDR SDRAM memory tile are interconnected by a meshed Network on Chip (NoC) with support for multiple quality of service levels. Overall\, this processing architecture follows a distributed-\nshared-memory model. The limited degree of parallelism in many embedded computing applications\nalso bounds the number of compute tiles possibly sharing associated data structures. Therefore\, we favor region-based cache coherence (RBCC) among a limited number of compute tiles over global coherence approaches. Coherence regions are dynamically configured at runtime and comprise a number of arbitrary (adjacent or non-adjacent) compute tiles which are interconnected through regular NoC channels for the exchange of coherency protocol messages. We will show that region-based coherence allows maintaining substantially smaller coherence directories (e.g.\, by approx. 40% reduced in size for 16 tiles systems with up to 4 tiles per region) and shorter sharer checking latencies than global coherence. RBCC increases the locally usable intra-tile shared SRAM memories and may reduce execution times of sample video processing applications by 30% in comparison to message passing based parallelization. However\, the benefits of RBCC may strongly depend on the task and data placement among tiles in the coherency region which can affect performance by up to an order of magnitude. Near memory processing using near memory accelerators (NMA) positions processing resources for specific data manipulations as close as possible to the data memory for the benefit of shortening access latencies and increasing compute efficiency. \nBiography: \nAndreas Herkersdorf is a professor in the Department of Electrical and Computer Engineering and also\naffiliated to the Department of Informatics at Technical University of Munich (TUM). He received a Dr.\ndegree from ETH Zurich\, Switzerland\, in 1991. Between 1988 and 2003\, he has been in technical and\nmanagement positions with the IBM Research Laboratory in Rüschlikon\, Switzerland.\nSince 2003\, Dr. Herkersdorf leads the Chair of Integrated Systems at TUM. He is a senior member of the\nIEEE\, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer and De Gruyter journals for design automation and information technology. His research interests include application-specific multi-processor architectures\, IP network processing\, Network on Chip and self-adaptive fault-tolerant computing.
URL:https://www.cecs.uci.edu/event/regional-coherence-and-near-memory-acceleration-in-distributed-shared-memory-architectures/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190742Z
CREATED:20231011T190742Z
LAST-MODIFIED:20231011T190742Z
UID:14533-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Accurate and Stable CPU Power Modelling and Run-Time System Management"
DESCRIPTION:Name: Matthew Walker\nDate and Time: Friday\, July 27 at 11:00 a.m. – 12:00 p.m. \nLocation: Donald Bren Hall 4011 \nAbstract:  \nModern processors must provide an ever-increasing level of performance and are therefore including\nhigher numbers of Heterogeneous Multi-Processing (HMP) units. Intelligent run-time control of performance and power consumption is required to extend battery-life in mobile systems\, reduce energy and cooling costs in data centres\, and increase peak performance while respecting thermal and power constraints. Accurate online power estimation is essential in guiding run-time power management mechanisms and energy-aware scheduling decisions.\n\nIn this talk Matt will share his experience with CPU modelling and run-time management\, and present three open-source software tools for developing power models on mobile devices (http://www.powmon.ecs.soton.ac.uk)\, calibrating performance and energy models in the gem5 simulation framework (http://gemstone.ecs.soton.ac.uk)\, and developing run-time management algorithms (https://github.com/PRiME-project/PRiME-Framework/).\nBiography: \nMatthew J. Walker received his M.Eng. degree in Electronic Engineering (Hons) from the University of Southampton\, UK\, in 2013. In 2016 he worked on implementing non-volatile memory technologies in mobile systems at Intel Labs\, CA\, and has also completed two internships at Arm\, UK\, in 2015 and 2018. He is currently in his fourth year of his PhD at the University of Southampton researching CPU modelling techniques and run-time management approaches.
URL:https://www.cecs.uci.edu/event/accurate-and-stable-cpu-power-modelling-and-run-time-system-management/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190805Z
CREATED:20231011T190805Z
LAST-MODIFIED:20231011T190805Z
UID:14534-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Sensors" Innovation at Intersections"
DESCRIPTION:Name: Khaled Salama\nDate and Time: Friday\, August 3 at 10:00 a.m. – 11:00 a.m. \nLocation: Engineering Hall 2430 \nAbstract:  \n\nEnergy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. We will provide a summary of various sensors developed under the KAUST sensors initiative a consortium of 9 universities (KAUST\, MIT\, UCLA\, GATECH\, MIT\, UCLA\, Brown University\, Georgia Tech\, TU Delft\, Swansea University\, the University of Regensburg and the Australian Institute of Marine Science (AIMS). \n\nBiography: \nKhaled N. Salama received the B.S. degree from the Department Electronics and Communications\, Cairo University\, Cairo\, Egypt\, in 1997\, and the M.S. and Ph.D. degrees from the Department of Electrical Engineering\, Stanford University\, Stanford\, CA\, USA\, in 2000 and 2005\, respectively. He was an Assistant Professor at Rensselaer Polytechnic Institute\, NY\, USA\, between 2005 and 2009. He joined King Abdullah University of Science and Technology (KAUST) in January 2009\, where he is now a professor\, and was the founding Program Chair until August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford–Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc. He is the author of 200 papers and 14 US patents on low-power mixed-signal circuits for intelligent fully integrated sensors and neuromorphic circuits using memristor devices.
URL:https://www.cecs.uci.edu/event/sensors-innovation-at-intersections/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180712T150000
DTEND;TZID=America/Los_Angeles:20180712T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190808Z
LAST-MODIFIED:20231011T190813Z
UID:14539-1531407600-1531411200@www.cecs.uci.edu
SUMMARY:"Sensors" Innovation at Intersections"
DESCRIPTION:Name: Khaled Salama\nDate and Time: Friday\, August 3 at 10:00 a.m. – 11:00 a.m. \nLocation: Engineering Hall 2430 \nAbstract:  \n\nEnergy efficiency is a key requirement for wireless sensor nodes\, biomedical implants\, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement\, or even better\, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus\, they are attractive from an energy efficiency perspective. In addition\, they can be employed in a wide range of sensing applications\, such as pressure\, humidity\, biological\, and chemical sensing. We will provide a summary of various sensors developed under the KAUST sensors initiative a consortium of 9 universities (KAUST\, MIT\, UCLA\, GATECH\, MIT\, UCLA\, Brown University\, Georgia Tech\, TU Delft\, Swansea University\, the University of Regensburg and the Australian Institute of Marine Science (AIMS). \n\nBiography: \nKhaled N. Salama received the B.S. degree from the Department Electronics and Communications\, Cairo University\, Cairo\, Egypt\, in 1997\, and the M.S. and Ph.D. degrees from the Department of Electrical Engineering\, Stanford University\, Stanford\, CA\, USA\, in 2000 and 2005\, respectively. He was an Assistant Professor at Rensselaer Polytechnic Institute\, NY\, USA\, between 2005 and 2009. He joined King Abdullah University of Science and Technology (KAUST) in January 2009\, where he is now a professor\, and was the founding Program Chair until August 2011. His work on CMOS sensors for molecular detection has been funded by the National Institutes of Health (NIH) and the Defense Advanced Research Projects Agency (DARPA)\, awarded the Stanford–Berkeley Innovators Challenge Award in biological sciences and was acquired by Lumina Inc. He is the author of 200 papers and 14 US patents on low-power mixed-signal circuits for intelligent fully integrated sensors and neuromorphic circuits using memristor devices.
URL:https://www.cecs.uci.edu/event/sensors-innovation-at-intersections-2/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180719T150000
DTEND;TZID=America/Los_Angeles:20180719T160000
DTSTAMP:20231011T190813Z
CREATED:20231011T190806Z
LAST-MODIFIED:20231011T190813Z
UID:14535-1532012400-1532016000@www.cecs.uci.edu
SUMMARY:"Efficient Processing when Intelligence Moves to the Edge"
DESCRIPTION:Name: Tinoosh Mohsenin\nDate and Time: Friday\, July 20 at 10:00 a.m. – 11:00 a.m. \nLocation: Donald Bren Hall 4011 \nAbstract:  \n\nContinuous collection and processing of vast amounts of data is becoming more common with the advancement of wearable sensors\, Internet of Things (IoT) devices and cyber physical systems. Despite their potential significant impact\, intelligent mobile technologies face a number of challenges for use in daily life. These devices usually stream raw data to cloud computers for computation which leads to massive storage\, significant transmission power consumption\, real time constraints and privacy/security issues\, thus processing at the edge of sensors is becoming increasingly preferred. Processing these sensor-level data requires a variety of signal processing and machine learning tasks that come at the cost of high computational complexity and memory storage which is overwhelming for these light weight and battery constrained platforms. \nIn this talk I will present research solutions that enable efficient processing of machine learning tasks to improve energy efficiency and throughout without sacrificing application accuracy for wide deployment of embedded/edge processing. First\, I present DeepMatter a scalable framework across algorithms\, architectures and hardware to design an embedded Deep Neural Net (DNN) accelerator. DeepMatter takes any number of raw sensor data for variety of applications and classifies the events within 92% accuracy and consumes very low power. Next I present two programmable domain-specific manycore accelerators namely PENC and BinMACthat achieve energy and speed efficiencies comparable to application-specific custom hardware through data-level and task level parallelization as well as customization of instruction-sets per-core and near-memory computing. I will show the efficiency of DeepMatter as well as PENC and BinMAC solutions for several application domains including multi-physiological processing for seizure and stress monitoring\, tongue drive assistive device\, air quality monitoring andvision-based situational awareness. The solutions derived at the intersection of algorithms\, architectures and implementation allow designers to rapidly prototype and deploy the next generation of sophisticated and intelligent systems for efficient edge processing in extreme environments. \n\nBiography: \nTinoosh Mohsenin is an Assistant Professor in the Department of Computer Science and Electrical Engineering at University of Maryland Baltimore County\, where she directs Energy Efficient High Performance Computing (EEHPC) Lab. She received her PhD from University of California\, Davis in 2010 and M.S. degree from Rice University in 2004\, both in Electrical and Computer Engineering. Prof. Mohsenin’s research focus is on designing highly accurate and energy efficient embedded processors for machine learning\, signal processing and knowledge extraction techniques for autonomous systems\, wearable smart health monitoring\, and embedded big data computing. She has over 80 peer-reviewed journal and conference publications and is the recipient of NSF CAREER award in 2017\, the best paper award in the GLSVLSI conference in 2016\, and the best paper honorable award in ISCAS 2017 for developing domain-specific accelerators for biomedical\, deep learning and cognitive computing. She currently leads 8 research projects in her lab which are all funded by National Science Foundation (NSF)\, Army Research Lab (ARL)\, Northrop Grumman\, Boeing\, Nvidia and Xilinx. She has served as associate editor in IEEE Transactions on Circuits and Systems-I (TCAS-I) and IEEE Transactions on Biomedical Circuits and Systems (TBioCAS). She was the local arrangement co-chair for the 50th IEEE\nInternational Symposium on Circuits and Systems (ISCAS) in Baltimore. She has also served as technical program committee member of the IEEE International Solid-State Circuits Conference Student Research (ISSCC-SRP)\, IEEE Biomedical Circuits and Systems (BioCAS)\, IEEE International Symposium on Circuits and Systems (ISCAS)\, ACM Great Lakes Symposium on VLSI (GLSVLSI and IEEE International Symposium on Quality Electronic Design (ISQED) conferences. She also serves as secretary of IEEE P1890 on Error Correction Coding for Non-Volatile Memories.
URL:https://www.cecs.uci.edu/event/efficient-processing-when-intelligence-moves-to-the-edge/
LOCATION:CA
CATEGORIES:Seminars at CECS
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