BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CECS
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20190310T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20191103T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180206T150000
DTEND;TZID=America/Los_Angeles:20180206T160000
DTSTAMP:20231011T190718Z
CREATED:20231011T190718Z
LAST-MODIFIED:20231011T190718Z
UID:14512-1517929200-1517932800@www.cecs.uci.edu
SUMMARY:“Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins”
DESCRIPTION:Title: “Near-Threshold Computing: The bottom floor for Energy in IoT devices and its Vanishing Design Noise Margins”\nSpeaker: Prof. Sergio Bampi\, Informatics Institute – Microelectronics Design – Federal University of Rio Grande do Sul\, Brazil \nDate and Time: Thursday\, February 15\, 2018 at 2:00PM-3:00PM \nLocation: ICS 432 \nAbstract: \nPromising opportunities for research on heterogeneous Internet-of- Things (IoT) devices lie at the energy-bottom floor\, where CMOS is still an unbeatable\, flexible technology to make the internet of “everything” possible and cost-effective. Near-threshold computing (NTC) in CMOS is a promising alternative for any application which can tolerate or benefit from very wide voltage-frequency scaling (VFS). The digital blocks of devices may operate at very different power-performance modes\, from sub-MHz to peaks of hundreds of MHz\, which requires CMOS design libraries targeted for NTC. The analog and RF content on IoT chips will be even more crucial\, from a power-savings standpoint. In IoT it is best to avoid using costlier CMOS\, and yet closer to an end\, two-dimensional transistor and IC scaling. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific logic design techniques to be applied in digital CMOS. This talk addresses a method to design CMOS digital circuits for a wide dynamic range of VFS\, and targets near-threshold for best energy-efficiency. Our work on 65nm CMOS has demonstrated 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their system operating modes. The results in CMOS were obtained using the minimal cycle time achievable at each supply voltage\, down to very low 200 mV supplies. The strategy for transistor sizing in digital cells and static noise margin maximization will be addressed in particular. The seminar seeks to stimulate system-level and circuit-level design approaches for IoT nodes\, as the presenter is available to discuss digital\, mixed-signal\, and even RF aspects of CMOS systems-on- IoT-devices. \nBiography: \nSergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS\, 1979)\, and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics design fields at the Informatics Institute\, member of the faculty since 1986. He is a member of the PPGC Computing Graduate Program since 1988\, and of the PGMICRO since its start in 2002. He served as Graduate Program Coordinator (2003-2007)\, head of research group and projects\, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff\, and a visiting research faculty at Stanford University (1998-99). His research interests are in the area of IC design\, nano-CMOS devices\, mixed signal and RF CMOS design\, ultra-low power digital design\, dedicated complex algorithms\, architectures\, and ASICs for image and video processing. He has co-authored more than 360 papers in these fields and in MOS devices and EDA. He is a senior member of IEEE. He was Technical Program Chair of IEEE SBCCI Symposium (1997\, 2005)\, SBMICRO (1989\, 1995)\, IEEE LASCAS (2013)\, VARI 2016 Conferences and Workshops.
URL:https://www.cecs.uci.edu/event/near-threshold-computing-the-bottom-floor-for-energy-in-iot-devices-and-its-vanishing-design-noise-margins/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20180222T150000
DTEND;TZID=America/Los_Angeles:20180222T160000
DTSTAMP:20231011T190729Z
CREATED:20231011T190724Z
LAST-MODIFIED:20231011T190729Z
UID:14514-1519311600-1519315200@www.cecs.uci.edu
SUMMARY:”Cost and Power Efficient Deep Neural Network Acceleration”
DESCRIPTION:Title: “Cost and Power Efficient Deep Neural Network Acceleration”\nSpeaker: Associate Prof. Jongeun Lee\, School of ECE\, UNIST\, Ulsan\, Korea \nDate and Time: Monday\, February 26\, 2018 at 11:00am – 12:00pm \nLocation: EH 2430 \nAbstract: \nDeep neural networks prove to be a right direction after all\, but the enormous computational complexity calls for new research into novel ways of making efficient implementations of the connectionist model for small\, mobile devices. \nIn this talk I will discuss two directions\, one based on FPGA and the other based on a new computing paradigm called stochastic computing (SC).  FPGA is a very capable device housing thousands of processing elements in a single chip with low power consumption.  However\, FPGAs are very different from GPUs\, and making it easy to program FPGAs for deep neural networks is one of the key challenges facing FPGAs today.  I will present a design space exploration approach to help find the best design for a given FPGA and for a specific deep neural network model. \nStochastic computing (SC) was first introduced in the 60’s when computing devices were not very reliable.  Unlike conventional binary number representations\, stochastic computing uses a bitstream to represent a number\, and is therefore inherently more error-resilient. \nIn addition\, SC shares some good qualities with analog computing such as low power dissipation and low cost while strictly operating in the digital domain.  At the same time\, error fluctuation and conversion overhead are the key challenges facing SC today.  I will present a new SC architecture for deep neural networks that is much more accurate and efficient than previous SC solutions. \nBiography: \nJongeun Lee received his B.S. and M.S. in Electrical Engineering\, and his Ph.D. in electrical engineering and computer science all from Seoul National University\, Korea. In 2009 he joined UNIST (Ulsan National Institute of Science and Technology)\, Ulsan\, Korea\, where he is now an Associate Professor of Electrical and Computer Engineering. Prior to joining UNIST\, he worked as a postdoctoral research associate at Arizona State University\, and previously worked for Samsung Electronics. His current research interests include reconfigurable architectures\, compilers\, stochastic computing\, and deep neural networks.
URL:https://www.cecs.uci.edu/event/cost-and-power-efficient-deep-neural-network-acceleration/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR