BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20160313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20161106T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171003T150000
DTEND;TZID=America/Los_Angeles:20171003T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14496-1507042800-1507046400@www.cecs.uci.edu
SUMMARY:“Detecting Hardware Trojans Hidden in Unspecified Design Functionality”
DESCRIPTION:Title: “Detecting Hardware Trojans Hidden in Unspecified Design Functionality”\nSpeaker: Dr. Nicole Fern\, University of California\, Santa Barbara \nDate and Time: Thursday\, November 16th\, 2017 at 2:00PM-3:00PM \nLocation: Donald Bren Hall 3011 \nAbstract: \nTraditional verification methods and metrics attempt to answer the question: does my design correctly perform the intended functionality?  This talk will look at hardware verification from a security perspective\, which demands the verification effort answer an additional question: does my design perform malicious functionality in addition to the intended functionality?  The talk will motivate through examples why Hardware Trojans modifying only unspecified design functionality are both powerful and stealthy.  RTL don’t cares and idle cycles in on-chip bus protocols are two examples of unspecified functionality vulnerable to malicious modification that this talk will explore in depth.  This talk will also detail how to formulate the Trojan detection problem as a satisfiability problem in order to leverage existing formal verification tools to highlight Trojans hidden in unspecified functionality. \nBiography:  \nNicole Fern received her undergraduate degree in Electrical Engineering from The Cooper Union for the Advancement of Science and Art and her PhD degree in the ECE department at UC Santa Barbara under the advisement of Professor Tim Cheng.  She is now a post-doc at UC Santa Barbara.  Her thesis work focused on developing techniques to verify the absence of Hardware Trojans in unspecified design functionality.  Her current research interests include investigating security issues in emerging memory technologies and at the hardware/software boundary. \n  \n 
URL:https://www.cecs.uci.edu/event/detecting-hardware-trojans-hidden-in-unspecified-design-functionality/
LOCATION:CA
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20171003T150000
DTEND;TZID=America/Los_Angeles:20171003T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14495-1507042800-1507046400@www.cecs.uci.edu
SUMMARY:"Application Mapping Methodologies for NoC-Based MPSOCs"
DESCRIPTION:Title: “Application Mapping Methodologies for NoC-Based MPSOCs”\nSpeaker: Jürgen Teich\, Friedrich-Alexander Universität Erlangen-Nürnberg (FAU) \nDate and Time: Tuesday\, November 14\, 2017 at 3:00PM-4:00PM \nLocation: DBH 4011 \nAbstract:  \nIn this talk\, we give an overview of novel techniques for systematically mapping applications to NoC-based multi-core architectures\n(MPSoCs). Complex applications requiring heterogenous processing resources are often described by task graphs\nwith data dependencies. Here\, the nodes represent actors or tasks which are typically activated periodically based on the\navailability of data. One prominent domain of applications fitting this model is stream processing. Here\, it is often important to guarantee\neither bandwidth or execution time requirements. But more recently\, also security\, energy and reliability aspects impose\nconstraints on the mapping of the tasks as well as their communication to cores\, respectively routes in the underlying NoC. \nConcerning mapping methodologies\, we first present a class of algorithms that perform “Self-Embedding”. The idea is here that\na source node issues a request to find appropriate resources to embed its sucessor tasks\, and so on.\nThe next class of techniques introduced is called “Hybrid Application Mapping (HAM)”. Here\, a careful analysis and\ncharacterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time)\nphase called “Design Space Exploration (DSE)”. At run-time\, the operating system then only needs to search within such\npre-analysed constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction.\nWe present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that\ndeadlines or throughput requirements will be automatically met for streaming applications.\nFinally\, we conclude with a discussion on resource constellations that may satisfy certain security requirements on an MPSoC. \nBiography: \nJürgen Teich is with Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)\, Germany\, where he is directing\nthe Chair for Hardware/Software Co-Design since 2003. He received the M.S. degree (Dipl.-Ing.; with honors)\nfrom the University of Kaiserslautern\, Germany in 1989 and the Ph.D. degree (Dr.-Ing.; summa cum laude)\nfrom the University of Saarland\, Saarbruecken\, Germany\, in 1993. In 1994\, he joined the DSP design group of Prof. E. A. Lee\nin the Department of Electrical Engineering and Computer Sciences (EECS)\, University of California at\nBerkeley (PostDoc). From 1995 to 1998\, he held a position at the Institute of Computer Engineering and\nCommunications Networks Laboratory (TIK)\, ETH Zurich\, Switzerland with his Habilitation\non the topic of `Synthesis and Optimization of Digital Hardware/Software Systems’ in 1996.\nFrom 1998 to 2002\, he was Full Professor in the Electrical Engineering and Information Technology\nDepartment\, University of Paderborn\, Germany. \nHis current research focuses on electronic design automation of embedded systems\nwith emphasis on hardware/software co-design\, reconfigurable computing and multi-core systems.\nProf. Teich has organized various ACM/IEEE conferences/symposia as Program Chair\nincluding CODES+ISSS´07\, FPL´08\, ASAP´10\, and DATE´2016.\nHe serves regularly as a TPC member of many program committees including DAC\, ASP-DAC\, ICCAD\, FPL\,\nASAP\, FPT\, FPGA\, RECONFIG\, ESTIMEDIA\, VLSI Design\, GECCO\, EMO\, RTSS\, etc.\nHe also serves in the editorial board of journals including ACM TODAES\, IEEE Design and Test and JES and has\nedited two text books on Hardware/Software Co-Design and recently a Handbook on this topic (Springer). \nProf. Teich is involved in many interdisciplinary projects on basic research as well as industrial projects.\nFrom 2003-2009\, he was an elected board member (Fachkollegiat) of the Deutsche Forschungsgemeinschaft (DFG)\nfor the area of Computer Architecture and Embedded Systems. He has been the initiator and\ncoordinator of the DFG priority programme 1148 on “Reconfigurable Computing”.\nSince 2010\, he has also been the principal coordinator of the Transregional\nResearch Center 89 “Invasive Computing” funded by the German Research Foundation (DFG).\nIn 2011\, he was elected member of the Academia Europaea. \n 
URL:https://www.cecs.uci.edu/event/application-mapping-methodologies-for-noc-based-mpsocs/
LOCATION:CA
CATEGORIES:Seminars at CECS
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