BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
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REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
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TZOFFSETFROM:-0800
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TZOFFSETFROM:-0700
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TZNAME:PST
DTSTART:20161106T090000
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TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20170312T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20171105T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20180311T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20181104T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170807T150000
DTEND;TZID=America/Los_Angeles:20170807T160000
DTSTAMP:20231011T190642Z
CREATED:20231011T190642Z
LAST-MODIFIED:20231011T190642Z
UID:14494-1502118000-1502121600@www.cecs.uci.edu
SUMMARY:Part I: “Development of Low-End Embedded Processors for Some SoC Applications”    Part II: “The Application-Specific Design for Signal Processing Applications”
DESCRIPTION:Title: Part I: “Development of Low-End Embedded Processors for Some SoC Applications”Part II: “The Application-Specific Design for Signal Processing Applications” \nSpeaker: Prof. Fitzgerald Sungkyung Park\, Pusan National University\, Busan\, South Korea\nProf. Chester Park\, Konkuk University\, Seoul\, Korea \nDate and Time: Monday\, August 7\, 2017\, 2:00 PM – 3:00 PM \nLocation: Donald Bren Hall 3011 \nAbstract: \nLow-end processor cores can be utilized in various SoC applications including IoT\, wireless communication\, and machine learning.  In this short talk\, we will introduce how we designed some low-end integer cores applied to some applications such as deeply embedded IoT and WLAN MAC Soc\, and also introduce the basic design of embedded cores for neural networks. \nPart II: The application-specific design for signal processing applications tends to necessitate multi-disciplinary knowledge on system\, algorithm\, architecture and circuit levels.  In this talk\, we will introduce our application-specific design approaches for various signal processing applications.  In addition\, we discuss several design challenges involved in system-on-a-chip (SoC) design for neural networks\, regarding how to customize the on-chip bus architecture. \nBiography: \nProf. Fitzgerald Sungkyung Park took his Ph.D. degree in electronics engineering from Seoul National University\, Korea\, in 2002. He worked for Samsung Electronics from 2002 to 2004\, joined Electronics and Telecommunications Research Institute (ETRI) from 2004 to 2006\, and worked for Ericsson\, Inc.\, USA\, from 2006 to 2009\, where he developed mixed-signal circuits for radio transceivers. In 2009\, he joined the faculty of Pusan National University\, where he has worked on low-end processors and SoC for IoT and other applications. \nProf. Chester Park received his Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST)\, Korea\, in 2006. After about two years with Samsung Electronics Inc.\, Giheung\, Korea\, he joined Ericsson Research\, USA\, where he developed various signal processing algorithms for wireless communications. Since 2013\, he has been with Konkuk University\, Seoul\, Korea\, working on hardware accelerator design for signal processing algorithms. \n 
URL:https://www.cecs.uci.edu/event/part-i-development-of-low-end-embedded-processors-for-some-soc-applications-part-ii-the-application-specific-design-for-signal-processing-applications/
LOCATION:CA
CATEGORIES:Seminars at CECS
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