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DTSTART;TZID=America/Los_Angeles:20170605T150000
DTEND;TZID=America/Los_Angeles:20170605T160000
DTSTAMP:20231011T190636Z
CREATED:20231011T190636Z
LAST-MODIFIED:20231011T190636Z
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SUMMARY:Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics
DESCRIPTION:Title:  “Self-Awareness in Remote Health Monitoring Systems using Wearable Electronics”\nSpeaker: Prof. Axel Jantsch\, TU Wien \nDate and Time:  Friday\,  June 16\, 2017 at 11 A.M. \nLocation: 2430 Engineering Hall \nHost: Prof. Nikil Dutt \nAbstract: In healthcare\, effective monitoring of patients plays a key role in detecting health deterioration early enough. Many signs of deterioration exist as early as 24 hours prior having a serious impact on the health of a person. As hospitalization times have to be minimized\, in-home or remote early warning systems can fill the gap by allowing in-home care while having the potentially problematic conditions and their signs under surveillance and control. This walk presents a remote monitoring and diagnostic system that provides a holistic perspective of patients and their health conditions. It discusses how the concept of self-awareness can be used in various parts of the system such as information collection through wearable sensors\, confidence assessment of the sensory data\, the knowledge base of the patient’s health situation\, and automation of reasoning about the health situation. This approach to self-awareness provides \n(i) situation awareness to consider the impact of variations such as sleeping\, walking\, running\, and resting\, \n(ii) system personalization by reflecting parameters such as age\, body mass index\, and gender\, and \n(iii) the attention property of self-awareness to improve the energy efficiency and dependability of the system via adjusting the priorities of the sensory data collection.\nBiography: \n Axel Jantsch received the Dipl.Ing. and Dr. Tech. degrees from TU Wien\, Vienna\, Austria\, in 1988 and 1992\, respectively. He was with Siemens Austria\, Vienna\, Austria\, as a system validation engineer from 1995 to 1997. From 1997 to 2002 he was an associate professor and from 2002 to 2014 he was full professor of Electronic Systems Design at the Royal Institute of Technology (KTH)\, Stockholm\, Sweden. Since 2014 he has been professor of Systems on Chip at TU Wien. He has published about 300 papers in international conferences and journals and one book in the areas of Systems on chip\, networks on chip and embedded systems. He has served on a large number of technical program committees of international conferences\, such as FDL\, DATE\, CODES ISSS\, SOC\, NOCS\, and others. He has been the TPC Chair of SSDL/ FDL 2000\, the TPC Co-Chair of CODES ISSS 2004\, the General Chair of CODES ISSS 2005\, and the TPC Co-Chair of NOCS 2009. From 2002 to 2007\, he was a subject area editor for the Journal of System Architecture. He is on the editorial board for IEEE Design and Test and for the Leibniz Transactions on Embedded Systems. He is a member of the IEEE. His main research interest is on networks on chip and self-awareness in systems on chip and embedded systems.\n\n\nView Details Here
URL:https://www.cecs.uci.edu/event/self-awareness-in-remote-health-monitoring-systems-using-wearable-electronics/
LOCATION:CA
CATEGORIES:Seminars at CECS
ATTACH;FMTTYPE=image/png:https://cecs.uci.edu/files/2023/10/axel_jantsch_seminar-iBdaHY.tmp_.png
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DTSTART;TZID=America/Los_Angeles:20170607T150000
DTEND;TZID=America/Los_Angeles:20170607T160000
DTSTAMP:20231011T190637Z
CREATED:20231011T190637Z
LAST-MODIFIED:20231011T190637Z
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SUMMARY:Mobile and Emerging Computing Systems: challenges and research opportunities
DESCRIPTION:Title: “Mobile and Emerging Computing Systems: challenges and research opportunities”\nSpeaker: Dr. Raid Ayoub\, Intel Strategic CAD Lab\, Portland\, Oregon\, USA \nDate and Time: Friday\, June 23\, 2017 at 11:00AM-12:00PM \nLocation: DBH 3011 \nAbstract: \nThe computing systems have been evolving at a fast pace and they are increasingly ubiquitous. This trend is driven by advancements in mobile technologies and emerging of Internet-of-Things (IoT) as well as new applications. However\, the complexity and diversity of these systems continue to rise\, which require transformative design automation solutions to meet stringent design metrics\, e.g. time-to-market. This talk will address research problems in mobile computing at the system level with some emphasis on energy efficiency and power budgeting of the CPU-GPU subsystem as well as user-experience related problems (e.g. skin temperature estimation and control). In addition\, this talk will discuss emerging challenges and future research problems in the domain of IoT systems with a focus on End-to-End system design. \nBiography: \nRaid Ayoub received his Ph.D. degree in computer engineering from the department of computer science and engineering\, University of California at San Diego in 2011.Currently he is a research scientist at the Strategic CAD Labs of Intel Corporation. He has published more than 30 journal and conference papers. His research interests include run-time optimizations\, dynamic control\, system modeling\, human cyber-physical systems/IoT\, dynamic power and thermal management\, machine learning\, and design automation.
URL:https://www.cecs.uci.edu/event/mobile-and-emerging-computing-systems-challenges-and-research-opportunities/
LOCATION:CA
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20170614T150000
DTEND;TZID=America/Los_Angeles:20170614T160000
DTSTAMP:20231011T190708Z
CREATED:20231011T190700Z
LAST-MODIFIED:20231011T190708Z
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SUMMARY:"Optimizing Private Local Memories in Heterogeneous Architectures"
DESCRIPTION:Title: “Optimizing Private Local Memories in Heterogeneous Architectures”\nSpeaker: Christian Pilato\, Università della Svizzera italiana (USI)\, Lugano\, Switzerland \nDate and Time: Wednesday\, June 14\, 2017 at 11:00AM-12:00PM \nLocation: ICS 432 \nAbstract: \nModern Systems-on-Chip (SoC) architectures and state-of-the-art computing platforms that integrate CPUs with FPGAs are heterogeneous systems featuring an increasing number of hardware accelerators. Private local memories play a key role in the design of these components both with respect to performance optimization and because they are responsible for most of their area and power dissipation. Each local memory unit is usually implemented with a multibank microarchitecture based on the combined requirements of each hardware block accessing the corresponding data. However\, the creation of these multibank memory microarchitectures is not well supported by current design flows\, and the designers must perform this tedious and error-prone process manually. \nIn this talk\, I will present a system-level methodology for the generation of multi-bank memories in heterogeneous architectures. The methodology is supported by Mnemosyne\, an open-source prototype CAD tool that can be easily integrated into commercial design flows. Mnemosyneincludes various technology-aware optimizations to reduce the memory cost (area and power) by efficiently reusing the physical banks for storing different data. With Mnemosyne\,we can reduce the memory cost of single accelerators by up to 45%. Moreover\, when reusing memory IPs across accelerators\, we achieve area savings that range between 17% and 55% compared to the case where the memory elements are designed separately. \nBiography: \nChristian Pilato is a Postdoctoral Researcher at the ALaRi institute of Università della Svizzera italiana (USI)\, Lugano\, Switzerland. He received the Laurea degree in computer engineering and the Ph.D. degree in information technology from Politecnico di Milano\, Italy\, in 2007 and 2011\, respectively. From 2013 to 2016\, he was a Postdoctoral Research Scientist with the Department of Computer Science\, Columbia University\, USA. He has been visiting researcher at NanGate\, Chalmers University of Technology\, and Delft University of Technology. 
His current research interests include high-level synthesis\, reconfigurable systems and system-on-chip architectures\, with emphasis on memory aspects. He has actively participated in several projects sponsored by the European Union and DARPA\, as well as a research center supported by SRC. Dr. Pilato served as the Program Chair of the Embedded and Ubiquitous Conference (EUC) in 2014. He is currently involved in the program committees of many conferences on embedded systems\, CAD\, and reconfigurable architectures\, such as FPL\, DATE\, and CASES. He is a Member of IEEE and ACM.

URL:https://www.cecs.uci.edu/event/optimizing-private-local-memories-in-heterogeneous-architectures/
LOCATION:CA
CATEGORIES:Seminars at CECS
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