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DTSTART;TZID=America/Los_Angeles:20170417T150000
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DTSTAMP:20231011T190631Z
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LAST-MODIFIED:20231011T190631Z
UID:14484-1492441200-1492444800@www.cecs.uci.edu
SUMMARY:Heterogeneous Chip Architectures for Big Data Analytics
DESCRIPTION:Title: “Heterogeneous Chip Architectures for Big Data Analytics”\nSpeaker: Houman Homayoun\, George Mason University\, Virginia \nDate and Time: Friday\, April 28\, 2017 at 11:00AM \nLocation: 2430 Engineering Hall \n \nAbstract: \nThere is a fundamental shift underway now in various industry sectors to transport their big data to the clouds\, thus increasing their efficiency and improving cash flow. In addition to traditional web service sector\, this also includes sectors such as telecommunication (e.g.\,  software defined network  applications)\, and healthcare (e.g.\, GE Cloud Health and Cloud PACS ). Cloud servers to process big data are now aggregating multiple disparate workloads with heterogeneously structured and unstructured data (image\, text\, video\, graph) with varying performance goals (batch\, streaming\, real-time\, and near-real-time). Emerging analytics applications in these domains rely heavily on specific deep machine learning and mining algorithms\, and are running complex database software stack with significant interaction with I/O and OS and sharing many inherent characteristics that are fundamentally different from traditional CPU and parallel applications. Emerging big data applications require computing resources that can efficiently scale to manage massive amounts of diverse data. However\, the rapid growth in the data yields challenges to process them efficiently using current cloud server architectures such as high performance Xeon. Furthermore\, physical design constraints\, such as power and density\, have become the dominant limiting factor for scaling out servers. To respond to these challenges\, heterogeneous architectures which integrates big and little cores with FPGA accelerators has emerged as a promising solution. In this talk\, through methodical investigation of power and performance measurements\, and comprehensive system level and micro-architectural analysis\, I first show the characterization results of emerging big data applications on big Xeon and little Atom-based servers. The characterization results across a wide range of real-world big data applications and various software stacks demonstrate how the choice of big vs little core-based server for energy-efficiency is significantly influenced by the size of data\, performance constraints\, and presence of accelerator. Furthermore\, the microarchitecture-level analysis highlights where improvement is needed in big and little core servers. \nSecond\, I will show how in a heterogeneous architecture effective mapping of Hadoop and Spark MapReduce based applications to FPGA accelerator can significantly increase the energy-efficiency and performance. The real-system results show promising kernel speedup of more than 100X and significant energy-efficiency gains. \nBiography: \nHouman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University. He also holds a joint appointment with the Department of Computer Science as well as Information Science and Technology Department. He is the director of GMU’s Green Computing and Heterogeneous Architectures (GOAL) Laboratory. Prior to joining George Mason University\, Houman spent two years at the University of California\, San Diego\, as National Science Foundation Computing Innovation (CI) Fellow awarded by the Computing Research Association (CRA) and the Computing Community Consortium (CCC). \nHouman’s research is in big data computing\, heterogeneous computing\, hardware security and trust\, and spans the areas of computer design and embedded systems\, where he has published more than 70 technical papers in the most prestigious conferences and journals on the subject. He is currently leading a number of research projects\, including the design of next generation heterogeneous architectures for big data processing\, non-volatile STT logic to prevent design reverse engineering\, heterogeneous accelerator platforms for wearable biomedical computing\, and logical vanishable design to enhance hardware security which are all funded by National Science Foundation (NSF)\, General Motors Company (GM)\, National Institute of Standards and Technology (NIST)\, Defense Advanced Research Projects Agency (DARPA)\, and Air Force Research Laboratory(AFRL). He received the 2016 GLSVLSI conference best paper award. He is currently serving as an Associate Editor of IEEE Transactions on VLSI (TVLSI). \nHouman received his PhD degree from the Department of Computer Science at the University of California\, Irvine in 2010\, an MS degree in computer engineering in 2005 from University of Victoria\, Canada and his BS degree in electrical engineering in 2003 from Sharif University of Technology.
URL:https://www.cecs.uci.edu/event/heterogeneous-chip-architectures-for-big-data-analytics/
LOCATION:CA
CATEGORIES:Seminars at CECS
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