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DTSTART;TZID=America/Los_Angeles:20161104T150000
DTEND;TZID=America/Los_Angeles:20161104T160000
DTSTAMP:20231011T190622Z
CREATED:20231011T190622Z
LAST-MODIFIED:20231011T190622Z
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SUMMARY:Adaptive Design: Tackling Variability Challenges in VLSI Circuits
DESCRIPTION:Title: “Adaptive Design: Tackling Variability Challenges in VLSI Circuits”\nSpeaker: Professor Mingoo Seok\, Columbia University\, New York \nDate:  Friday\, April 22\, 2016 \nTime:  3:00PM \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost: Prof. Payam Heydari \nAbstract: In this talk\, we will discuss variability challenges in VLSI systems and our recent research efforts on variation-adaptive design techniques. Variability in supply voltage\, chip temperature\, manufacturing process\, and transistor aging have imposed a large amount of pessimistic margins in clock frequency\, voltage\, and device size\, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead\, in-situ\, within-a-cycle timing-error detection and correction technique that can operate at near/sub-threshold voltage\, (2) ultra-compact thermal sensor circuits enabling 10-100X denser on-chip thermal sensing\, (3) self-testing circuits and frameworks for in-field & in-situ aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented. \nBio: \nMingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. He received the BS (with summa cum laude) in electrical engineering from Seoul National University\, South Korea\, in 2005\, and the MS and PhD degree from University of Michigan in 2007 and 2011\, respectively\, all in electrical engineering. He was a member of technical staff in Texas Instruments\, Dallas in 2011. He joined Columbia University in 2012. His research interests are various aspects of computing systems\, including ultra-low-power computing systems\, computing systems for machine learning\, adaptive circuits and architecture\, and non-conventional computing systems. \nHe received 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies\, 2005 Doctoral Fellowship from the same organization\, and 2008 Rackham Pre-Doctoral Fellowship from University of Michigan. He also won 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and 2009 DAC/ISSCC Design Contest for the 35pW sensor platform design. He won 2015 NSF CAREER award. He has been serving as an associate editor for IEEE Transactions on Circuits and Systems I since 2013\, and IEEE Transactions on VLSI Systems since 2015.
URL:https://www.cecs.uci.edu/event/adaptive-design-tackling-variability-challenges-in-vlsi-circuits/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161105T150000
DTEND;TZID=America/Los_Angeles:20161105T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14478-1478358000-1478361600@www.cecs.uci.edu
SUMMARY:Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow
DESCRIPTION:Title:  “Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow”\nSpeaker: Christian Krieg\, Vienna University of Technology\, Vienna\, Austria \nDate and Time: Thursday\, November 17\, 2016 at 2:00 PM \nLocation: Donald Bren Hall 3011 \nHost:  Professor Nikil Dutt \nAbstract: We present a novel type of Trojan trigger targeted at the field-programmable gate array (FPGA) design flow. Traditional triggers base on rare events\, such as rare values or sequences. While in most cases these trigger circuits are able to hide a Trojan attack\, exhaustive functional simulation and testing will reveal the Trojan due to violation of the specification. Our trigger behaves functionally and formally equivalent to the hardware description language (HDL) specification throughout the entire FPGA design flow\, until the design is written by the place-and-route tool as bitstream configuration file. From then\, Trojan payload is always on. We implement the trigger signal using a 4-input lookup table (LUT)\, each of the inputs connecting to the same signal. This lets us directly address the least significant bit (LSB) and most significant bit (MSB) of the LUT. With the remaining 14 bits\, we realize a “magic” unary operation. This way\, we are able to implement 16 different Triggers. We demonstrate the attack with a simple example and discuss the effectiveness of the recent detection techniques unused circuit identification (UCI)\, functional analysis for nearly-unused circuit identification (FANCI) and VeriTrust in order to reveal our trigger. \nBiography: Christian Krieg received the bachelor’s and master’s degree in electrical engineering from TU Wien and is now pursuing his PhD studies on hardware security at TU Wien. His research focuses on design-level hardware Trojan design and detection. He also works on reasonable threat models for hardware Trojan attacks. Christian recently received the William McCalla best paper award for a novel hardware Trojan implementation. At a wider scope\, Christian’s research interests include cyber-physical systems security and IoT security. \nView Details
URL:https://www.cecs.uci.edu/event/malicious-lut-a-stealthy-fpga-trojan-injected-and-triggered-by-the-design-flow/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161105T150000
DTEND;TZID=America/Los_Angeles:20161105T160000
DTSTAMP:20231011T190623Z
CREATED:20231011T190623Z
LAST-MODIFIED:20231011T190623Z
UID:14480-1478358000-1478361600@www.cecs.uci.edu
SUMMARY:High Level Synthesis - Some Challenging Problems
DESCRIPTION:Title: “High Level Synthesis – Some Challenging Problems”\nSpeaker: George A. Constantinides\, Imperial College London\, UK \nDate and Time: Wednesday\, November 16\, 2016 at 11:00 A.M. \nLocation: Engineering Hall 2430 \nHost: Professor Nikil Dutt \nAbstract: High Level Synthesis – synthesis of circuits from behavioral descriptions – is a long-standing problem\, but one that appears to now have come to age. Both the demand for\, and the supply of\, quality HLS tools is now in place. However\, there are still some hard problems to be overcome in order to make HLS fully general. My research focuses on two of these: customization of memory systems to algorithms\, and customization of number representation to algorithms. After briefly introducing the work at Imperial – and encouraging PhD and postdoc applications (!) – I will spend a little time on each of these problems. In particular\, I will look at the problem of customization of memory for heap manipulating programs\, the potential of parametric analysis for synthesis of lightweight run-time scheduling changes\, and automates code refactoring for rigorously controlled accuracy / latency / area optimization. I hope to inspire the audience to consider how you may be able to contribute to these problems. \nBiography: Prof George A. Constantinides holds the Royal Academy of Engineering / Imagination Technologies Chair in Digital Computation at Imperial College London\, where he leads the Circuits and Systems research group. He has been a member of staff at Imperial since 2001. Over this time he has been the proud supervisor of 25 graduated PhD students and chaired the FPGA\, FPT\, and FPL conferences. He enjoys hard problems and espresso. \nView more here
URL:https://www.cecs.uci.edu/event/high-level-synthesis-some-challenging-problems/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20161107T150000
DTEND;TZID=America/Los_Angeles:20161107T160000
DTSTAMP:20231011T190616Z
CREATED:20231011T190616Z
LAST-MODIFIED:20231011T190616Z
UID:14472-1478530800-1478534400@www.cecs.uci.edu
SUMMARY:Low Energy\, a New Trend for Lightweight Cryptography
DESCRIPTION:Title: “Low Energy\, a New Trend for Lightweight Cryptography”\nSpeaker: Dr. Francesco Regazzoni\, ALaRI Institute of Università della Svizzera italiana\, Lugano\, Switzerland \nDate and Time:  Wednesday\, February 1\, 2017 at 11:00 a.m. \nLocation: DBH 4011 \nHost: Prof. Nikil Dutt \nAbstract: In the last decade\, several lightweight block ciphers and hash functions have been proposed. One of the metrics\, so far largely unexplored\, which has to be used to identify a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers\, this operation is the encryption of one plaintext. \nThis talk will address several approaches for reducing the energy consumption of existing block ciphers\, touching the design space of the AES algorithm\, to which few algorithmic optimizations are applied. \nThe gained experience lead to the design of Midori\, the first block cipher designed to optimize the energy consumed per bit in encryption or decryption operation. Each component of the circuit\, as well as its entire architecture of the cipher\, have been optimized for energy\, and design choices leading to low energy consumption in an electrical circuit were taken. Achieved results demonstrate that the energy consumption of Midori64 and Midori128 is much lower that current stateof the art.\n \nBiography: Dr. Francesco Regazzoni is a senior researcher at the the ALaRI Institute of Universita’ della Svizzera italiana (Lugano\, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at the ALaRI Institute of Universita’ della Svizzera italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft\, and visiting researcher at several institutions\, including NEC Labs America\, Ruhr University of Bochum\, EPFL\, and NTU Singapore. His research interests are mainly focused on embedded systems security\, covering in particular side channel attacks\, electronic design automation for security\, hardware Trojans\, low energy cryptography\, and post quantum security. He has published more than 70 journal and conference papers in the area of security and design automation\, and has been in the technical program committed of top conferences of the area. Francesco is the principal investigator and project leader at Universita’ della Svizzera italiana of the projects (SAFECrypto\, exploring lattice-based constructions as building blocks for quantum resistant cryptography)\, and CERBERO (design tools for Cyber-Physical Systems). \nView Details Here
URL:https://www.cecs.uci.edu/event/low-energy-a-new-trend-for-lightweight-cryptography/
LOCATION:CA
CATEGORIES:Seminars at CECS
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