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DTSTART;TZID=America/Los_Angeles:20160715T150000
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UID:14447-1468594800-1468598400@www.cecs.uci.edu
SUMMARY:Area/speed tradeoffs in a retargetable FPGA-optimized processor core
DESCRIPTION:Speaker:  Marco Zec\, University of Zagreb \nTitle:  “Area/speed tradeoffs in a retargetable FPGA-optimized processor core” \nDate:  Friday\, July 15\, 2016 \nTime:  11:00 AM \nLocation:  CECS Conference Room (Engineering Hall 3206) \nHost:  Prof. Daniel Gajski \nAbstract: Can portable yet efficient\, FPGA-optimized processor cores be constructed using generic HDL\, without depending on any vendor-specific primitives?  In this talk we will discuss the techniques applied for achieving a balance between instruction throughput and FPGA resource utilization in a synthesizable scalar core which outperforms its proprietary counterparts (MicroBlaze\, Nios\, Cortex-M3) by 20% to 40% in industry-standard integer benchmarks (CoreMark\, Dhrystone per MHz) while\noccupying less than 1000 6-input LUTs\, and less than 650 LUTs in an area-optimized configuration.  The core can be retargeted to execute subsets of either the emerging RISC-V or the traditional MIPS instruction sets\, and is supported by contemporary GNU-based software toolchains.\n \nBio: Marko Zec received a BSc in electrical engineering from the University of Zagreb\, where since 2005. he has been working as a project scientist on various computer networks projects with funding from ICSI Berkeley\, the FreeBSD foundation\, Boeing Integrated Defense Systems\, and Ericsson. His research interests include operating systems\, computer networks\, software-based packet processing datapaths\, and programmable logic. \nView Details
URL:https://www.cecs.uci.edu/event/area-speed-tradeoffs-in-a-retargetable-fpga-optimized-processor-core/
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CATEGORIES:Seminars at CECS
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