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DTSTART;TZID=America/Los_Angeles:20150709T150000
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DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14436-1436454000-1436457600@www.cecs.uci.edu
SUMMARY:Reviving Processing-in-Memory for Large Data Workload on Existing Computer Architecture
DESCRIPTION:Speaker:  Professor Sungjoo Yoo\, Computing and Memory Architecture Lab\, Seoul National University \nTitle:  Reviving Processing-in-Memory for LArge Data Workload on Existing Computer Architecture \nDate:  Tuesday\, July 14\, 2015 \nTime:  11:00 AM \nLocation:  Donald Bren Hall 3011 \nHost:  Nikil Dutt \nAbstract:  Processing-in-memory (PIM) is rebounding from its unsuccessful attempts in 1990s due to two main reasons\, recent advances in 3D stacking technologies and emerging large data workload.  In this talk\, we present two of our recent works\, PIM for large data workload and combining PIM with the existing computer architecture.\nGraph data are becoming more and more popular in many areas such as machine learning\, social network analysis\, etc.  Graph computation is to process a query to the graph database\, e.g.\, finding the most popular personality.  Graph computation is characterized by computation parallelism (per-vertex parallel computation) and significant random memory accesses (to neighbor vertices).  The conventional architecture is not well suited for this type of workload.  We present a programmable PIM accelerator for large-scale graph processing called Tesseract.  Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth\, (2) an efficient method of communication between different memory partitions\, and (3) a programming interface that reflects and exploits the unique hardware design.  It also includes two hardware prefecthers specialized for memory access patterns of graph processing\, which operate base on the hints provided by our programming model.\nIn order to make best use of PIM in more areas\, it is required to integrate the PIM architectures with existing systems in a seamless manner.  The current PIM proposals lack due to two common characteristics: unconventional programming models for in-memory computation units (as programmable co-processors) and lack of ability to utilize large on-chip caches.  We propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data.  The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions\, which we call PIM-enabled instructions\, to invoke in-memory computation.  This allows PIM operations to be interoperable with existing programming models\, cache coherence protocols\, and virtual memory mechanisms with no modification. \nView Details
URL:https://www.cecs.uci.edu/event/reviving-processing-in-memory-for-large-data-workload-on-existing-computer-architecture/
LOCATION:CA
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20150729T150000
DTEND;TZID=America/Los_Angeles:20150729T160000
DTSTAMP:20231011T190519Z
CREATED:20231011T190518Z
LAST-MODIFIED:20231011T190519Z
UID:14438-1438182000-1438185600@www.cecs.uci.edu
SUMMARY:Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems
DESCRIPTION:Speaker:  Prof. Muhammad Mustafa Hussain\, King Abdullah University of Science and Technology (KAUST) \nTitle:  “Flexible-Stretchable-Reconfigurable CMOS Electronics Through Hybrid Integration of Heterogeneous Materials for Wearable Interactive Electronic Systems” \nDate:  Tuesday\, April 21\, 2015 \nTime:  2:00 PM \nLocation:  Harut Barsamian Colloquia Room (Engineering Hall 2430) \nHost:  Prof. Fadi Kurdahi \nAbstract: Our research is focused on heterogeneous electronic materials and high-performance complementary metal oxide semiconductor (CMOS) based tunable shape-size-conformity wearable interactive electronics and systems for smart living (computation-communication-infotainment) through internet of everything and a sustainable future (healthcare-water-food-environment-security). For scientific exploration\, we make collective use of the materials\, processes and device architecture leveraging multidisciplinary tracks of material science\, bioengineering\, mechanical\, environmental engineering and computer science. As engineering tool\, we use CMOS technology extensively due to its industrial relevance\, maturity and reliability for rapid tech transfer.\nTo bridge between the high-performance state-of-the-art electronics and emerging soft-materials based flexible-stretchable electronics. we have developed various generic batch processes using CMOS technologies to transform any already processed Integrated Circuitry (IC) or arrays of devices to be fabricated on virgin substrates (thin film based\, examples include but not limited to: silicon\, silicon germanium\, indium phosphide\, gallium arsenide\, etc.) into flexible and stretchable one [ACS Nano 2014\, pss-RRL 2014]. These processes are cost effective ($1.25/cm2)\, non-abrasive and retain high-performance\, energy-efficiency\, ultra-large-scale-integration density as obtained in today’s state-of-the-art electronics. Often the transformed fabrics (ultra-thin version of the bulk thin film substrates with pre-fabricated devices) are semi-transparent due to the presence of the process originated vertical channels. As per ITRS 2014 metrics\, the processes are fully scalable down to 2 nm technology node. Using these techniques we have demonstrated high-κ/metal gate based planar and non-planar nano-scale (sub-20 nm) CMOS logic devices [Adv. Mater. 2014 (cover page)\, ACS Nano 2014\, APL 2013\, pss-RRL 2013 (cover pages)\, IEEE TED 2013\, pss-RRL 2013\, Sci. Rep. 2013\, pss-RRL 2013]\, memory [Adv. Electronic Mater. 2015\, Microelect. Engr. 2014]\, micro-scale thermoelectric generators [Small 2013 (frontispiece)]\, micro lithium ion batteries (150 μAh/cm2 normalized capacity)\, MEMS devices [MEMS 2014]\, smart thermal patch using copper stretched up to 800% [Adv. Healthcare Mater. 2015 (frontispiece)]\, mono-crystalline silicon stretched up to 1000% [APL 2014]. Variety of device demonstrations on wide range of inorganic thin films using this technique proves the efficiency and versatility of it. Our research greatly complements the $150M Flexible Hybrid Electronics Manufacturing Initiative (FHEMII) – recently introduced by the US Department of Defense: “Highly tailorable devices on flexible\, stretchable substrates that combined thinned CMOS components with components that are added via printing process”.\n \nView Details
URL:https://www.cecs.uci.edu/event/flexible-stretchable-reconfigurable-cmos-electronics-through-hybrid-integration-of-heterogeneous-materials-for-wearable-interactive-electronic-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
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