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DTSTART;TZID=America/Los_Angeles:20110602T150000
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UID:14264-1307026800-1307030400@www.cecs.uci.edu
SUMMARY:GoldMine: Automatic Assertion Generation and Achieving Test Coverage Closure
DESCRIPTION:GoldMine: Automatic Assertion Generation and Achieving Test Coverage Closure\n\n\n\n\nSpeaker\n\n\nProf. Shobha Vasudevan\nECE\, University of Illinois at Urbana-Champaign\nUrbana\, Illinois\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 4011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 2\, 2011\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAssertions are ubiquitous in the modern system design cycle. They are used in pre-Silicon verification\, post-Silicon validation and debug\, emulation\, reliability checking\, and many related functional assurance phases. Assertion generation is an intensely manual\, time-intensive task. GoldMine\, developed by my group in UIUC\, is an assertion generation software that uses a combination of data mining and static analysis of the design. GoldMine uses formal verification to guide the data mining algorithms. GoldMine assertions are attested by designers\, as adding value to the verification process. In the first part of my talk\, I will present the function and working of this engine\, as well as its recent application at the specification level.  \nCounterexample feedback from formal verification of an assertion can be used to grow the size of the data set that is mined by GoldMine. When iteratively applied\, this data set eventually captures the entire behavior. This data set now forms a test suite where coverage closure can be achieved. This algorithm for monotonically increasing coverage of validation inputs is presented in the second part of my talk. I will also discuss how GoldMine can be applied in the context of soft error detection and emulation.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nShobha Vasudevan is an assistant professor of Computer Engineering in the ECE Department\, at the Univ of Illinois. She obtained her PhD and MS degrees from the University of Texas at Austin. Her research interests are in design verification\, validation\, reliability\, software testing\, data mining and formal verification. She is a recepient of the 2010 NSF CAREER award and the YWCA leadership in Science award.
URL:https://www.cecs.uci.edu/event/goldmine-automatic-assertion-generation-and-achieving-test-coverage-closure/
LOCATION:CA
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20110603T150000
DTEND;TZID=America/Los_Angeles:20110603T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181236Z
LAST-MODIFIED:20231011T192031Z
UID:14256-1307113200-1307116800@www.cecs.uci.edu
SUMMARY:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund
DESCRIPTION:An Overview Over Research Activities at the Design Automation for Embedded Systems (DAES) Group at TU Dortmund\n\n\n\n\nSpeaker\n\n\nPeter Marwedel\nChair for Embedded Systems\nTU Dortmund/Informatik 12 + ICD\nDortmund\, Germany\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nRainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 3\, 2011\nRefreshments at 9:30 am\, Lecture begins at 10:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThe group headed by Dr. Marwedel focuses on the design of efficient embedded systems. The talk will provide an overview of the research performed in this group:  \n\nEmbedded systems connected to the physical environment must meet timing constraints. Typically\, timing verification is performed after software generation\, possibly leading to many design iterations until timing constraints are finally met. In order to avoid such loops\, compilers can be made timing-aware. An approach for such integration will be presented together with some results.\nThe next part of the talk will be about addressing the memory wall problem. In particular\, the use of energy-efficient and timing-predictable scratchpad memories will be presented. Results on the worst-case execution time aware compilation for an automotive application using scratchpad memories will be included.\nThe final part will cover other research projects in the DAES group. These include two projects of the collaborative research project on resource constrained machine learning (SFB 876). In the first project\, resource-efficient image analysis for an advanced real-time virus detector is the subject for design space exploration. The second project aims at speeding up the execution of programs written in R (a language frequently used for statistical analyses) by about two orders of magnitude\, thereby enabling more comprehensive statistical analyses\, particularly in life sciences. Another project addresses the problem of guaranteeing timeliness for systems based on unreliable hardware.
URL:https://www.cecs.uci.edu/event/an-overview-over-research-activities-at-the-design-automation-for-embedded-systems-daes-group-at-tu-dortmund/
LOCATION:CA
CATEGORIES:Seminars at CECS
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