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DTSTART;TZID=America/Los_Angeles:20101006T150000
DTEND;TZID=America/Los_Angeles:20101006T160000
DTSTAMP:20231011T192748Z
CREATED:20231011T181235Z
LAST-MODIFIED:20231011T192748Z
UID:14253-1286377200-1286380800@www.cecs.uci.edu
SUMMARY:Programming FPGA in C using ROCCC
DESCRIPTION:Programming FPGA in C using ROCCC\n\n\n\n\nPresenters\n\n\nJason Villarreal\, Adrian Park\, Roby Atadero\, and Walid Najjar\n\n\n\n \n\n\n \n\n\n\nCECS Host\n\n\nProfessor Fadi Kurdahi\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nCALit2 3008\, University of California\, Irvine\n\n\n\n \n\n\n \n\n\n\nDate & Time\n\n\nOctober 6\, 2010\nLight refreshments at 9:30am\, Tutorial begins 10:00am\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nROCCC (Riverside Optimizing Compiler for Configurable Computing) is a C to VHDL compilation framework specifically focused on FPGA-based code acceleration. Its focus is on compile time transformations and optimizations aimed at generating an efficient circuit from a loop nest. Its objectives are to maximize parallelism within the constraints of the target device\, optimize clock cycle time by efficient pipelining and minimize the area utilized. Furthermore\, ROCCC relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory. ROCCC 2.0 is a free and open source tool that supports a modular bottom-up approach to the programming of FPGA accelerators\, supporting code reuse at multiple levels while maintaining full compatibility with C. It has been ported to several platforms including Xilinx development boards and the Convey Computers HC-1.
URL:https://www.cecs.uci.edu/event/programming-fpga-in-c-using-roccc/
LOCATION:CA
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20101025T150000
DTEND;TZID=America/Los_Angeles:20101025T160000
DTSTAMP:20231011T182453Z
CREATED:20231011T182453Z
LAST-MODIFIED:20231011T182453Z
UID:14267-1288018800-1288022400@www.cecs.uci.edu
SUMMARY:Component-Based Design of Embedded Systems
DESCRIPTION:Component-Based Design of Embedded Systems\n  \n\n\n\n\nSpeaker\n\n\nProf. Hermann Kopetz\,\nUniversity of Vienna\, Austria\n\n\n\n\n\n\n\n\n\n\nCECS Hosts\n\n\nKane Kim\, Rainer Doemer\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nCalIT2 Room 3008\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 25 \, 2010\nLecture begins at 10:30 AM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn many engineering disciplines\, large systems are built from prefabricated components with known and validated properties. Components are connected via stable\, understandable\, and standardized interfaces. The system engineer has knowledge about the global properties of the components–as they relate to the system functions– and of the detailed specification of the component interfaces. Knowledge about the internal design and implementation of the components is neither needed\, nor available in many cases. Component-based design refers to a meet-in-the middle design methodology\, where\, starting from a purpose and requirements on one side and a set of available components on the other side a new design is produced that tries to satisfy the requirements by a proper interconnection of available and newly developed components. In this lecture we introduce the recursive component concept and the integration framework of the time- triggered architecture and demonstrate how the component-based design of embedded systems can be realized within this framework\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nHermann Kopetz received his PhD in physics sub auspiciis praesidentis from the University of Vienna\, Austria in 1968. After eight years in Industry he accepted in 1978 an appointment as a Professor for Computer Process Control at the Technical University of West-Berlin\, moving to the Technical University of Vienna in 1992. Kopetz is a full member of the Austrian Academy of Science\, Fellow of the IEEE\, and is a member of the Information Society Advisory Group (ISTAG)\, advising the European Commission in Brussels in the domain of Information Technology since 2008. In June 2007 he received the honorary degree of Dr. honoris causa from the University Paul Sabatier in Toulouse\, France. Kopetz is the chief architect of the Time-Triggered Architecture for dependable Embedded Systems and a co-founder of the company TTTech that has industrialized the time-triggered technology in many reputable projects\, among others in the Boeing 787 Dreamliner and the Audi A8 premium car.
URL:https://www.cecs.uci.edu/event/component-based-design-of-embedded-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
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