BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CECS
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REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20090308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20091101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20100314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20101107T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20110313T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20111106T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100803T150000
DTEND;TZID=America/Los_Angeles:20100803T160000
DTSTAMP:20231011T182656Z
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UID:14268-1280847600-1280851200@www.cecs.uci.edu
SUMMARY:Towards Practical High-Level Synthesis from Large Behavioral Descriptions
DESCRIPTION:Towards Practical High-Level Synthesis from Large Behavioral Descriptions\n\n\n\n\nSpeaker\n\n\nDr. Yuko Hara-Azumi\nNagoya University\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nNikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nAugust 3\, 2010\nLecture begins at 3:00PM \n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDue to the continuously increasing size and complexity of LSIs\, the traditional Register-Transfer Level (RTL) design with Hardware Design Languages (HDLs) is approaching its limit on design productivity. High-level synthesis\, which automatically synthesizes an RTL circuit from a behavioral description\, is expected as a promising solution to improve design productivity. However\, the LSI design has not been completely shifted from the traditional RTL design with HDLs to high-level synthesis yet since the quality of automatically synthesized RTL circuits through high-level synthesis can be inferior to that of human-designed ones\, which is especially serious for large designs.  \nThe goal of my work is to develop practical technologies of “high-level synthesis from large behavioral descriptions”. In this talk\, first\, one of my thesis works\, which revealed some problems in current technologies of high-level synthesis\, is briefly presented. Then\, previous/ongoing works which tackle with the problems are presented.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nYuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. Currently she is a research fellow of the Japan Society for the Promotion and Science at Nagoya University. Also\, she serves as a visiting researcher at Ritsumeikan University and University of California\, Irvine. Her research interests include high-level synthesis and compiler techniques.
URL:https://www.cecs.uci.edu/event/towards-practical-high-level-synthesis-from-large-behavioral-descriptions/
LOCATION:CA
CATEGORIES:Seminars at CECS
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