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DTSTART;TZID=America/Los_Angeles:20100611T150000
DTEND;TZID=America/Los_Angeles:20100611T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
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UID:14271-1276268400-1276272000@www.cecs.uci.edu
SUMMARY:The Inevitable Use of High Level Synthesis in Complex SoC Designs
DESCRIPTION:The Inevitable Use of High Level Synthesis in Complex SoC Designs\n\n\n\n\nSpeaker\n\n\nDr. Benjamin Schaefer\,\nNEC Research Lab\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nElaheh Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 413\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 11 \, 2010\nLecture begins at 11:00 am (Lecture Cancelled)\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nESL is becoming main stream when modeling complete SoCs in order to evaluate different architectural trade-offs and get some early performance estimates. These models are mainly described in SystemC. The central question that remains is if these models can ultimately be synthesized in order to further reduce the development cycle or if these models need to be manually described and integrated at the RT-level. This talk addresses how complete SoCs can be fully designed in C.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nBenjamin received his Ph.D from the University of Birmingham\, UK in 2003 \, where he investigated the acceleration of numerical intensive algorithms on reconfigurable computing platforms. He then moved to UCLA as a postdoctoral researcher working in the area of High Level synthesis and then moved to Seoul National University\, Korea where he worked on thermal estimation and reduction issues in VLSI circuits. Since 2007 he is with NEC’s Central Research Laboratory in Japan\, working on System and High Level Synthesis.
URL:https://www.cecs.uci.edu/event/the-inevitable-use-of-high-level-synthesis-in-complex-soc-designs/
LOCATION:CA
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20100615T150000
DTEND;TZID=America/Los_Angeles:20100615T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14270-1276614000-1276617600@www.cecs.uci.edu
SUMMARY:Secure VLSI Test Methods
DESCRIPTION:Secure VLSI Test Methods\n\n\n\n\nSpeaker\n\n\nDr. Ramesh Karri\nPolytechnic University\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nIan Harris\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 15 \, 2010\nRefreshments at 10:30 am; Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nDesign for Test (DFT) techniques improve access to the internal state of hardware either by improving control of internal nodes from the primary inputs or by improving observation of values on internal nodes at the primary outputs or both. On the other hand\, from a security perspective\, hardware should minimize controllability and observability of the internal state to a minimum. In this talk we will discuss our research on secure DFT architectures that reconcile Testability and Security.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nRamesh Karri is an Associate Professor in the Department of Electrical and Computer Engineering. Prof. Karri’s research interests are in the areas of secure hardware design\, computer-aided secure hardware design\, high-speed architectures for network protocols and encryption\, and computer-aided design of fault-tolerant nanoscale systems. \nProf. Karri is the recipient of an NSF CAREER award\, an Alexander Humboldt Fellowship and several grants including from the National Science Foundation\, the Air Force Research Labs and Army. Most recently\, Prof. Karri has been a co-PI with Program Director Nasir Memon on the just-awarded $2.124 million NSF grant from the National Science Foundation research and teaching of security and privacy issues on the Internet and other critical information infrastructure and is a founding member of the Center for Research in Interdisciplinary Studies in Security and Privacy at NYU. \nProfessor Karri received his MS in Computer Engineering at the University of California (1992)\, and his PhD in Computer Science also at the University of California (1993).
URL:https://www.cecs.uci.edu/event/secure-vlsi-test-methods/
LOCATION:CA
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100617T150000
DTEND;TZID=America/Los_Angeles:20100617T160000
DTSTAMP:20231011T182656Z
CREATED:20231011T182656Z
LAST-MODIFIED:20231011T182656Z
UID:14269-1276786800-1276790400@www.cecs.uci.edu
SUMMARY:Location and Time in Sensor Networks
DESCRIPTION:Automatic Design Space Exploration for Chip Multi-Processors\n\n\n\n\nSpeaker\n\n\nDr. Cristina Silvano\,\nPolitecnico di Milano\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nAlex Veidenbaum\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 17 \, 2010\nRefreshments at 10:30 am\, Lecture begins at 11:00 am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nGiven the increasing complexity of Chip Multi-Processors\, a wide range of architecture parameters (number of processors\, processor issue width\, L1 & L2 cache size\, etc.) must be tuned to find the best trade-off in terms of multiple metrics (energy\, delay\, bandwidth\, area\, etc.). Multi-Objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. Automatic Design Space Exploration is necessary to support systematically the exploration and the quantitative comparison in terms of multiple objectives. This talk addresses these problems by presenting MULTICUBE Explorer\, an open-source tool to support an automatic and fast optimization of configurable system-on-chip architectures towards a set of objective functions such as energy and delay. MULTICUBE Explorer provides a set of innovative sampling and optimization techniques to help finding the multi-objective Pareto points. Design of Experiments techniques are used to identify the experimentation plan where the set of tunable design parameters can vary. Response Surface Modeling techniques are used to obtain a response surface of the system behavior based on the set of data generated by DoE. MULTICUBE Explorer can also provide some support for run-time management of system resources.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n \nShe is an Associate Professor in Computer Engineering at Politecnico di Milano (Italy). Her primary research interests are in the area of Computer Architectures and Electronic Design Automation\, with particular emphasis on design space exploration techniques and low- power design techniques for multi-processor systems-on-chip. She is co-author of more than seventy scientific papers on international journals and conferences\, collecting one best paper award. She was co-author of the book: Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems\, published by Kluwer Academic Publisher (2003). She also holds some international patents. She participated to a number of national and international research projects. She is currently the European Coordinator of the on-going project FP7-MULTICUBE-216693 “Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications” (Jan. 2008 – June 2010). >From 2010\, she is also the Project Coordinator of the project FP7-2PARMA-248716 on “Parallel paradigms and run-time management techniques for many-core architectures.”
URL:https://www.cecs.uci.edu/event/location-and-time-in-sensor-networks/
LOCATION:CA
CATEGORIES:Seminars at CECS
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