BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
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REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20080309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20081102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20090308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20091101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20100314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20101107T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091214T150000
DTEND;TZID=America/Los_Angeles:20091214T160000
DTSTAMP:20231011T192949Z
CREATED:20231011T180835Z
LAST-MODIFIED:20231011T192949Z
UID:14246-1260802800-1260806400@www.cecs.uci.edu
SUMMARY:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases
DESCRIPTION:STP Engine\, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: its Architecture\, Tool\, and Real System Usecases\n\n\n\n\nSpeaker\n\n\nDr. Masato Motomura\,\nSystem IP Core Research Laboratories\, NEC Corporation\,\nJapan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\, University of California\, Irvine\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nDecember 14\, 2009\nRefreshments at 1:30pm; Talk begins 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nStream Transpose (STP) Engine is a programmable HW core to accelerate stream processing in modern system LSIs. It is composed of an array of numerous numbers of processing and memory elements as well as an intelligent data streaming HW mechanism. Key differentiation from other many-core type parallel architectures lies in its programming model: i.e.\, a design tool based on high-level HW synthesis technology compiles a C source code into a set of pseudo HW configurations which are spatially and temporally mapped onto the array. The STP engine is productized in 90nm-generation system LSIs\, and is targeted for wider-range use in forthcoming generations beyond 40nm.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Motomura received EE doctorial degree from Kyoto University in 1996. He has been engaged in research of various LSI architectures\, such as functional memories\, parallel processors\, and reconfigurable arrays in NEC research laboratories since 1987. From 2002 to 2009\, he led technology and business development of STP Engine in NEC Electronics. He was also the winner of 1992 IEEE JSSC Best Paper Award.
URL:https://www.cecs.uci.edu/event/stp-engine-a-c-based-programmable-hw-core-featuring-massively-parallel-and-reconfigurable-pe-array-its-architecture-tool-and-real-system-usecases/
LOCATION:CA
CATEGORIES:Seminars at CECS
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