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DTSTART;TZID=America/Los_Angeles:20091009T150000
DTEND;TZID=America/Los_Angeles:20091009T160000
DTSTAMP:20231011T192654Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192654Z
UID:14250-1255100400-1255104000@www.cecs.uci.edu
SUMMARY:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA
DESCRIPTION:Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA\n\n\n\n\nSpeaker\n\n\nProf. Lei He\nElectrical Engineering Department\,\nUCLA\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Eli Bozorgzadeh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nEngineering Hall (EH) 2430\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 9\, 2009\nRefreshments at 10:30am; Lecture begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nAs devices become smaller\, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired\, especially if no extra area\, power and delay and little change of the existing design flow are introduced. Using FPGA and internet router as a testbed\, this talk first presents fault tolerance techniques applying (1) logic don’t care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both increase MTTF by 2X with little or no overhead. Particularly\, IPR does not change circuit placement and routing\, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. Finally\, I will briefly discuss my ongoing research on cyber-physical systems involving renewal energy storage and environment/water monitoring.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nDr. Lei He is an associate professor at electrical engineering department\, UCLA\, and was a faculty member at University of Wisconsin\, Madison between 1999 and 2001. He also held visiting or consulting positions with Intel\, Hewlett-Package\, Cadence and Synopsys\, was a technical advisory board member for Rio Design Automation\, and Apache Design Solutions\, and is a guest professor at Fudan University (China) and China National Laboratory for Optoelectronics.  \nHis research interests include electronic design automation\, VLSI circuits and systems\, and cyber-physical systems. He has published one book and over 200 technical papers and has been a technical program committee member for a number of conferences including Design Automation Conference\, International Conference on Computer-Aided Design\, International Symposium on Low Power Electronics and Design\, International Symposium on Field Programmable Gate Array\, and International Symposium on Physical Design. Dr. He obtained Ph.D. degree in computer science from UCLA in 1999. He was granted National Science Foundation CAREER award in 2000\, UCLA Chancellor’s faculty career development award in 2003\, IBM Faculty Award in 2003\, Northrop Grumman Excellence in Teaching award in 2005\, best paper award at the 2006 International Symposium on Physical Design\, and multiple best paper nominations at Design Automation Conference and International Conference on Computer-Aided Design.
URL:https://www.cecs.uci.edu/event/power-efficient-and-fault-tolerant-circuits-and-systems-using-commodity-fpga/
LOCATION:CA
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20091019T150000
DTEND;TZID=America/Los_Angeles:20091019T160000
DTSTAMP:20231011T193148Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T193148Z
UID:14249-1255964400-1255968000@www.cecs.uci.edu
SUMMARY:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
DESCRIPTION:Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design\n\n\n\n\nSpeaker\n\n\nDr. Hiroshi Nakamura\nUniversity of Tokyo\, Japan\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 19 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nWe are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk\, we first briefly introduce the project\, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However\, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem\, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nHiroshi Nakamura received the BE\, ME\, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985\, 1987\, and 1990\, respectively. From 1990 to 1996\, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California\, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture\, VLSI design\, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.
URL:https://www.cecs.uci.edu/event/ultra-low-power-vlsi-through-co-optimization-of-architecture-and-circuit-level-design/
LOCATION:CA
CATEGORIES:Seminars at CECS
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091022T150000
DTEND;TZID=America/Los_Angeles:20091022T160000
DTSTAMP:20231011T192031Z
CREATED:20231011T181036Z
LAST-MODIFIED:20231011T192031Z
UID:14248-1256223600-1256227200@www.cecs.uci.edu
SUMMARY:A Virtualization-Based Software Architecture for Real-Time Embedded Systems
DESCRIPTION:A Virtualization-Based Software Architecture for Real-Time Embedded Systems\n\n\n\n\nSpeaker\n\n\nDr. Sung-Soo Lim\nAssistant Professor\,\nSchool of Computer Science\,\nKookmin University\,\nSeoul\, Korea\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Nikil Dutt\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nDonald Bren Hall (DBH) 3011\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nOctober 22 \, 2009\nRefreshments at 1:30 pm\, Lecture begins at 2:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nThis talk introduces an on-going work in Embedded Systems Laboratory\, Kookmin University to build next generation software architecture for mobile phones cooperating with Samsung Electronics. Future mobile phones need to accommodate both legacy applications and hard real-time communication protocols regardless of the underlying hardware organization. Such support for flexibility and reconfigurability should be accompanied with guarantee of reliability and security.  \nWe design and implement a light-weight hypervisor based on L4 microkernel for real-time embedded systems accommodating both general-purpose and hard real-time operating systems. The virtualization-based software architecture based on our hypervisor could have the reliability with zero-down feature and safety during dynamic software upgrade. We built a prototype smartphone platform running both Linux and uCOS-II on a single ARM11 core using the proposed software architecture. The structure and core techniques used in our software architecture will be introduced in the talk.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nSung-Soo Lim received BS\, MS\, and PhD degrees in Computer Engineering from Seoul National University in 1993\, 1995\, and 2002\, respectively. From 2000 to 2001\, he was a visiting researcher in University of Illinois at Urbana-Champaign. From 2001 to 2004\, he was the CTO of PalmPalm Technology\, Inc. in Korea (a smartphone development company). He is currently an assistant professor in School of Computer Science\, Kookmin University. His research area includes real-time operating systems\, real-time performance analysis\, low-power technology\, and mobile phone architecture.
URL:https://www.cecs.uci.edu/event/a-virtualization-based-software-architecture-for-real-time-embedded-systems/
LOCATION:CA
CATEGORIES:Seminars at CECS
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