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DTSTART;TZID=America/Los_Angeles:20050609T150000
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DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14295-1118329200-1118332800@www.cecs.uci.edu
SUMMARY:VLSI Design Methodologies Considering Fabrication Variability
DESCRIPTION:VLSI Design Methodologies Considering Fabrication Variability\n\n\n\n\nSpeaker\n\n\nProfessor Shrivastava \nDepartment of Electrical and Computer Engineering\nUniversity of Maryland\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Elaheh Bozorgzadeh\neli@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 127\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 9\, 2005\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nIn the past few years\, it has become clear that fabrication variability is one of the most important challenge that needs to be addressed for keeping the semiconductor industry profitable. Fabrication variability imposes an underlying uncertainty on the design process of VLSI chips making several parameters random. Therefore\, the old way of doing design needs to be overhauled for considering this randomness. This implies that VLSI CAD needs to incorporate probabilistic models for capturing uncertainty and stochastic optimization for controlling the design decision variables. Several challenges need to be addressed before this is made possible…\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nAnkur Srivastava received the B.S. degree from the Indian Institute of Technology\, Delhi\, the M.S. degree from Northwestern University\, Evanston\, IL\, and the Ph.D. degree from the University of California Los Angeles (UCLA) in 1998\, 2000\, and 2002. Since fall 2002 he has been an Assistant Professor with the University of Maryland\, College Park. His research interests include all aspects of design automation including logic and high-level synthesis\, low-power issues and predictability\, and low-power issues pertaining to sensor networks. Dr. Srivastava received the outstanding Ph.D. Award from the Computer Science Department of UCLA in 2002. He is a member of ACM and IEEE.
URL:https://www.cecs.uci.edu/event/vlsi-design-methodologies-considering-fabrication-variability/
LOCATION:CA
CATEGORIES:Seminars at CECS
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DTSTART;TZID=America/Los_Angeles:20050617T150000
DTEND;TZID=America/Los_Angeles:20050617T160000
DTSTAMP:20231011T192041Z
CREATED:20231011T180434Z
LAST-MODIFIED:20231011T192041Z
UID:14233-1119020400-1119024000@www.cecs.uci.edu
SUMMARY:Cutpoints for Formal Equivalence Verification of Embedded Software
DESCRIPTION:Cutpoints for Formal Equivalence Verification of Embedded Software\n\n\n\n\nSpeaker\n\n\nDr. Alan Hu\nDepartment of Computer Science\nUniversity of British Colombia\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 432\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nJune 17 \, 2005\nTalk begins at 9:30am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nLike hardware\, embedded software faces stringent design constraints\, undergoes extremely aggressive optimization\, and therefore has a similar need for verifying the functional equivalence of two versions of a design\, e.g.\, before and after an optimization. The concept of cutpoints was a breakthrough in the formal equivalence verification of combinational circuits and is the key enabling technology behind its successful commercialization. We introduce an analogous idea for formally verifying the equivalence of structurally similar\, “combinational” software\, i.e.\, software routines that compute a result and return/terminate\, rather than executing indefinitely. We have implemented a proof-of-concept cutpoint approach in our prototype verification tool for the TI C6x family of VLIW DSPs\, and our experiments show large improvements in runtime and memory usage.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nAlan Hu received his BS and PhD degrees from Stanford University . He is an associate professor and associate head of the Department of Computer Science at the University of British Columbia . For the past15 years\, his main research focus has been automated\, practical techniques for formal verification. He has served on the program committees of most major CAD and formal verification conferences\, and chaired or co-chaired CAV (1998)\, HLDVT (2003)\, and FMCAD (2004). He was also a Technical Working Group Key Contributor on the 2001 International Technology Roadmap for Semiconductors.
URL:https://www.cecs.uci.edu/event/cutpoints-for-formal-equivalence-verification-of-embedded-software/
LOCATION:CA
CATEGORIES:Seminars at CECS
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