BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20040404T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20041031T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20050403T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20051030T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20060402T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20061029T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050509T150000
DTEND;TZID=America/Los_Angeles:20050509T160000
DTSTAMP:20231011T183322Z
CREATED:20231011T183322Z
LAST-MODIFIED:20231011T183322Z
UID:14296-1115650800-1115654400@www.cecs.uci.edu
SUMMARY:Customizable Embedded Processor Architectures
DESCRIPTION:Customizable Embedded Processor Architectures\n\n\n\n\nSpeaker\n\n\nProfessor Orailoglu \nDepartment of Computer Science and Engineering\nUniversity of California\, San Diego\, CA\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Jean-Luc Gaudiot\ngaudiot@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nApril 14\, 2005\nRefreshments at 3:30 pm\, Lecture begins at 4:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nRecent advances in VLSI technology are resulting in ever more complex system-on-a-chip designs. Reduced time-to-market and low product cost requirements have been placing increased pressure upon designers to shift as much as possible of the system functionality onto a set of available microprocessor cores so as to reduce the hardware cost of the system and achieve faster time-to-market. Yet one of the fundamental difficulties in implementing larger parts of SOC functionality in software is the stringent timing constraints of the critical modules; methods need to be developed for matching such stringent constraints if embedded processor cores are to be widely used. Low-cost\, application-specific microarchitecture customizations promise to be an efficient solution to this problem. The basic advantage of microprocessor cores versus ASICs is the intrinsic reconfiguration capability of the processor by means of software. In order to preserve this fundamental advantage\, application-specific features added to the microarchitecture need to be implemented as reprogrammable hardware. Post-manufacturing customization capability can thus provide seamless migration to new applications possibly due to late specification changes or market requirements\, while delivering superior levels of performance. In this talk\, we outline the incorporation of application specific properties into the processor microarchitecture\, thus increasing performance and reducing power consumption. The fundamental approach is the identification of application properties during compile time and their dynamic exploitation during program execution by the processor. The basic characteristic of these properties is that their existence can be statically identifiable by the compiler\, and that they can lead to significant improvements in performance when exploiting their behavior dynamically. Such properties may consist of the control structure of the algorithm\, the run-time data values and the code manipulating some data structures; for example\, an array access\, its stride\, or its control structure. Microarchitectural features that can be enhanced with such application-specific information include the branch predictor\, the cache subsystem\, and the processor communication infrastructure; techniques aimed at all three are outlined in this talk.\ndownload pdf\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n\nAlex Orailoglu received his BS Degree cum laude from Harvard University in Applied Mathematics and his M.S. and Ph.D. degrees in Computer Science from the University of Illinois \, Urbana-Champaign. Alex Orailoglu is currently a Professor of Computer Science and Engineering at the University of California \, San Diego . His research interests include Embedded Systems and Processors\, digital and analog test\, fault tolerant computing\, Computer-Aided Design\, and nanoelectronics.\n\n\n\nCustomizable Embedded Processor Architectures\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/customizable-embedded-processor-architectures/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20050513T150000
DTEND;TZID=America/Los_Angeles:20050513T160000
DTSTAMP:20231011T192748Z
CREATED:20231011T180435Z
LAST-MODIFIED:20231011T192748Z
UID:14234-1115996400-1116000000@www.cecs.uci.edu
SUMMARY:Practical Considerations for Power-Aware Real-Time Scheduling
DESCRIPTION:Continuous Compilation for Aggressive and Adaptive\nCode Transformation\n\n\n\n\nSpeaker\n\n\nDr. Bruce Childers\nDepartment of Computer Science\nUniversity of Pittsburgh\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nIERF Conference Room 127\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMay 13 \, 2005\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOver the past several decades\, the compiler research community has developed a number of sophisticated and powerful algorithms for a variety of code improvements. Although there are still promising directions for particular aspects of code optimization\, research on optimizations is nearing the point of diminishing returns and other approaches are needed to achieve further performance improvements. Our research aims to address this challenge by investigating and developing an innovative framework and system for continuously and adaptively applying code improvements. Our system\, the Continuous Compiler ( CoCo )\, determines “optimization plans” at compile-time that describe the best way in which to apply both static and dynamic code transformations. The plans consider program and machine context\, interaction among optimizations\, and performance profit. Through such planning\, CoCo can tailor and adapt its decisions to more synergistically apply a whole suite of code transformations.  \nThis talk will describe the Continuous Compilation approach and present initial results. These results include novel analytic models that can accurately predict the performance benefit (profit) of applying an optimization without actually doing it or running the resulting program code. Using the analytic models\, we have developed several planners that can guide a static optimizer. Initial results are very encouraging and show that optimizations can be effectively directed by planning. The talk will conclude with a brief discussion of CoCo ‘s run-time system\, including its dynamic code translator\, instrumentation optimizer\, and source-level debugger for dynamically translated code.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n  \n \nBruce Childers is an Assistant Professor in the Department of Computer Science at the University of Pittsburgh. Dr. Childers received a BS degree (Computer Science\, 1991) from the College of William and Mary\, and a PhD degree (Computer Science\, 2000) from the University of Virginia. His research interests are compilers and software development tools\, computer architecture\, and embedded systems. Current projects include continuous compilation to synergistically apply both static and dynamic code optimizations\, debugging for dynamically translated code\, power-aware real-time systems\, and demand-driven software testing.
URL:https://www.cecs.uci.edu/event/practical-considerations-for-power-aware-real-time-scheduling-2/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR