BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.cecs.uci.edu
X-WR-CALDESC:Events for CECS
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20030406T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20031026T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20040404T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20041031T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20050403T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20051030T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20040322T150000
DTEND;TZID=America/Los_Angeles:20040322T160000
DTSTAMP:20231011T183336Z
CREATED:20231011T183336Z
LAST-MODIFIED:20231011T183336Z
UID:14300-1079967600-1079971200@www.cecs.uci.edu
SUMMARY:Bluespec: Why chip design can't be left to EE's
DESCRIPTION:Lecture Slides \nBluespec: Why chip design can’t be left to EE’s\n\n\n\n\nSpeaker\n\n\nProfessor Arvind\nCSAIL (formerly LCS and AI Lab)\nMassachusetts Institute of Technology\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nMarch 22\, 2004\nRefreshments at 2:30pm\, Lecture begins at 3:00pm\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nHundred million-gate ASICs are possible by the end of the decade. However\, numerous problems related to process technology and design need to be solved before such large chips will become commonplace. Computer scientists are much better equipped to solve the new problems related to the design-in-the-large. Bluespec is a language/methodology that promotes correctness-by-construction. Its underlying execution model is based on atomic actions on state elements (such as flip-flops\, registers\, …)\, i.e.\, any legal behavior is explainable in terms of a sequence of atomic actions on the state. Expressiveness of Bluespec is achieved by keeping its static semantics orthogonal to its hardware execution semantics — the source program is turned into a flat interconnection of modules by “static elaboration” during the compile phase.This talk will present Bluespec via examples and show some of the designs done so far.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\n\n\nArvind is the Johnson Professor of Computer Science and Engineering at the Massachusetts Institute of Technology. His work at MIT on high-level specification\, modeling\, synthesis and verification of architectures and protocols using Term Rewriting Systems (TRSs) laid the foundations for Sandburst and more recently Bluespec Inc. Previously\, he contributed to the development of dynamic dataflow architectures\, and together with Dr R.S.Nikhil published the book “Implicit Parallel Programming in pH”. Arvind is an IEEE Fellow and was awarded the Charles Babbage Outstanding Scientist Award in 1994. He has received the Distinguished Alumni Awards from the Indian Institute of Technology\, Kanpur\, and the University of Minnesota.\n\n\n\nBluespec: Why chip design can’t be left to EE’s\nclick on the thumbnails to view the full-sized images
URL:https://www.cecs.uci.edu/event/bluespec-why-chip-design-cant-be-left-to-ees/
LOCATION:CA
CATEGORIES:Seminars at CECS
END:VEVENT
END:VCALENDAR