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DTSTART;TZID=America/Los_Angeles:20040206T150000
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DTSTAMP:20231011T183337Z
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UID:14301-1076079600-1076083200@www.cecs.uci.edu
SUMMARY:Embedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond
DESCRIPTION:Lecture Slides \nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\nSpeakers\n\n\nJonathan R. Haigh and Michael W. Wilkerson\n\n\n\n\n\n\n\n\n\n\nCECS Host\n\n\nProfessor Alex Veidenbaum\nalexv@ics.uci.edu\n\n\n\n\n\n\n\n\n\n\n\nLocation\n\n\nMcDonnell Douglas Auditorium\n\n\n\n\n\n\n\n\n\n\nDate & Time\n\n\nFriday\, February 6\, 2004\nRefreshments at 10:30am\, Seminar begins at 11:00am\n\n\n\n\n\n\n\n\n\n\nAbstract\n\n\nOptimizing power consumption is a primary goal in the design of embedded microprocessors even as the push for higher performance continues.  Managing the microprocessor’s power dissipation while still striving to push the design into GHz speeds provides a significant challenge.  As designs move to 90 nm and beyond\, device scaling has reduced oxide thicknesses and V T to the point where standby leakage power is on the same order of magnitude as active power.  Today’s successful designs need to aggressively manage both active and standby currents.  A collection of methods to control both active and leakage power in Cache and Translation Lookaside Buffer (TLB) circuits\, while minimizing the impact to performance\, will be discussed.\n\n\n\n\n\n\n\n\n\n\nBiography\n\n\nJonathan R. Haigh: \nJon is the lead L1 cache designer for the current generation of XScale products.  He began his EE career at GE in 1996 followed by the former Digital Semiconductor in 1998.  He joined Intel Corporation in 2000 and has been working on the XScale cache circuit design team since joining the company.  He received his B.S. degree in Electrical Engineering concentrating in VLSI design from the University of Cincinnati .Michael W. Wilkerson: \nMike received the B.S. and M.S. degrees in electrical engineering from the University of Florida in 1991 and 1997.  He was in the U.S. Navy from 1983 to 1996 and joined Intel Corporation in 1998.  He has worked in logic verification and VLSI circuit design for Itanium and XScale microprocessors while at Intel.  He most recently completed the physical design of the data path memory management unit\, which includes a TLB structure\, for a new XScale core.\n\n\n\nEmbedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond\n\n\n\n\n\n\n\nclick on the thumbnails to view the full-sized images\n\n\n\n\n\n\nThe lecture was held at the McDonnell Douglas Auditorium\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh and Mike Wilkerson are members of the team designing the Intel XScale embedded processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon and Mike chatting with CECS students before delivering their talk. Professor Alex Veidenbaum\, left background\, hosted the event.  \nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nMike Wilkerson discussing embedded processor design challenges. At 90 nm\, it is important to employ architectural techniques that emphasize power reduction.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nJon Haigh explaining cache memory design strategies for the XScale processor.\nview larger image\n\n\n\n\n\n\n\n\n\n\n\n\n\nA lively Q & A session followed the presentation.\nview larger image
URL:https://www.cecs.uci.edu/event/embedded-microprocessor-cache-and-translation-lookaside-buffer-tlb-low-power-circuit-techniques-for-90nm-and-beyond/
LOCATION:CA
CATEGORIES:Seminars at CECS
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