BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://www.cecs.uci.edu X-WR-CALDESC:Events for CECS REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20020407T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20021027T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20030406T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20031026T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20040404T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20041031T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20050403T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20051030T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20060402T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20061029T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20070311T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20071104T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20080309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20081102T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20090308T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20091101T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20100314T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20101107T090000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090603T150000 DTEND;TZID=America/Los_Angeles:20090603T160000 DTSTAMP:20231011T183716Z CREATED:20231011T183716Z LAST-MODIFIED:20231011T183716Z UID:14321-1244041200-1244044800@www.cecs.uci.edu SUMMARY:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors DESCRIPTION:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors\nby Ashok Halambi \nLocation: DBH 4013 \nDate and Time: June 3\, 2009 2:00pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Alex Nicolau\nProfessor Alex Viedenbaum \nAbstract:\nEmbedded systems continue to increase in functionality\, complexity and connectivity. Programmable platforms\, consisting of processors programmable in software\, are a popular solution to satisfy the design constraints (such as cost\, performance\, flexibility\, reliability etc.) of such systems. Key challenges in the design of programmable platforms include compiler-in-loop design space exploration (DSE)\, and automatic generation of software toolkit for hardware/software co-design. \nA language-based model of the processor-memory subsystem has several benefits: it serves as a golden reference model for all principals involved in the design; it can be used to drive DSE and automatic software toolkit generation; it can be used to perform top-down (formal) verification and validation; and\, it can be refined down to implementation (register-transfer level). In this dissertation\, we present EXPRESSION\, an architecture description language (ADL) that is designed for DSE of processor-memory sub-system and automatic generation of software toolkit including compiler and cycle-accurate simulator. EXPRESSION has been used to describe various processors from RISC (DLX\, MIPS R4000\, ARM 9)\, VLIW (TI C6x)\, DSP (ST100)\, etc. Our EXPRESSION based DSE methodology permits exploration of a wide range of processor architectures\, and includes compiler-in-loop for accurate analysis of each design configuration. \nTo aid compiler-in-loop DSE\, we developed EXPRESS\, a retargetable\, instruction level parallelizing compiler that accepts programs in “C” and produces assembly code for the target processor described in EXPRESSION. The EXPRESS compiler is capable of handling irregular architectures\, and can adapt to changes in the processor’s instruction-set or micro-architecture. EXPRESS also includes a framework for dynamic customization of the compiler based on the target application and architecture characteristics. These capabilities of EXPRESS make it ideal for use in the DSE of processor-memory subsystems. \nRetargetable compilers suffer from the drawback of poor output code quality as compared to a compiler that is “hand-crafted” for the target processor. Key differences between the two compilers include the presence of target specific optimizations and custom phase ordering of optimization passes in the target specific compiler. In this dissertation\, we propose a framework\, called TransMutations\, that enables dynamic\, run-time customization of a retargetable compiler. It allows for easy integration of optimizations (called mutations) into the compiler and solves the phase ordering problem by applying optimizations in a context-sensitive manner for each region of the application code. The TransMutations framework has been implemented in the EXPRESS compiler and we present results demonstrating the effectiveness of the technique. This framework improves the quality of code generated by retargetable compilers and enables them to be used in accurate compiler-in-loop DSE of programmable embedded systems. URL:https://www.cecs.uci.edu/event/transmutations-a-framework-for-dynamic-customization-of-retargetable-compilers-for-embedded-processors/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090529T150000 DTEND;TZID=America/Los_Angeles:20090529T160000 DTSTAMP:20231011T183716Z CREATED:20231011T183716Z LAST-MODIFIED:20231011T183716Z UID:14322-1243609200-1243612800@www.cecs.uci.edu SUMMARY:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement DESCRIPTION:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement\nby Aseem Gupta \nLocation: DBH 3011 \nDate and Time: May 29\, 2009 1:30pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Fadi Kurdahi\nProfessor Tony Givargis \nAbstract:\nProcess scaling and shrinking device geometries have resulted in chips with greater performance and complexity levels. However\, these advancements have come at the cost of higher power densities and increased operating temperatures. The inability to control the operating temperatures by existing cooling techniques is the principal reason for discontinuation of an increase in frequencies and introduction of multi-core architectures. Apart from operability\, high temperatures have unfavorable consequences such as: increased leakage power\, reduced interconnect life time\, slowing of interconnects and transistors\, need for expensive package and cooling mechanisms\, and increased manufacturing cost and design effort. Traditionally\, thermal issues have been examined only at the post-synthesis stages of the design flow. This thesis attempts to migrate the “thermal awareness” from the physical level design phase to early stages of the VLSI design flow and utilize it to target various design metrics such as power\, performance\, reliability\, and operability. This thesis advances the procedure of leakage power estimation by coupling it with thermal profile estimation and capturing the positive interdependence between temperature and leakage power. It also advances the traditional role of communication architecture to that of an active thermal manager. The proposed communication architecture based thermal manager delays the execution of chosen components by regulating the flow of data over the on-chip communication fabric. This dissertation demonstrates the need of examining the effects of frequency\, supply voltage\, power dissipation\, and temperature on SRAM reliability in a mutually interrelated manner. Our observation contradicts the conventional belief that increasing supply voltage always reduces the failure rate in SRAMs. Because of thermal effects\, an increase in the supply voltage can also lead to increase in the SRAM failure rate. This thesis also extends the procedure of system level floorplanning to manage the leakage power and reliability of the design. The fundamental contribution of this thesis is that it advances the traditional design flow in the direction of incorporating thermal awareness during various stages of the flow. URL:https://www.cecs.uci.edu/event/temperature-aware-vlsi-design-for-reduced-power-and-reliability-enhancement/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090527T150000 DTEND;TZID=America/Los_Angeles:20090527T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14323-1243436400-1243440000@www.cecs.uci.edu SUMMARY:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems DESCRIPTION:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems\nby Gabor Madl \nLocation: DBH 3011 \nDate and Time: May 27\, 2009 10:00am \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Tony Givargis\nProfessor Ian Harris \nAbstract:\nAs embedded systems become increasingly networked\, and interact with the physical world\, Distributed Real-time Embedded (DRE) systems emerge. DRE systems range from small-scale Multi-processor Systems-on-Chip (MPSoCs) operating in resource constrained environments such as cell phone platforms\, medical devices and sensor networks all the way to large-scale software-intensive systems of systems used in avionics\, ship computing environments\, and in supervisory control and data acquisition systems managing regional power grids. \nThis dissertation focuses on the model-based analysis of event-driven DRE systems. Event-driven DRE systems are based on a reactive communication paradigm\, where the execution of tasks is triggered asynchronously\, invoked by external events\, interrupts\, or by other tasks. Events can also express time\, providing a common semantic domain for the compositional analysis of time- and event-driven DRE systems. \nThe key technical contributions of this dissertation are (1) the specification of a formal semantic domain for DRE systems\, (2) a model checking method for the real-time verification of non-preemptive DRE systems using timed automata\, (3) a performance estimation method for DRE systems by discrete event simulations\, (4) a conservative approximation method for the verification of preemptive event-driven asynchronous DRE systems by timed automata\, (5) a method for the functional verification and performance estimation of MPSoCs built on an industry standard interconnect\, and (6) a cross-abstraction real-time analysis method for MPSoC designs utilizing bus matrix interconnects. \nThe novelty of our approach lies in combining formal methods and symbolic simulations for the system-level evaluation of DRE designs early in the design flow\, and utilizing multiple abstractions to trade off analysis accuracy in scalability. \nWe implemented the proposed analysis methods in the open-source Distributed Real-time Embedded Analysis Method (DREAM) framework for the model-based real-time verification and performance estimation of DRE systems. DREAM focuses on the practical application of formal analysis methods to automate the verification\, development\, configuration\, and integration of event-driven DRE systems. DREAM is available for download at http://dre.sourceforge.net. We applied the proposed design flow to the domain of software-intensive mission-critical avionics DRE applications\, and the domain of multimedia MPSoCs. URL:https://www.cecs.uci.edu/event/model-based-analysis-of-event-driven-distributed-real-time-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090227T150000 DTEND;TZID=America/Los_Angeles:20090227T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14324-1235746800-1235750400@www.cecs.uci.edu SUMMARY:Automatic Design and Optimization of Application Specific Processors DESCRIPTION:Automatic Design and Optimization of Application Specific Processors\nby Jelena Trajkovic \nThe stringent performance and power requirements of modern applications have fueled the need for application specific computing platforms. Conventional general purpose embedded processor do not provide the necessary throughput for meeting the applications’ performance and power needs. On the other hand\, manual hardware design is too expensive and results in inflexible implementation. The short time to market demands also make hardware design prohibitive. Therefore\, there exists a need for automatic design methods and tools that provide a high performance\, programmable and energy-efficient implementation starting from standard application descriptions such as C reference code. High level synthesis and application specific processor tools are a step in this direction\, but suffer from scalability\, quality and controllability issues. In this dissertation\, we present techniques for automatic processor design from C code that are scalable to thousands of lines of C code\, are controllable at each step of the design process and provide quality of results comparable to manual design. \nOur contributions enable a system level design methodology for application specific processors that starts with a reference C code of the application. An initial processor data path is constructed from a database of available components such as function units\, register files and buses. The initial data path is based on the types of operations and available concurrency in the application. The data path is then iteratively refined until an efficient architecture is derived. The key optimization goal is to keep performance within given boundaries while maximizing resource utilization. We further optimize the processor design using a novel algorithm for automatic custom pipelining based on the C code. The pipelining optimization also targets both resource utilization and performance. Our experimental results with large applications such as DCT and MP3 decoder show that automatically generated architectures are comparable to manual designs\, but can be obtained in a matter of few seconds\, leading to significant productivity gains. \nOur final contribution to design methods for embedded systems deals with low power memory design. Typically\, DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high\, exceeding that of the data cache or even that of the processor. We present and evaluate a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small\, cache-like structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption\, 23%\, on average\, and reduction in the energy-delay product\, 44%\, on average. The approach also improves performance: the CPI is reduced by 26%\, on average. URL:https://www.cecs.uci.edu/event/automatic-design-and-optimization-of-application-specific-processors/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080709T150000 DTEND;TZID=America/Los_Angeles:20080709T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14325-1215615600-1215619200@www.cecs.uci.edu SUMMARY:Improving Packet Latencies of Live Streams in Wired Networks DESCRIPTION:Improving Packet Latencies of Live Streams in Wired Networks\nby Arijit Ghosh (Advisor: Prof. Tony Givargis)\nDate: July 9\, 2008 \nLive streaming is becoming increasingly popular. In a study published in January 2008\, Cisco predicted that Internet-to-TV video will account for 30% of all Internet traffic. If all kinds of video traffic are considered\, then it will be 90% of consumer traffic by 2012. We distinguish live streams from on demand streams. Live streams are sent as the data is being generated\, is typically of long duration\, requires high bandwidth and associated with flash crowd behavior. As such\, live streams place tremendous demand on network resources. \nIn this thesis\, we proposed network techniques to improve packet latencies of live streams in wired networks. In particular\, we made the following contributions. First\, we proposed a technique that allows multicasting at the access network\, the proverbial last mile which presents tremendous bandwidth limitations. Second\, we reduced nodal processing by a tunelling scheme based on source routing. Essentially\, using routing computed at source and a novel network encoding scheme\, we eliminated intermediate processing. Third\, we presented a queueing algorithm that schedules packets based on application deadlines\, reduces the number of sorting iterations\, thereby improving performance\, has low complexity\, exhibits good fairness and provides a bounded delay for a single packet that is independent of the number of flows. Finally\, we proposed a variation of QoS routing that works with only partial network state information. URL:https://www.cecs.uci.edu/event/improving-packet-latencies-of-live-streams-in-wired-networks/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080708T150000 DTEND;TZID=America/Los_Angeles:20080708T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14326-1215529200-1215532800@www.cecs.uci.edu SUMMARY:xTune: A Formal Methodology for Cross-layer Tuning of Mobile Real-time Embedded Systems DESCRIPTION:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems\nby Minyoung Kim (Advisor: Prof. Nikil Dutt)\nDate: July 8\, 2008 \nResource limited mobile real-time embedded systems can benefit greatly from  dynamic adaptation of system parameters. This thesis proposes a novel framework  xTune that employs iterative tuning using light-weight formal verification at runtime with feedback for dynamic adaptation. One objective of this approach is to enable tradeoff analysis across multiple layers (for example\, application\, middleware\, operating system) and predict the possible property violations as the system evolves dynamically over time. Specifically\, an executable formal specification is developed for each layer of the mobile real-time system under consideration. The formal specification is then analyzed using statistical model checking and statistical quantitative analysis\, to determine the impact of various resource management policies for achieving desired a variety of end-to-end properties in a quantifiable manner. The integration of formal analysis with dynamic behavior from system execution results in a feedback loop that enables model refinement and further optimization of policies and parameters. Finally\, we propose a composition method for coordinated interaction of optimizers at different layers. The core idea of our approach is that each participating optimizer can restrict its own parameters and exchange refined parameters with its associated layers. We demonstrate the applicability of the proposed methodology to the adaptive provisioning of mobile real-time embedded systems by treating a multimedia case study on resource-limited devices. URL:https://www.cecs.uci.edu/event/xtune-a-formal-methodology-for-cross-layer-tuning-of-mobile-real-time-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080616T150000 DTEND;TZID=America/Los_Angeles:20080616T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14327-1213628400-1213632000@www.cecs.uci.edu SUMMARY:A Runtime System for Memory-Constrained Distributed Embedded Systems DESCRIPTION:A Runtime System for Memory-Constrained Distributed Embedded Systems\nby Jiwon Hahn (Advisor: Prof. Pai Chou)\nDate: June 16\, 2008 \nWearable and embedded wireless sensor platforms are often highly constrained in size and power consumption in order to operate in unintrusive ways. To meet these constraints\, the memory is kept as small as possible to reduce area and power\, but at the same time it poses new challenges on programming. To address these problems\, this dissertation proposes \n(1) a framework for synthesis of host-assisted scripting engines\, \n(2) a minimum-overhead yet powerful runtime system based on recursive threaded code\, and \n(3) a host-assisted memory optimization technique that exploits high-level knowledge in models of computation. The benefits are three-fold: first\, the interactive access between programmer and embedded system improve productivity of programmers. Second\, the low runtime overhead and memory requirements enable this runtime system to run on compact platforms while providing high flexibility and composability. Third\, a new memory optimization scheme combined with the dispatching structure expose regularity of dataflow models to enable memory and scheduling optimizations\, sometimes in ways better than manual coding. \nExperimental results show that systems developed using these techniques have unleashed the power of these resource-constrained distributed embedded systems. As memory is currently the limiting factor\, the lightweight runtime system and systematic memory optimization technique presented in this dissertation are enabling technology for a new class of real-world\, ultra-compact distributed embedded systems. URL:https://www.cecs.uci.edu/event/a-runtime-system-for-memory-constrained-distributed-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080604T150000 DTEND;TZID=America/Los_Angeles:20080604T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14328-1212591600-1212595200@www.cecs.uci.edu SUMMARY:Source Re-coding to Create Parallel and Flexible MPSoC Models for Embedded System Design and Exploration DESCRIPTION:by Pramod Chandraiah\, University of California\, Irvine\nJune 4\, 2008\nview details URL:https://www.cecs.uci.edu/event/source-re-coding-to-create-parallel-and-flexible-mpsoc-models-for-embedded-system-design-and-exploration/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080512T150000 DTEND;TZID=America/Los_Angeles:20080512T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14329-1210604400-1210608000@www.cecs.uci.edu SUMMARY:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip DESCRIPTION:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip\nby Sudeep Pasricha (advisor: Prof. Nikil Dutt)\nDate: May 12\, 2008 \nWith the increasing performance demands of emerging convergence applications and advances in process technology\, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance\, power\, cost and reliability. Consequently\, the design\, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today. \nIn this dissertation\, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis\, comprehensively and automatically generating both the topology and protocol parameters\, while trading off multiple design constraints such as power\, performance\, area and cost.Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality\, better complexity management\, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs. URL:https://www.cecs.uci.edu/event/commsyn-on-chip-communication-architecture-synthesis-for-multi-processor-systems-on-chip/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080303T150000 DTEND;TZID=America/Los_Angeles:20080303T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14330-1204556400-1204560000@www.cecs.uci.edu SUMMARY:Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design DESCRIPTION:by Gunar Schirner\, University of California\, Irvine\nMarch 3\, 2008\nview details URL:https://www.cecs.uci.edu/event/analysis-and-optimization-of-transaction-level-models-for-multi-processor-system-on-chip-design/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20071206T150000 DTEND;TZID=America/Los_Angeles:20071206T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14331-1196953200-1196956800@www.cecs.uci.edu SUMMARY:Synthesis and Optimization of Low-Power Custom NISC Processors DESCRIPTION:by Bita Gorjiara\, University of California\, Irvine\nDecember 6\, 2007\nview details URL:https://www.cecs.uci.edu/event/synthesis-and-optimization-of-low-power-custom-nisc-processors/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070920T150000 DTEND;TZID=America/Los_Angeles:20070920T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14332-1190300400-1190304000@www.cecs.uci.edu SUMMARY:Software Architecture for High Data Rate Wireless Body Sensor Applications DESCRIPTION:Software Architecture for High Data Rate Wireless Body Sensor Applications\nby Seung-Mok Yoo \nFor wireless body area sensor networks\, the wearable nodes are highly constrained by low power\, low cost\, and small size while deliverly high throughput and low latency in a multiple access environment. To accomplish these goals\, the hardware must be kept simple\, and as a result\, the traditional abstractions with separate layers of the protocol stack and application must be merged and made as streamlined as possible. This dissertation identifies and removes two bottlenecks with data transfers: one is between the base station and its sensor nodes\, and the other is within the sensor node. \nFirst\, we propose a thin-server\, fat-client architecture. It supports a pulling protocol that achieves intra-network collision-free multiple access as in TDMA but without the time synchronization overhead. It also achieves high data throughput of air bandwidth and adaptivity of CSMA protocols but without collision or complexity on the node side. \nSecond\, for intra-node transfers\, another known bottleneck is the system bus. We identify the double-transaction problem\, which is common to SPI\, DMA\, and other interfaces. We propose the Master-Handoff Protocol to eliminate the redundant transaction and improve latency significantly\, and it is compatible with existing controllers. It not only halves the data transfer time but also achieves energy reduction. Together\, these techniques enable highly constrained hardware to meet strict size and power constraints for high wearability without sacrificing performance. URL:https://www.cecs.uci.edu/event/software-architecture-for-high-data-rate-wireless-body-sensor-applications/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070918T150000 DTEND;TZID=America/Los_Angeles:20070918T160000 DTSTAMP:20231011T184245Z CREATED:20231011T184245Z LAST-MODIFIED:20231011T184245Z UID:14333-1190127600-1190131200@www.cecs.uci.edu SUMMARY:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract DESCRIPTION:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract\nby Mehrdad Reshadi \nToday\, depending on the size and complexity of a program\, there are two options for synthesizing a program to hardware: (1) using High Level Synthesis (HLS)\, and (2) using Application-Specific-Instruction-Processor (ASIP). \nTraditional HLS techniques can only support relatively small applications and do not give enough control to the designer over the quality of results. Poor quality of results and limited application domain has prevented the HLS from wide spread usage. \nEmbedded processors often run only one or a few applications in the life-time of the system. Therefore\, they can be customized for the target applications and significantly improve the quality of the embedded system in terms of cost\, performance\, power consumption\, etc. This is the goal in ASIP approaches. Instruction-based architectures limit the customizations because: (a) hardware designer is limited by instruction coding\, size and complexity of the decoder; (b) compilers can support certain class of instructions and hence instructions cannot be very complex; and (c) manually updating compilers to incorporate the custom instructions is not practical and developing compilers that automatically utilize hardware customizations through new custom instructions is very complex. \nIn this talk I present a new design approach called NISC (No-Instruction-Set-Computer) Technology. In NISC\, the datapath and controller are generated in two different phases. First the datapath is generated or selected from a database based on the application behavior. At the core of NISC technology\, there is a cycle-accurate compiler that maps a given application directly on a given datapath and generates the control words (CWs) that control the datapath resources in every clock cycle. The NISC architecture style is similar to the old nanocode machines. However\, instead of using nanocodes inside the process for implementing the microcodes and in turn instructions\, in NISC the nanocode (CWs) are directly used to program the datapath. \nNISC simplifies customization and allows designer to fully control design quality. NISC simplifies ASIP (Application-Specific-Instruction-Processor) approach by removing the complex task of finding and designing “most profitable” custom instructions. In NISC only the datapath needs to be specified and NISC compiler generates code “as if” each basic block of the program is executed with one custom instruction. On the other hand\, NISC improves resource constrained HLS techniques by adding the connectivity constraints\, on top of the traditional resource constraints\, into synthesis process. This enables the designer to control every thing in datapath including wires\, which are becoming increasingly more critical in newer technologies. In fact NISC combines the ASIP and HLS techniques. \nTo realize the NISC Technology design flow\, several challenging categories of problems must be solved. Mainly we need: \n1. Techniques for efficiently designing and customizing a datapath for an application\n2. Techniques for efficiently compiling any application on any given datapath\n3. Techniques for efficiently synthesizing a controller from the output of compiler and then generating synthesizable code for different target implementations. \nIn my thesis\, I focus on the compilation problems to enable practical use of NISC IPs in a system. A working compiler and other NISC tools are available for public use from NISC websitehttps://www.cecs.uci.edu/~nisc/. An online version of the tools can be also directly accessed at this website. URL:https://www.cecs.uci.edu/event/no-instruction-set-computer-nisc-modeling-and-compilation-abstract/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070423T150000 DTEND;TZID=America/Los_Angeles:20070423T160000 DTSTAMP:20231011T184245Z CREATED:20231011T184245Z LAST-MODIFIED:20231011T184245Z UID:14334-1177340400-1177344000@www.cecs.uci.edu SUMMARY:Software for Embedded Systems: Serializing Compilers and Its Applications DESCRIPTION:Software for Embedded Systems: Serializing Compilers and Its  Applications\nby Andre Costi Nacul \nIn order to cope with the complexity of systems\, engineers are  turning to software. In part\, well established programming models\,  highly evolved tool chains\, ease of software reuse\, availability of  open-source software\, and expeditious nature of the design-compile- execute paradigm make developing a new feature in software more  favorable. It is assumed that\, in coming years\, more than 70% of  product features are going to be supported by software.\nIn particular\, the concurrent programming paradigm is an ideal model  of computation for design of embedded systems\, which often encompass  inherent concurrency. The support for concurrent programming is  usually provided by a real-time operating system (RTOS). Usually\, an  RTOS is a generic framework which can be used across a large number  of processors and applications. An RTOS provides coarse grained  timing support\, and is loosely coupled to the running tasks. As a  result\, an RTOS is seldom optimized for any particular application. \nDespite of all the recent enhancements to compiler technology\,  current compilers have a limited understanding of tasks. Generally\,  the compiler is tightly integrated with the platform. Traditional  compilers are efficient in using platform specific resources\, and in  generating an optimized instruction sequence. Current compiler  technology is capable of extracting instruction-level parallelism  (ILP)\, to varying degrees. Traditionally\, ILP comes from optimizing  loops\, and most likely analyzes code at the basic block level. Today\,  there is no compiler that can detect parallelism at the task level.  Parallelism detection is usually restricted to basic block  structures\, or higher level constructs such as loops. Moreover\,  compilers also lack support for timing constraints of real-time  applications. \nIn this thesis\, we propose an alternative to an RTOS based on the  idea of serializing compilers. A serializing compiler is an automated  software synthesis methodology that can transform a multitasking  application into an equivalent and optimized monolithic sequential  code\, to be compiled with the embedded processor’s native optimizing  compiler. The serializing compiler can analyze the tasks at compile  time and generate a fine-tuned\, application specific infrastructure  to support multitasking\, resulting in a more efficient executable  than one that is intended to run on top of a generic RTOS. By having  control over the application execution and context switches\, the  serializing compiler enables the fine grain control of task timing  while enhancing overall performance. Our serializing compiler  technology strengthens existing compilers\, making them timing and  task-aware. \nThe Phantom Compiler\, our implementation of a serializing compiler\,  provides a fully automated mechanism to synthesize a single threaded\,  ANSI C/C++ program from a multithreaded C/C++ (extended with POSIX)  program. The Phantom generated code is highly tuned for the input  application. With a serializing compiler such as the Phantom  Compiler\, it is possible to generate a multitasking infrastructure  that is small in size\, very efficient when context-switching\, and  customized for each specific application. URL:https://www.cecs.uci.edu/event/software-for-embedded-systems-serializing-compilers-and-its-applications/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070411T150000 DTEND;TZID=America/Los_Angeles:20070411T160000 DTSTAMP:20231011T184638Z CREATED:20231011T184638Z LAST-MODIFIED:20231011T184638Z UID:14346-1176303600-1176307200@www.cecs.uci.edu SUMMARY:New Strategies for System-Level Design DESCRIPTION:New Strategies for System-Level Design: Where to Go?\nKeynote Talk \n\n\n\n\nSpeaker\n\n\nProfessor Gajski \nElectrical Engineering and Computer Science\nUniversity of California at Irvine\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nThe 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems\, Kraków\, Poland\n\n\n\n \n\n\n \n\n\n\nDate\n\n\nApril 11\, 2007\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nWith complexities of Systems-on-Chip rising almost daily\, the design community has been searching for new vision that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution\, such as increasing levels of abstraction\, introducing variety of IPs or offering new design languages will not solve the problem but only prolong the present status of inefficiency and confusion. What is needed is a drastic change in design automation for complex systems that consist of software and hardware. In order to design such systems efficiently\, we need a new approach with a new design flow\, with new models with well defined semantics and a new formalism that will support system synthesis and verification of software and hardware. \nIn order to find the solution\, we will look first at the system gap between SW and HW designs and derive requirements for the design flow that includes software as well as hardware. In order to enable new EDA tools for model generation\, simulation\, synthesis and verification\, the design flow has to be well defined with unique abstraction levels\, model semantics and model transformations corresponding to design decisions made by the designers. We will introduce the concept of model algebra that supports this approach and can serve as an enabler for the extreme makeover of EDA. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of complex systems to the basic principles of design science only.\n\n\n\n\n\n\n\n\n\n\nSlides\n\n\nDownload slides\n\n\n\n \n\n\n \n\n\n\nBiography\n\n\n  \n\n \n\nDaniel Gajski\, a leader in the areas of embedded systems\, design methodologies and languages\, headed the research teams that created new design concepts\, methodologies\, tools and languages. He was instrumental in developing formalisms such as Y-chart\, and numerous algorithms for high-level synthesis\, the definition of the control-data-flow-graph (CDFG) and finite-state-machine with data (FSMD)\, system level languages such as SpecCharts and SpecC\, and design tools such as SpecSyn and Embedded-System Environment. Many of these concepts have been adapted by academia and industry in the last 25 years. \nGajski directs the UCI Center for Embedded Computer Systems\, with a research mission to incorporate embedded systems into automotive\, communications\, and medical applications. He has authored over 300 papers and numerous textbooks\, including Principles of Digital Design (Englewood Cliffs\, NJ: Prentice Hall\, 1997) that has been translated into several languages. \nHe holds Dipl. Ing. and M.S. degrees in electrical engineering from the University of Zagreb\, Croatia\, and a doctoral degree in computer and information sciences from the University of Pennsylvania\, Philadelphia. After 10 years as Professor at University of Illinois he has joined UCI\, where he presently holds The Henry Samueli Endowed Chair in Computer System Design. URL:https://www.cecs.uci.edu/event/new-strategies-for-system-level-design/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070305T150000 DTEND;TZID=America/Los_Angeles:20070305T160000 DTSTAMP:20231011T184246Z CREATED:20231011T184246Z LAST-MODIFIED:20231011T184246Z UID:14335-1173106800-1173110400@www.cecs.uci.edu SUMMARY:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems DESCRIPTION:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems\nby Radu Cornea \nRecent advances in processor\, wireless and graphics technology have fueled a convergence of traditional PDA and cellphone functionality into complex\, media-centric mobile devices. A popular class of applications emerging on these platforms is represented by multimedia\, in particular content streaming (video\, audio). However\, all this added functionality has not come without an expense in one of the most important area for a mobile device: battery life. Multimedia streaming in particular\, with its stringent compu tation\, communication and quality of service requirements further aggravates battery life on these already constrained devices. \nOn the other hand\, multimedia applications have very regular execution patterns\, the only changes being introduced by variations in the data stream itself. This thesis presents a new way to optimize power consumption for multimedia applications\, based on content analysis and annotations. Specifically\, we pre-process the multimedia streams and utilize annotations to capture and carry content-related information to the client device at the receiving end. Annotations allow us to perform more accurate and aggressive optimizations\, with knowledge of the actual content and without relying to less accurate prediction models. \nWe investigate the use of annotation for content-aware optimizations at all level of abstraction (hardware/OS\, network\, application) for the most important system components in a mobile device: CPU/memory\, network interface\, display. Our experimental results show that important energy savings can be achieved for all these components through annotations. Finally\, we integrate the techniques at all levels of abstraction for an increased user experience and battery functionality. We also show how cross-layer trade-offs between power and quality can lead to even higher energy savings with minimal quality degradation. URL:https://www.cecs.uci.edu/event/content-annotation-for-power-and-quality-trade-offs-in-mobile-multimedia-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070205T150000 DTEND;TZID=America/Los_Angeles:20070205T160000 DTSTAMP:20231011T184246Z CREATED:20231011T184246Z LAST-MODIFIED:20231011T184246Z UID:14336-1170687600-1170691200@www.cecs.uci.edu SUMMARY:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications DESCRIPTION:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications\nby Ilya Michailovich Issenin \nWith increasing processing power demands of embedded applications and technology advances\, Multiprocessor Systems-on-Chip (MPSoCs) become prevalent in embedded systems. The memory subsystem is a large and critical contributor to both energy and performance of such systems\, requiring system designers to perform exploration of low power memory organizations. In this dissertation we present an automated approach for data memory subsystem customization for streaming applications. Our approach allows modification of the program to use custom scratch pad memory configurations comprising a hierarchical set of buffers for local storage of frequently reused data. Our data reuse analysis technique provides the system designer with a wide range of customized memory hierarchy organizations with different size and energy profiles and enables the system designer to explore feasible memory subsystem solutions that satisfy power and area constraints while still meeting task deadlines\, both for uniprocessor and multiprocessor systems. \nIn modern multiprocessor embedded systems the communication subsystem also plays an important role in determining overall system power consumption and performance. We propose novel approaches that enables energy-aware co-synthesis of both memory and communication architectures for streaming applications targeting hierarchical bus-based and Network-on-Chip communication architectures. Our techniques achieve significant reduction in memory and communication subsystems energy consumption for data dominant applications\, and allow system designers to explore custom scratch pad memory configuration for a range of power and area constraints. \nThesis\nSlides URL:https://www.cecs.uci.edu/event/multiprocessor-system-on-chip-data-memory-customization-for-embedded-array-intensive-applications/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20060302T150000 DTEND;TZID=America/Los_Angeles:20060302T160000 DTSTAMP:20231011T184246Z CREATED:20231011T184246Z LAST-MODIFIED:20231011T184246Z UID:14337-1141311600-1141315200@www.cecs.uci.edu SUMMARY:Acceleration beyond Memory Barriers in IS-extensible Processors DESCRIPTION:Acceleration beyond Memory Barriers in IS-extensible Processors\nby Partha Biswas \nExtensible processors refer to a class of processors that can be customized for a given application with new designer-defined functional units. One popular feature to extend is the Instruction Set (IS) of the processor—we call such a processor an IS-extensible processor. In an IS-extensible processor\, applications can be accelerated by extending the processor architecture with Application-specific Functional Units (AFUs)\, which execute Instruction Set Extensions (ISEs) in the critical segments of the applications. Automatic identification of such ISEs is the key step in automating the process of processor customization. \nA high-quality ISE identification approach needs to obtain results close to those achieved by experienced designers\, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. This thesis develops an ISE identification algorithm (ISEGEN)\, which identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Traditionally\, synchronization issues have discouraged the inclusion of memory operations in ISEs during the ISE identification step\, causing a “memory barrier”. We show in this thesis that it is possible to go beyond these memory barriers and accelerate the application even more than the traditional ISE identification approaches by eliminating costly memory operations. We present the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively. Finally\, we develop an interface-aware processor customization methodology and use the methodology to realize an IS-extensible-processor-based system on a real platform. \nExperimental results on a number of MediaBench\, EEMBC and cryptographic applications demonstrate that our ISEGEN approach matches the quality of the optimal solution obtained by exhaustive search. We show that our ISEGEN technique is on average 20X faster than a genetic formulation that generates equivalent solutions. We also demonstrate the effectiveness of our approach by incorporating the generated ISEs in the cycle-accurate SimpleScalar simulator. The average speedup on the selected benchmarks increases from 1.4X to 2.8X when the ISE identification process goes beyond memory barriers. Furthermore\, we show a concomitant reduction in energy consumption as a result of reduced cache pollution. In addition to analytical and simulation-based evaluation of the identified ISEs\, we implement our approach in a realistic hardware-software system that allows us to comprehensively study the effect of ISEs on performance\, energy\, power\, and code size using our interface-aware processor customization methodology. Our experiments on a Xilinx Virtex II board—employing the Microblaze soft-core as an extensible processor—show a simultaneous increase in performance\, and reduction in code size\, energy and power consumption with the incorporation of the AFU in the Microblaze soft-core processor. URL:https://www.cecs.uci.edu/event/acceleration-beyond-memory-barriers-in-is-extensible-processors/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20060201T150000 DTEND;TZID=America/Los_Angeles:20060201T160000 DTSTAMP:20231011T184446Z CREATED:20231011T184446Z LAST-MODIFIED:20231011T184446Z UID:14338-1138806000-1138809600@www.cecs.uci.edu SUMMARY:Compiler-in-the-Loop Exploration of Programmable Embedded Systems DESCRIPTION:Compiler-in-the-Loop Exploration of Programmable Embedded Systems\nby Aviral Shrivastava \nEmbedded Systems are characterized by strict\, multi-dimensional design constraints such as power\, performance\, and time-to-market. Increasingly\, embedded processors are being employed for the flexibility of programmable solutions for embedded systems. However\, in order to satisfy all the design constraints simultaneously\, such embedded processors use many idiosyncratic architectural features (e.g.\, partial register renaming and partial bypassing)\, which in turn complicates the task of efficient software generation for the embedded processors. \nThe challenge in developing compilers for embedded processors is not only in developing compiler technology to exploit the idiosyncratic design feature\, but also to perofrm the required analysis in the limited resources present in embedded systems. When the compiler is able to exploit the idiosyncratic design feature\, it often has significant impact on the overall system characteristics. In such cases\, the compiler effects cannot be ignored while searching for the optimal processor design. Traditionally exploration to find an optimal processor is performed by simulating the same application binary over different processor variations. The variation that faresbest on the cost metric is chosen. Compiler effects in such an exploration scheme are typically accounted for\, using ad-hoc methods\, like hand-tuning the application binary\, or scaling the simluation results. Such ad-hoc methods miss many interesting design options\, and may even result in incorrect decisions being made during architectural exploration. \nMy thesis proposes a Compiler-in-the-Loop (CIL) Design Space Exploration (DSE) methodology to systematically include compiler effects in the search for an optimal embedded processor. In this talk I will demonstrate the need and usefulness of CIL DSE at several levels of design abstractions: the micro-architectural level\, the architectural level\, memory level\, and at the processor-memory-interface level. The CIL DSE approach results in a more meaningful exploration of the design space\, and allows embedded system designers to efficiently evaluate architectural options with respect to system constraints quickly\, reliably and early in the design process. URL:https://www.cecs.uci.edu/event/compiler-in-the-loop-exploration-of-programmable-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20051202T150000 DTEND;TZID=America/Los_Angeles:20051202T160000 DTSTAMP:20231011T184446Z CREATED:20231011T184446Z LAST-MODIFIED:20231011T184446Z UID:14340-1133535600-1133539200@www.cecs.uci.edu SUMMARY:Cache Power-Performance Optimization DESCRIPTION:Cache Power-Performance Optimization\nby Dan Nicolaescu \nThe speed gap between the memory and processor continues to increase. As a consequence the cache system becomes more and more important for bridging this speed gap in order to obtain good performance. As the cache size and associativity increase\, its energy consumption becomes a higher part of the total processor energy budget. The high energy consumption is a major problem for current processors\, and given the predictions for the semiconductor industry\, it will further increase in the future. The traditional way of reducing energy consumption through decreasing the feature size is running out of steam. Therefore solutions need to be found at other levels in the design hierarchy. This dissertation studies the performance and energy consumption of the cache system and proposes and proves effective low complexity\, yet highly effective solutions for reducing the cache energy consumption and increasing the processor performance at the architectural level. \nThe cache energy consumption can be reduced by reducing the number of cache accesses. This can be achieved by using a new architectural component called Cached Load/Store Queue which also allows for a performance improvement by reducing average cache access latency. The energy consumption of highly associative CAM based caches can be improved by using a predictor and changing the way the access is performed. The Way Cache is a novel component that can be used to improve the dynamic and static energy consumption of associative caches by reducing the number of tag and data ways accessed for each cache access. URL:https://www.cecs.uci.edu/event/cache-power-performance-optimization/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20051202T150000 DTEND;TZID=America/Los_Angeles:20051202T160000 DTSTAMP:20231011T184446Z CREATED:20231011T184446Z LAST-MODIFIED:20231011T184446Z UID:14339-1133535600-1133539200@www.cecs.uci.edu SUMMARY:Functional Verification of System Level Model Refinements DESCRIPTION:Functional Verification of System Level Model Refinements\nby Samar Abdi \nWith continuous improvement in process technology\, designers have more resources than ever available for implementing their systems. As applications become larger\, the modeling abstraction has to rise to keep the complexity manageable. This has given rise to modeling at abstractions above the register transfer and cycle accurate levels. Verification becomes an even greater challenge as designers try to develop more models to evaluate their implementation choices. In this dissertation we present our verification strategy to alleviate the problems resulting from the move to system level. We argue our case for a system level modeling and verification methodology where detailed models are refined from abstract models. The models are represented formally using Model Algebra and the refinements are proved to be functionality preserving\, using the rules of Model Algebra. We define the objects and composition rules of Model Algebra and show how system level models are represented as expressions in this formalism. The formal execution semantics of such models are discussed and a notion for functional equivalence of models is also presented. We then define transformation rules that syntactically modify a model algebraic expression\, while keeping its functionality intact. Then we present key refinements that are commonly encountered in system level design and prove the correctness of those refinements using the transformation rules of Model Algebra. As a proof of concept\, we implemented a tool that automatically checks if the refinements were performed correctly on SpecC models. As a result\, the designer needs to perform the costly and time consuming property verification on the first model only. All step wise refinements from the original model are proven to produce functionally equivalent models. URL:https://www.cecs.uci.edu/event/functional-verification-of-system-level-model-refinements/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20041025T150000 DTEND;TZID=America/Los_Angeles:20041025T160000 DTSTAMP:20231011T184638Z CREATED:20231011T184638Z LAST-MODIFIED:20231011T184638Z UID:14347-1098716400-1098720000@www.cecs.uci.edu SUMMARY:Extreme Makeover of Design Automation DESCRIPTION:Extreme Makeover of Design Automation \n\n\n\n\nSpeaker\n\n\nProfessor Gajski \nElectrical Engineering and Computer Science\nUniversity of California at Irvine\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nUniversity Club\, UC Irvine\n\n\n\n \n\n\n \n\n\n\nDate & Time\n\n\nOctober 25\, 2004\nSocial Hour at 6:00pm\, Presentation begins at 7:00pm\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nWith complexities of Systems-on-Chip rising almost daily\, the design community has been searching for new vision that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution\, such as increasing levels of abstraction\, introducing variety of IPs or offering new design languages will not solve the problem but only prolong the present status of inefficiency and confusion. What is needed is a drastic change in design automation for complex systems that consist of software and hardware. In order to design such systems efficiently\, we need a new approach with a new design flow\, with new models with well defined semantics and a new formalism that will support system synthesis and verification of software and hardware. \nIn order to find the solution\, we will look first at the system gap between SW and HW designs and derive requirements for the design flow that includes software as well as hardware. In order to enable new EDA tools for model generation\, simulation\, synthesis and verification\, the design flow has to be well defined with unique abstraction levels\, model semantics and model transformations corresponding to design decisions made by the designers. We will introduce the concept of model algebra that supports this approach and can serve as an enabler for the extreme makeover of EDA. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of complex systems to the basic principles of design science only.\n\n\n\n \n\n\n \n\n\n\nBiography\n\n\n  \n\n \n\nProfessor Gajski directs the UCI Center for Embedded Computer Systems\, with a research mission to incorporate embedded systems into automotive\, communications\, and medical applications. He has authored over 300 papers and seven textbooks\, including Principles of Digital Design (Englewood Cliffs\, NJ: Prentice Hall\, 1997) that has been translated into several languages. \nHe holds Dipl. Ing. and M.S. degrees in electrical engineering from the University of Zagreb\, Croatia\, and a doctoral degree in computer and information sciences from the University of Pennsylvania\, Philadelphia. After 10 years as Professor at University of Illinois he has joined UCI\, where he presently holds The Henry Samueli Endowed Chair in Computer System Design. URL:https://www.cecs.uci.edu/event/extreme-makeover-of-design-automation/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20040416T150000 DTEND;TZID=America/Los_Angeles:20040416T160000 DTSTAMP:20231011T184447Z CREATED:20231011T184447Z LAST-MODIFIED:20231011T184447Z UID:14342-1082127600-1082131200@www.cecs.uci.edu SUMMARY:Communication Synthesis for SoC DESCRIPTION:Communication Synthesis for System on Chip\nby Dongwan Shin \nWith the ever increasing complexity of system level designs and the pressure of the time-to-market in the design of System-on-Chip (SoC)\, communication between components is becoming more and more important. Communication design for SoCs poses the unique challenges in order to cover a wide range of architectures while offering new opportunities for optimizations based on the application specific nature of system designs. In this thesis\, we propose a communication design methodology that enables rapid design space exploration in order to achieve the required productivity gains. We define communication abstraction layers\, corresponding design models and transformations which refine abstract message passing channels down to a cycle-accurate implementation. We also implemented automatic model generation tools which apply transformations to a model in order to represent and implement design decisions taken from the users or from automatic synthesis algorithms. The experimental results show the benefits of our methodology and demonstrate the effectiveness of our automatic model generation for communication synthesis. URL:https://www.cecs.uci.edu/event/communication-synthesis-for-soc/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20040416T150000 DTEND;TZID=America/Los_Angeles:20040416T160000 DTSTAMP:20231011T184446Z CREATED:20231011T184446Z LAST-MODIFIED:20231011T184446Z UID:14341-1082127600-1082131200@www.cecs.uci.edu SUMMARY:Modeling Flow for Automated System Design and Exploration DESCRIPTION:Modeling Flow for Automated System Design and Exploration\nby Andreas Gerstlauer \nRaising the level of abstraction is widely seen as the solution for closing the productivity gap in the design of embedded computer systems and systems-on-chip (SoCs). However\, system design thus far suffers from a lack of rigorous\, structured\, and comprehensive design processes from abstract specification down to cycle-accurate implementation. \nIn order to provide an automated design process\, a well-defined design flow with clear and unambiguous abstraction levels\, models\, and transformations is required. The key to the success of this approach are properly defined design models. Arbitrary models without clear semantics do not enable synthesis and verification. In addition\, synthesis requires clear definitions of the target architecture and the set of synthesis steps to transform the input model into the target model. In this dissertation\, we define such input and target models\, a set of design steps\, design decisions\, model transformation\, and intermediate models that are necessary for an automated system design flow. \nThe design flow has been implemented in the form of an interactive system-on-chip design environment (SCE). Automating tedious and error-prone tasks while reaping human expertise and insight results in a flow with the necessary transparency\, controllability\, observability and productivity. As part of this work\, architecture\, organization\, tool flow\, design model management\, interfaces\, and databases of the design framework have been established. Models in the flow have been defined such that they can be automatically generated and model refinement tools have been integrated into the design environment. Finally\, a graphical user interface (GUI) has been developed that aids and steers the designer in the decision making process\, provides visualization of design models\, and supports interactive\, graphical decision entry for each design step. \nExperiments using the design environment prove the feasibility and effectiveness of a seamless\, comprehensive\, and automated design flow supporting rapid\, early design space exploration. Results obtained by applying the design flow to several industrial-strength examples show the tradeoffs and benefits of intermediate models at each step and demonstrate that required productivity gains can be achieved while supporting a wide range of realistic target implementations. URL:https://www.cecs.uci.edu/event/modeling-flow-for-automated-system-design-and-exploration/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20040402T150000 DTEND;TZID=America/Los_Angeles:20040402T160000 DTSTAMP:20231011T184637Z CREATED:20231011T184637Z LAST-MODIFIED:20231011T184637Z UID:14343-1080918000-1080921600@www.cecs.uci.edu SUMMARY:System-Level Automatic Model Refinement DESCRIPTION:System-Level Automatic Model Refinement\nby Junyu Peng \nIn a system-level design methodology\, the system under design is represented by models at different abstraction levels. The design process is essentially a series of steps that gradually transform the most abstract specification model into a detailed implementation model. In practice\, all these models are written manually by designers. As the result\, the designers spend long time on this tedious and error-prone model-writing task. In addition\, it is not possible to verify the equivalence between the models written manually. In this dissertation we present our work on automatic model generation\, where models are generated automatically by tools rather than manually by designers. This kind of automation not only relieves designers from the mundane and time-consuming coding task but also makes it possible to formally verify the functional equivalence between models. \nThis dissertation in particular focuses on the architecture refinement\, which is aimed to automatically generate an architecture model from the input specification model after architecture exploration when architecture allocation and partitioning decisions are made. We approach the problem by first formally defining the semantics and styles of the input specification model and the output architecture model. Based on the differences between the input and output models\, we are able to define a refinement flow which consist of a series of formally-defined transformations. \nDistinguishing itself from other similar approaches\, our approach addresses the quality issue of the automatically generated models. We defined a set of quality metrics that are relevant to architecture refinement. Then we devised several optimization algorithms which can be embedded into the transformations to improve the quality of the output model. \nIn order to prove the feasibility of our approach\, we implemented an automatic model refinement engine which is targeted at the SpecC language. We validated the effectiveness of our approach by applying the refinement engine to a couple of large\, real-life applications. Experimental results demonstrate that 1000x productivity gain is achievable with automatic model generation. URL:https://www.cecs.uci.edu/event/system-level-automatic-model-refinement/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20040319T150000 DTEND;TZID=America/Los_Angeles:20040319T160000 DTSTAMP:20231011T184637Z CREATED:20231011T184637Z LAST-MODIFIED:20231011T184637Z UID:14344-1079708400-1079712000@www.cecs.uci.edu SUMMARY:Specification-driven Validation of Programmable Embedded Systems DESCRIPTION:Specification-driven Validation of Programmable Embedded Systems\nby Prabhat Mishra\nValidation of programmable embedded systems\, consisting of processor cores\, coprocessors\, and memory subsystems\, is one of the major bottlenecks in current System-on-Chip (SOC) design methodology. One of the most important problems in validation of such systems is the lack of a golden reference model. As a result\, many existing validation techniques employ a bottom-up approach to design verification\, where the functionality of an existing architecture is\, in essence\, reverse-engineered from its implementation. \nThis thesis presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification. We have developed validation techniques to ensure that the static and dynamic behaviors of the specified architecture are well formed. The validated specification is used as a golden reference model. \nA major challenge in top-down validation methodology is the ability to generate executable models from the specification for a wide variety of programmable architectures. We have developed a functional abstraction technique that enables specification-driven model generation for simulation\, hardware generation\, and property checking. The generated simulator and hardware models are used for design space exploration of programmable architectures. \nWe have explored two top-down validation scenarios: design validation and test generation. First\, the generated hardware is used as a reference model to verify the hand-written implementation using a combination of symbolic simulation and equivalence checking. Second\, we have proposed a functional coverage based test generation technique for validation of pipelined processor architectures. The experiments demonstrate the utility of the specification-driven validation methodology for programmable embedded systems. URL:https://www.cecs.uci.edu/event/specification-driven-validation-of-programmable-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20040127T150000 DTEND;TZID=America/Los_Angeles:20040127T160000 DTSTAMP:20231011T184837Z CREATED:20231011T184837Z LAST-MODIFIED:20231011T184837Z UID:14348-1075215600-1075219200@www.cecs.uci.edu SUMMARY:System-Level Design Methodology DESCRIPTION:Presented by Professor Daniel Gajski\, University of California\, Irvine\nASP-DAC 2004\nPacifico Yokohama\, Yokohama\, Japan\nJanuary 27\, 2004\ndownload pdf URL:https://www.cecs.uci.edu/event/system-level-design-methodology/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20031219T150000 DTEND;TZID=America/Los_Angeles:20031219T160000 DTSTAMP:20231011T184638Z CREATED:20231011T184638Z LAST-MODIFIED:20231011T184638Z UID:14345-1071846000-1071849600@www.cecs.uci.edu SUMMARY:Estimation and Exploration Automation of System Level Design DESCRIPTION:Estimation and Exploration Automation of System Level Design\nby Lukai Cai\nRecently\, as system design is becoming more and more challenging due to decreasing timeto-\nmarket and increasing system complexities\, trends are emerging to move the design process to\nhigher levels of abstraction. System-level design demands corresponding approaches that efficiently explore the complete system design space and rapidly evaluate a large number of design alternatives in a short amount of time. \nThis work proposes fast estimation and efficient exploration approaches for system synthesis\ndesign flow. It starts with the system behavior which represents the design functionality\, generates\nthe system architecture from the system behavior\, and finally maps the system behavior to the\nsystem architecture. \nIn this work\, we target at complex system design: the system behavior is modeled concurrently\nand hierarchically\, the system architecture is assembled by processing elements with\ndifferent attributes and incompatible communication protocols. Because our approaches are all\nimplemented at high abstraction levels and have relatively low time complexities\, we meet the\nrequirement for fast estimation and exploration of the system level design. URL:https://www.cecs.uci.edu/event/estimation-and-exploration-automation-of-system-level-design/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20031120T150000 DTEND;TZID=America/Los_Angeles:20031120T160000 DTSTAMP:20231011T184837Z CREATED:20231011T184837Z LAST-MODIFIED:20231011T184837Z UID:14349-1069340400-1069344000@www.cecs.uci.edu SUMMARY:System Debugging and Verification: A New Challenge DESCRIPTION:Presented by Professor Daniel Gajski and Samar Abdi\, University of California\, Irvine\nVerify 2003\nNovember 20\, 2003\ndownload pdf URL:https://www.cecs.uci.edu/event/system-debugging-and-verification-a-new-challenge/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20031107T150000 DTEND;TZID=America/Los_Angeles:20031107T160000 DTSTAMP:20231011T184837Z CREATED:20231011T184837Z LAST-MODIFIED:20231011T184837Z UID:14350-1068217200-1068220800@www.cecs.uci.edu SUMMARY:Covalidation of Hardware/Software Systems DESCRIPTION:Presented by Professor Ian G. Harris\, University of California\, Irvine\nIntel Test Research Symposium\nSanta Clara\, CA\nNovember 7\, 2003\ndownload pdf URL:https://www.cecs.uci.edu/event/covalidation-of-hardware-software-systems/ CATEGORIES:PhD Defenses END:VEVENT END:VCALENDAR