BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CECS - ECPv6.18.4//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://www.cecs.uci.edu X-WR-CALDESC:Events for CECS REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20050403T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20051030T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20060402T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20061029T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20070311T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20071104T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20080309T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20081102T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20090308T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20091101T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20100314T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20101107T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20110313T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20111106T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20120311T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20121104T090000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:20130310T100000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:20131103T090000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20120223T150000 DTEND;TZID=America/Los_Angeles:20120223T160000 DTSTAMP:20231011T183524Z CREATED:20231011T183524Z LAST-MODIFIED:20231011T183524Z UID:14309-1330009200-1330012800@www.cecs.uci.edu SUMMARY:Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: February 23\, 2012\, 3:30pm – 5:30pm \nCommittee:\nProfessor Ahmed Eltawil (Chair)\nProfessor Ender Ayanoglu\nProfessor Fadi Kurdahi \nTitle: Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures \nAbstract:\nMIMO communication has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. However\, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity. In this thesis\, we present efficient design for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels. We consider that the MIMO detector and the channel decoder are two major blocks and attempt to optimize them in a joint sense. First of all\, we will focus on the design of MIMO detector and propose two approaches. The first design presents a novel algorithm and architecture for K-Best detection. The algorithm examines a much smaller subset of points in the tree structure while still achieving near-optimal performance. The VLSI architecture of the detector is based on a pipelined sorter-free scheme such that high throughput is achieved. The second design demonstrates an algorithm and VLSI architecture of combining the features of classical depth-first and breadth-first methods. Techniques to reduce complexity while providing both hard and soft output detection are also presented. Finally we will present an approach to perform joint detection and decoding for MIMO systems using convolutional codes. The BER performance of this approach is significantly better than that of systems which utilize separate detection and decoding blocks. The proof of concept VLSI architecture is provided and a novel way to reduce memory usage is demonstrated. URL:https://www.cecs.uci.edu/event/tree-search-based-mimo-detectors-algorithms-and-vlsi-architectures/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20111027T150000 DTEND;TZID=America/Los_Angeles:20111027T160000 DTSTAMP:20231011T183524Z CREATED:20231011T183524Z LAST-MODIFIED:20231011T183524Z UID:14310-1319727600-1319731200@www.cecs.uci.edu SUMMARY:Energy Harvesting and Power Optimization for Remote Sensing Systems DESCRIPTION:Energy Harvesting and Power Optimization for Remote Sensing Systems\nby Sehwan Kim \nLocation: Engineering Gateway – CEE Conference Room \nDate and Time: October 27\, 2011 2:00pm \nCommittee:\nProf. Pai Chou (Chair)\nProf. Masanobu Shinozuka\nProf. Maria Feng \nAbstract:\nThe mobile and wireless micro-sensors suffer from short operational lifetimes because they lack space to store the energy that wireless transmission\, signal conditioning\, and monitoring require to operate across time. Energy harvesting capabilities enable totally untethered operation of mobile and wireless micro-sensors for extended periods of time without requiring battery replacement. This paper is to introduce and discuss the design challenges associated with harvesting circuits when harnessing\, conditioning\, and transferring power from ambient energy sources. In addition\, supercapacitors have emerged as an increasingly viable alternative to batteries for micro-solar energy harvesters. To address the problems of high leakage and high unusable residual charge\, previous work proposed multiple supercapacitors with a reconfigurable topology. We propose to optimize such systems by two ways: selection of optimal sizes of the supercapacitors at design time\, and choosing the optimal series or parallel topology at run time. This combination enables the supercapacitor subsystem to maximize the energy storage while minimizing leakage and residual energy\, thereby enabling the maximum utility of the energy storage elements over different operating scenarios. URL:https://www.cecs.uci.edu/event/energy-harvesting-and-power-optimization-for-remote-sensing-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20110928T150000 DTEND;TZID=America/Los_Angeles:20110928T160000 DTSTAMP:20231011T183525Z CREATED:20231011T183525Z LAST-MODIFIED:20231011T183525Z UID:14311-1317222000-1317225600@www.cecs.uci.edu SUMMARY:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures DESCRIPTION:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures\nby Amir Hossein Gholamipour \nCommittee:\nProf. Fadi Kurdahi (chair)\nProf. Ahmed Eltawil\nProf. Michael Dillencourt \nAn increasing number of digital systems\, from wireless devices to multi-media terminals\, are characterized by their multi-mode operation. This refers to the ability of a system to modify its characteristics or behavior based on user inputs or changes in the operational environment. FIR filters are frequently used in the operation of multi-mode systems due to their inherent stability and linear phase. In majority of such systems implementing a multi-mode FIR filter is the challenge in realizing the multi-mode behavior. FIR filters used for each mode of operation have different sets of parameters (coefficient sets). To implement multi-mode FIR filters\, General Purpose processors are incompetent in delivering the performance while Application Specific Integrated Circuits (ASICs) do not support the required flexibility. On Partially reconfigurable FPGA platforms we can optimize a filter structure based on the fixed parameters of filter and change the mode of operation by reconfiguring the fabric. However the reconfiguration overhead in this approach is not negligible. \nIn this work we introduce an approach which produces a spectrum of filter designs which trade-off area for reconfiguration overhead. In this thesis I prove that the problem of filter optimization can be solved in polynomial time. Furthermore as filter designs in the sequence of reconfiguration have similarities in their parameter sets\, we propose to jointly optimize their designs to further reduce the reconfiguration overhead. We consider the physical limitations of implementing multi-mode filters on FPGAs and propose a placement-aware approach to account for those limitations. Our placement-aware approach is an additional step called /Mapping/ that is introduced before floorplanning the design. In my work\, I show that mapping is an NP-hard problem and I propose ILP formulation and heuristics to solve it. As the result of my research\, I have developed a tool which gets the description of a sequence of filters as an input and generates the RTL design of the filters in VHDL code. It then gives hints on how to map the modules of the design to physical regions on the FPGA chip. This design approach has been tested on a rich set of applications including “preamble detection” unit of OFDMA receivers\, template matching and matched-filter based spectrum sensors. The results show the importance of this approach and the efficiency of the solutions proposed. URL:https://www.cecs.uci.edu/event/comprehensive-multi-level-joint-optimization-for-multi-mode-fir-like-structures/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20110903T150000 DTEND;TZID=America/Los_Angeles:20110903T160000 DTSTAMP:20231011T183525Z CREATED:20231011T183525Z LAST-MODIFIED:20231011T183525Z UID:14312-1315062000-1315065600@www.cecs.uci.edu SUMMARY:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story DESCRIPTION:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story\nby Houman Homayoun \nLocation: Bren Hall 4011 \nDate and Time: September 3\, 2011 2:30pm \nCommittee:\nProfessor Fadi Kurdahi (Chair)\nProfessor Alex Veidenbaum\,\nProfessor Jean-Luc Gaudiot\,\nProfessor Alex Nicolau. \nAbstract:\nLeakage currents in on-chip SRAMs: caches\, branch predictor\, register files and TLBs\, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines\, making remaining SRAM components\, in particular large drivers\, the primary source of leakage. We proposes an integrated circuit and architectural approach to reduce this source of leakage in all major SRAM-based units of the processor\, controlling them in a uniform way\, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Various low-power modes are defined\, from basic to ultra-low power\, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to be significant for all SRAM units. Resulting temperature reduction\, including the effect of positive feedback between temperature and leakage power\, is evaluated. A significant temperature reduction is achieved in each unit. URL:https://www.cecs.uci.edu/event/beyond-memory-cells-for-leakage-and-temperature-control-in-sram-based-units-the-peripheral-circuits-story/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20101129T150000 DTEND;TZID=America/Los_Angeles:20101129T160000 DTSTAMP:20231011T183701Z CREATED:20231011T183701Z LAST-MODIFIED:20231011T183701Z UID:14313-1291042800-1291046400@www.cecs.uci.edu SUMMARY:Aggressive Power Management Utilizing Embedded Memory Fault Tolerant Adaptation For Wireless/Multimedia Systems DESCRIPTION:Aggressive Power Management Utilizing Embedded Memory Fault Tolerant Adaptation For Wireless/Multimedia Systems\nby Amin Khajeh Djahromi \nLocation: Engineering Hall 2111 \nDate and Time: November 29\, 2010 4:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Stephen Jenks\nProf. Rainer Doemer \nAbstract:\nDesigners of next generation Systems-on-Chip (SoCs) face daunting challenges in generating high yielding architectures that integrate vast amounts of logic and memories in a minimum die size\, while simultaneously minimizing power consumption. Traditional design approaches attempt to guarantee 100% error-free SoCs. However\, advanced manufacturing technologies will make it economically impractical to insist on a 100% error-free SoC in terms of area and power. Fortunately\, many important application domains (e.g.\, communication and multimedia) are inherently error-aware\, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. In such systems\, the share of the SoC that is dedicated to embedded memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoC for most recent advanced wireless standards. Furthermore\, a large portion of the memory is typically used for buffering data that already has a high level of redundancy. \nFinally\, from a network perspective\, buffering memories are transparent across a hierarchy since they do not change the nature of the data stored\, which allows for simple and efficient cross- layer techniques. In my thesis I investigated the effect of voltage over scaling on the embedded memories functionality. Then I proposed fault tolerant adaptive voltage scaling and adaptive body biasing as a mean of reducing power consumption in embedded memories. These techniques tradeoff reliability versus power savings as a function of the time varying quality of the incoming data\, as long as the signal to noise ratio at the decision device is maintained at a desirable level. Moreover\, I addressed the notion of error-awareness across different abstraction layers physical\, application\, network\, and technology for the next generation SoCs. I showed that utilizing proposed techniques on embedded memories (mainly through aggressive ! voltage scaling) will result in a) appreciable power reduction in wire less systems depending on the application\, b) savings in cost and area by reducing or eliminating the need for circuit redundancy\, and c) achieving a higher “effective yield” by tolerating errors at the system level while keeping other parameters constant. URL:https://www.cecs.uci.edu/event/aggressive-power-management-utilizing-embedded-memory-fault-tolerant-adaptation-for-wireless-multimedia-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20100907T150000 DTEND;TZID=America/Los_Angeles:20100907T160000 DTSTAMP:20231011T183701Z CREATED:20231011T183701Z LAST-MODIFIED:20231011T183701Z UID:14314-1283871600-1283875200@www.cecs.uci.edu SUMMARY:Leveraging Profile-Selected Execution Patterns for Optimized Code Execution in Resource-Constrained Systems DESCRIPTION:Leveraging Profile-Selected Execution Patterns for Optimized Code Execution in Resource-Constrained Systems\nby Carmen Badea \nLocation: Bren Hall 3013 \nDate and Time: September 7\, 2010 11:00am \nCommittee:\nProf. Alex Nicolau (Chair)\nProf. Alex Veidenbaum\nProf. Nikil Dutt \nAbstract:\nEmbedded systems and related devices have become ubiquitous in today’s world and are expected to proliferate even further. The execution performance for such devices is of paramount importance and is often perceived as the limiting factor w.r.t. both the capabilities of the system\, as well as the user perception. Furthermore\, unlike traditional general-purpose computing systems\, these devices exhibit further inherent constraints due to their nature: memory and energy consumption. \nIn order to overcome the intrinsic drawbacks of Java execution for resource-constrained systems\, we propose to use dynamic profile-selected\, optimized execution patterns in order to build a lightweight Java execution environment\, targeting resource-constrained systems\, that achieves competitive Java runtime performance\, while having negligible impact on memory footprint\, as well as reducing the overall energy consumption. \nMore recently\, with the advancements in the web application technology\, the browser has emerged as the favorite platform for deploying many applications\, in particular for embedded devices such as smartphones. As such\, we investigated whether the use of frequent execution patterns selected as directed by dynamic profiling would be beneficial for browser execution performance. With the use of collected dynamic profiling data indicating the most frequent patterns of execution we were able to develop a browser prototype that delivers significant runtime performance speedups. URL:https://www.cecs.uci.edu/event/leveraging-profile-selected-execution-patterns-for-optimized-code-execution-in-resource-constrained-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20100903T150000 DTEND;TZID=America/Los_Angeles:20100903T160000 DTSTAMP:20231011T183701Z CREATED:20231011T183701Z LAST-MODIFIED:20231011T183701Z UID:14315-1283526000-1283529600@www.cecs.uci.edu SUMMARY:Framework for Spiking Neural Network Modeling on High-Performance Architectures DESCRIPTION:Framework for Spiking Neural Network Modeling on High-Performance Architectures\nby Jayram Moorkanikara Nageswaran \nCommittee: \nProf. Nikil Dutt (chair)\nProf. Jeffrey L Krichmar\nProf. Alex Nicolau\nProf. Alex Veidenbaum \nSpiking neural network (SNN) models are emerging as a plausible paradigm for characterizing neural dynamics in the cerebral cortex. Traditionally these SNN models were simulated on large-scale clusters\, super-computers\, or on dedicated VLSI architectures. Alternatively\, Graphics Processing Units (GPUs) can provide a low-cost\, programmable\, and high-performance computing platform for simulation of SNNs. This thesis proposes a systematic framework for modeling and simulation of biologically realistic large-scale spiking neural networks on high-performance graphics processors. \nThe first part of the framework consists of a high-level specification to quickly build arbitrary\, large-scale spiking neural network for different applications. The high-level SNN specification is then converted to a sparse adjacency matrix representation and mapped on the GPUs. Further\, we present a collection of new techniques related to parallelism extraction\, mapping of irregular communication\, and compact adjacency matrix representation for effective simulation of SNNs on GPUs. The last part of the generic framework proposes an evolutionary approach to automate parameter tuning in spiking neural networks. We demonstrate the validity of this framework by applying to three different spike-based computation problems. Significant improvements in modeling\, simulation and parameter tuning time have been achieved by these approaches. URL:https://www.cecs.uci.edu/event/framework-for-spiking-neural-network-modeling-on-high-performance-architectures/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20100519T150000 DTEND;TZID=America/Los_Angeles:20100519T160000 DTSTAMP:20231011T183702Z CREATED:20231011T183702Z LAST-MODIFIED:20231011T183702Z UID:14316-1274281200-1274284800@www.cecs.uci.edu SUMMARY:Code Layout Optimization for Remote Progressive Code Update for Networked Embedded Systems DESCRIPTION:Code Layout Optimization for Remote Progressive Code Update for Networked Embedded Systems\nby Jinsik Kim \nLocation: Engineering Hall 2111 \nDate and Time: November 18\, 2009 2:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Tony Givargis\nProf. Rainer Doemer \nAbstract:\nMany embedded systems need to have their firmware updated several times over the lifetime of the system after deployment. While those based on binary differencing suffer from unpredictable code shift\, overwriting the entire firmware image may be too costly for those connected by slow\, unreliable\, or expensive data links. In other words\, firmware update over a network connection is an essential but expensive feature for many embedded systems due to the relatively high power consumption and limited bandwidth. \nTo solve these problems\, we propose a new technique by exploiting high-level knowledge about the source program structure in laying out the binary image. Specifically\, we show that by laying out code in order of the cyclomatic complexity of the routines\, the code will evolve with minimal Hamming distance between successive revisions as the code evolves. This code layout technique has the benefits of minimizing bandwidth and power requirements for remote firmware update while also minimizing the wearing of the non-volatile program memory.For another target physical memory\, our work proposes a page-level\, link-time technique that minimizes not only the size of patching scripts but also perturbation to the firmware memory\, over the entire sequence of updates in the system’s lifetime. Experimental results show our technique to reduce the energy consumption of firmware update by 30–42% over the state-of-the-art. URL:https://www.cecs.uci.edu/event/code-layout-optimization-for-remote-progressive-code-update-for-networked-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20091118T150000 DTEND;TZID=America/Los_Angeles:20091118T160000 DTSTAMP:20231011T183702Z CREATED:20231011T183702Z LAST-MODIFIED:20231011T183702Z UID:14317-1258556400-1258560000@www.cecs.uci.edu SUMMARY:Low-Complexity and High-Throughput Protocols for Wireless Sensor Networks DESCRIPTION:Low-Complexity and High-Throughput Protocols for Wireless Sensor Networks\nby Chongjing Chen \nLocation: Engineering Hall 2210 \nDate and Time: November 18\, 2009 2:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Stephen Jenks\nProf. Rainer Doemer \nAbstract:\nWireless technologies have enabled mobility and convenience by eliminating cumbersome wires. Wireless sensor nodes must be made small and low power without sacri?cing performance. In addition to task scheduling\, the densely distributed wireless sensor nodes must run communication protocols to achieve better utilization and reliable communication. While many researchers work on wireless sensor networks that are densely distributed\, they assume low duty cycling and trivial data rate. Unfortunately\, this is a great mismatch with many real-world applications that require the high data rate. Furthermore\, most wireless communication protocols are too complicated to be used on compact wireless sensor nodes with limited RAM and ROM. \nTo address these issues\, we propose a lightweight multiple access control protocol to enable relatively high data rate and densely distributed deployment. It can achieve reliable communication on resource-constrained wireless sensor nodes and minimizes the protocol complexity to reduce the memory footprint. The protocol can also work under high utilization of air bandwidth without collision. While civil engineers are concerned about the sampling rate at 100 Hz for structure monitoring\, our system with this protocol can scale up to 50 wireless sensor nodes and stream real-time data in the same frequency channel at 100 Hz sampling rate. We also propose a compact\, multi-channel protocol with high scalability and small memory footprint. This multiple access control protocol enables wireless sensor nodes to transmit sensing data over multiple frequency channels to achieve a higher throughput than a system with only a single frequency channel. We integrate our protocol with a giant tiled display system\, HIPerWall\, to show the real-time sensing data at a high resolution without downsampling. Last\, we perform a thorough evaluation to study the channel characteristics of a wearable wireless sensor node. We vary several di?erent parameters\, the RF transmission power\, distance\, height\, and angle to observe the packet loss rates. These experimental results can be used for constructing a more reliable wireless communication for wireless sensor networks. URL:https://www.cecs.uci.edu/event/low-complexity-and-high-throughput-protocols-for-wireless-sensor-networks/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090901T150000 DTEND;TZID=America/Los_Angeles:20090901T160000 DTSTAMP:20231011T183716Z CREATED:20231011T183716Z LAST-MODIFIED:20231011T183716Z UID:14318-1251817200-1251820800@www.cecs.uci.edu SUMMARY:Algorithmic Code Optimization Using Conditional Expression Evaluation DESCRIPTION:Algorithmic Code Optimization Using Conditional Expression Evaluation\nby Mohammad Ali Ghodrat \nLocation: Bren Hall 3011 \nDate and Time: September 1\, 2009 10:30am \nCommittee:\nProfessor Tony Givargis (Chair)\nProfessor Alex Nicolau\nProfessor Nikil Dutt \nAbstract:\nSoftware is becoming a larger fraction of engineering effort. Aggressive compiler optimization\, in particular those that address loops\, can significantly improve the performance of the software\, thus justifying the additional compilation time requirements. This is in particular true in the embedded system domain where software has become a key element of the design process and performance/energy is of a critical concern. A particular area in software optimization\, where little work has been established\, is control flow performance and energy optimization\, which is the main focus of this thesis. \nArithmetic expressions are the fundamental building blocks of hardware and software systems. In this thesis we first propose a method for solving the arithmetic expression equivalence problem using partial evaluation. In our method\, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Using this technique\, we present three novel control flow optimization techniques to improve performance and energy in software. \nIn the first technique\, we present a short-circuit code transformation method to optimize conditional blocks in high-level programs. Specifically\, the transformation takes advantage of the fact that the Boolean value of the conditional expression\, determining the true/false paths\, can be statically analyzed to determine cases when one or the other of the true/false paths are guaranteed to execute. In such cases\, code is generated to bypass the evaluation of the conditional expression. In instances when the bypass code is faster to evaluate than the conditional expression\, a net performance gain is obtained. \nIn the second technique\, we present a loop transformation method to optimize loops containing nested conditional blocks. Results from conditional expression evaluation combined with loop dependency information are used to partition the iteration space of the nested loop. As a result\, the loop nest is decomposed such as to eliminate the conditional test\, thus substantially reducing the execution time. Our technique completely eliminates the conditional from the loops (unlike previous techniques) thus further facilitating the application of traditional optimizations and improving the overall speedup. \nIn the third technique\, we present a method to lower the software energy consumption using the technique mentioned above for loop transformation. In essence\, each of the smaller loops can be executed at a lower voltage/frequency setting\, yielding overall energy reduction. \nApplying the proposed transformation techniques on kernels taken from different application domains\, we measured a substantial performance and energy improvement. URL:https://www.cecs.uci.edu/event/algorithmic-code-optimization-using-conditional-expression-evaluation/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090709T150000 DTEND;TZID=America/Los_Angeles:20090709T160000 DTSTAMP:20231011T183716Z CREATED:20231011T183716Z LAST-MODIFIED:20231011T183716Z UID:14319-1247151600-1247155200@www.cecs.uci.edu SUMMARY:Transducer Synthesis for Heterogeneous Multi-processor Systems DESCRIPTION:Transducer Synthesis for Heterogeneous Multi-processor Systems\nby Hansu Cho \nLocation: EH 2210 \nDate and Time: July 9\, 2009\, 8:30 AM \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nContemporary system design requires more computational power than ever. To overcome this problem\, MPSoC is widely used\, but design complexity have been increased rapidly. Meanwhile\, short time to market forced system designer to reduce development time. Therefore\, designer raised the level of abstraction into the higher level called transaction level. But\, current high level synthesis tools are dedicated to computational components only. To our best knowledge\, there is no synthesis tool for communication components from the transaction level model down to RTL model. In this dissertation\, we present a component called transducer which can handle heterogeneous MPSoC communication with multiple buses. Also\, we presents a tool for automatic synthesis of transducer. The tool captures the communication parameters in the platform at transaction level and generates transducer in RTL. The design and configuration of the transducer depend on several platform components including heterogeneity of the components\, traffic on the bus\, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the transducer can be automatically derived based on these parameters. \nThe advantage of this approach is that the user may modifies transducer parameters to suit specific optimization goals. In contrast to conventional approaches like IP wrappers\, our approach enables the user to generate an application specific interface between any number of buses for any platform configuration. Therefore\, the system designer is not bound to a set of IPs or protocols for their platform definition. Furthermore\, due to automatic generation\, we provide several orders of magnitude savings in interface development cost. We demonstrate the synthesizability and quality of our automatically generated transducers using Xilinx ISE tools and FPGA board. We use industrial strength design drivers such as an MP3 decoder and JPEG encoder to test our automatically generated transducers for a variety of platforms and compare them to manually designed transducers on different quality metrics. Our experimental results show that performance of automatically generated transducers are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 20X of improvement in development time. URL:https://www.cecs.uci.edu/event/transducer-synthesis-for-heterogeneous-multi-processor-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090618T150000 DTEND;TZID=America/Los_Angeles:20090618T160000 DTSTAMP:20231011T183716Z CREATED:20231011T183716Z LAST-MODIFIED:20231011T183716Z UID:14320-1245337200-1245340800@www.cecs.uci.edu SUMMARY:Automatic Generation and Verification of Transaction Level Models DESCRIPTION:Automatic Generation and Verification of Transaction Level Models\nby Lochi Yu \nLocation: ET 331 \nDate and Time: June 18\, 2009 10:00am \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nThe rising complexity in system designs over the past decades poses great challenges to current designers. One way to cope with this challenge has been to raise the level of abstraction of design\, reducing the number of elements and speeding up design decisions. Transaction Level Models (TLM) have emerged as a new alternative to design Multi-Processor System-on-Chips (MPSoC). TLMs express communication among modules at the transaction level\, without simulating the dozens of individual signals in communication elements such as busses. Nevertheless\, several drawbacks exist: TLMs are fast\, but their accuracy is low\, TLMs are being coded manually\, often by the use of a System Level Design Language (SLDL)\, there is no widely-adopted and tool-supported TLM style\, and there has been little work on verifi cation at the System Level. In this dissertation\, we aimed to contribute in different aspects: We defined a modeling style for SystemC TLMs whose modules have a one-to-one relationship with actual synthesized modules in a FPGA. Then\, we defined a data structure\, complete and flexible enough to describe a complete embedded system\, its hardware platform and application\, and developed generation algorithms that would use it to automatically produce an executable TLM in SystemC. Fourth\, we designed new transformation rules for models in Model Algebra (MA) that allows veri cation on pipelined models in MA. With our approach\, we can have automatic generation and verification of Transaction Level Models\, freeing the designer from error-prone manual coding\, and allows him to focus on higher level design decisions\, speeding up the overall design phase. URL:https://www.cecs.uci.edu/event/automatic-generation-and-verification-of-transaction-level-models/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090603T150000 DTEND;TZID=America/Los_Angeles:20090603T160000 DTSTAMP:20231011T183716Z CREATED:20231011T183716Z LAST-MODIFIED:20231011T183716Z UID:14321-1244041200-1244044800@www.cecs.uci.edu SUMMARY:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors DESCRIPTION:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors\nby Ashok Halambi \nLocation: DBH 4013 \nDate and Time: June 3\, 2009 2:00pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Alex Nicolau\nProfessor Alex Viedenbaum \nAbstract:\nEmbedded systems continue to increase in functionality\, complexity and connectivity. Programmable platforms\, consisting of processors programmable in software\, are a popular solution to satisfy the design constraints (such as cost\, performance\, flexibility\, reliability etc.) of such systems. Key challenges in the design of programmable platforms include compiler-in-loop design space exploration (DSE)\, and automatic generation of software toolkit for hardware/software co-design. \nA language-based model of the processor-memory subsystem has several benefits: it serves as a golden reference model for all principals involved in the design; it can be used to drive DSE and automatic software toolkit generation; it can be used to perform top-down (formal) verification and validation; and\, it can be refined down to implementation (register-transfer level). In this dissertation\, we present EXPRESSION\, an architecture description language (ADL) that is designed for DSE of processor-memory sub-system and automatic generation of software toolkit including compiler and cycle-accurate simulator. EXPRESSION has been used to describe various processors from RISC (DLX\, MIPS R4000\, ARM 9)\, VLIW (TI C6x)\, DSP (ST100)\, etc. Our EXPRESSION based DSE methodology permits exploration of a wide range of processor architectures\, and includes compiler-in-loop for accurate analysis of each design configuration. \nTo aid compiler-in-loop DSE\, we developed EXPRESS\, a retargetable\, instruction level parallelizing compiler that accepts programs in “C” and produces assembly code for the target processor described in EXPRESSION. The EXPRESS compiler is capable of handling irregular architectures\, and can adapt to changes in the processor’s instruction-set or micro-architecture. EXPRESS also includes a framework for dynamic customization of the compiler based on the target application and architecture characteristics. These capabilities of EXPRESS make it ideal for use in the DSE of processor-memory subsystems. \nRetargetable compilers suffer from the drawback of poor output code quality as compared to a compiler that is “hand-crafted” for the target processor. Key differences between the two compilers include the presence of target specific optimizations and custom phase ordering of optimization passes in the target specific compiler. In this dissertation\, we propose a framework\, called TransMutations\, that enables dynamic\, run-time customization of a retargetable compiler. It allows for easy integration of optimizations (called mutations) into the compiler and solves the phase ordering problem by applying optimizations in a context-sensitive manner for each region of the application code. The TransMutations framework has been implemented in the EXPRESS compiler and we present results demonstrating the effectiveness of the technique. This framework improves the quality of code generated by retargetable compilers and enables them to be used in accurate compiler-in-loop DSE of programmable embedded systems. URL:https://www.cecs.uci.edu/event/transmutations-a-framework-for-dynamic-customization-of-retargetable-compilers-for-embedded-processors/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090529T150000 DTEND;TZID=America/Los_Angeles:20090529T160000 DTSTAMP:20231011T183716Z CREATED:20231011T183716Z LAST-MODIFIED:20231011T183716Z UID:14322-1243609200-1243612800@www.cecs.uci.edu SUMMARY:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement DESCRIPTION:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement\nby Aseem Gupta \nLocation: DBH 3011 \nDate and Time: May 29\, 2009 1:30pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Fadi Kurdahi\nProfessor Tony Givargis \nAbstract:\nProcess scaling and shrinking device geometries have resulted in chips with greater performance and complexity levels. However\, these advancements have come at the cost of higher power densities and increased operating temperatures. The inability to control the operating temperatures by existing cooling techniques is the principal reason for discontinuation of an increase in frequencies and introduction of multi-core architectures. Apart from operability\, high temperatures have unfavorable consequences such as: increased leakage power\, reduced interconnect life time\, slowing of interconnects and transistors\, need for expensive package and cooling mechanisms\, and increased manufacturing cost and design effort. Traditionally\, thermal issues have been examined only at the post-synthesis stages of the design flow. This thesis attempts to migrate the “thermal awareness” from the physical level design phase to early stages of the VLSI design flow and utilize it to target various design metrics such as power\, performance\, reliability\, and operability. This thesis advances the procedure of leakage power estimation by coupling it with thermal profile estimation and capturing the positive interdependence between temperature and leakage power. It also advances the traditional role of communication architecture to that of an active thermal manager. The proposed communication architecture based thermal manager delays the execution of chosen components by regulating the flow of data over the on-chip communication fabric. This dissertation demonstrates the need of examining the effects of frequency\, supply voltage\, power dissipation\, and temperature on SRAM reliability in a mutually interrelated manner. Our observation contradicts the conventional belief that increasing supply voltage always reduces the failure rate in SRAMs. Because of thermal effects\, an increase in the supply voltage can also lead to increase in the SRAM failure rate. This thesis also extends the procedure of system level floorplanning to manage the leakage power and reliability of the design. The fundamental contribution of this thesis is that it advances the traditional design flow in the direction of incorporating thermal awareness during various stages of the flow. URL:https://www.cecs.uci.edu/event/temperature-aware-vlsi-design-for-reduced-power-and-reliability-enhancement/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090527T150000 DTEND;TZID=America/Los_Angeles:20090527T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14323-1243436400-1243440000@www.cecs.uci.edu SUMMARY:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems DESCRIPTION:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems\nby Gabor Madl \nLocation: DBH 3011 \nDate and Time: May 27\, 2009 10:00am \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Tony Givargis\nProfessor Ian Harris \nAbstract:\nAs embedded systems become increasingly networked\, and interact with the physical world\, Distributed Real-time Embedded (DRE) systems emerge. DRE systems range from small-scale Multi-processor Systems-on-Chip (MPSoCs) operating in resource constrained environments such as cell phone platforms\, medical devices and sensor networks all the way to large-scale software-intensive systems of systems used in avionics\, ship computing environments\, and in supervisory control and data acquisition systems managing regional power grids. \nThis dissertation focuses on the model-based analysis of event-driven DRE systems. Event-driven DRE systems are based on a reactive communication paradigm\, where the execution of tasks is triggered asynchronously\, invoked by external events\, interrupts\, or by other tasks. Events can also express time\, providing a common semantic domain for the compositional analysis of time- and event-driven DRE systems. \nThe key technical contributions of this dissertation are (1) the specification of a formal semantic domain for DRE systems\, (2) a model checking method for the real-time verification of non-preemptive DRE systems using timed automata\, (3) a performance estimation method for DRE systems by discrete event simulations\, (4) a conservative approximation method for the verification of preemptive event-driven asynchronous DRE systems by timed automata\, (5) a method for the functional verification and performance estimation of MPSoCs built on an industry standard interconnect\, and (6) a cross-abstraction real-time analysis method for MPSoC designs utilizing bus matrix interconnects. \nThe novelty of our approach lies in combining formal methods and symbolic simulations for the system-level evaluation of DRE designs early in the design flow\, and utilizing multiple abstractions to trade off analysis accuracy in scalability. \nWe implemented the proposed analysis methods in the open-source Distributed Real-time Embedded Analysis Method (DREAM) framework for the model-based real-time verification and performance estimation of DRE systems. DREAM focuses on the practical application of formal analysis methods to automate the verification\, development\, configuration\, and integration of event-driven DRE systems. DREAM is available for download at http://dre.sourceforge.net. We applied the proposed design flow to the domain of software-intensive mission-critical avionics DRE applications\, and the domain of multimedia MPSoCs. URL:https://www.cecs.uci.edu/event/model-based-analysis-of-event-driven-distributed-real-time-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20090227T150000 DTEND;TZID=America/Los_Angeles:20090227T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14324-1235746800-1235750400@www.cecs.uci.edu SUMMARY:Automatic Design and Optimization of Application Specific Processors DESCRIPTION:Automatic Design and Optimization of Application Specific Processors\nby Jelena Trajkovic \nThe stringent performance and power requirements of modern applications have fueled the need for application specific computing platforms. Conventional general purpose embedded processor do not provide the necessary throughput for meeting the applications’ performance and power needs. On the other hand\, manual hardware design is too expensive and results in inflexible implementation. The short time to market demands also make hardware design prohibitive. Therefore\, there exists a need for automatic design methods and tools that provide a high performance\, programmable and energy-efficient implementation starting from standard application descriptions such as C reference code. High level synthesis and application specific processor tools are a step in this direction\, but suffer from scalability\, quality and controllability issues. In this dissertation\, we present techniques for automatic processor design from C code that are scalable to thousands of lines of C code\, are controllable at each step of the design process and provide quality of results comparable to manual design. \nOur contributions enable a system level design methodology for application specific processors that starts with a reference C code of the application. An initial processor data path is constructed from a database of available components such as function units\, register files and buses. The initial data path is based on the types of operations and available concurrency in the application. The data path is then iteratively refined until an efficient architecture is derived. The key optimization goal is to keep performance within given boundaries while maximizing resource utilization. We further optimize the processor design using a novel algorithm for automatic custom pipelining based on the C code. The pipelining optimization also targets both resource utilization and performance. Our experimental results with large applications such as DCT and MP3 decoder show that automatically generated architectures are comparable to manual designs\, but can be obtained in a matter of few seconds\, leading to significant productivity gains. \nOur final contribution to design methods for embedded systems deals with low power memory design. Typically\, DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high\, exceeding that of the data cache or even that of the processor. We present and evaluate a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small\, cache-like structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption\, 23%\, on average\, and reduction in the energy-delay product\, 44%\, on average. The approach also improves performance: the CPI is reduced by 26%\, on average. URL:https://www.cecs.uci.edu/event/automatic-design-and-optimization-of-application-specific-processors/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080709T150000 DTEND;TZID=America/Los_Angeles:20080709T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14325-1215615600-1215619200@www.cecs.uci.edu SUMMARY:Improving Packet Latencies of Live Streams in Wired Networks DESCRIPTION:Improving Packet Latencies of Live Streams in Wired Networks\nby Arijit Ghosh (Advisor: Prof. Tony Givargis)\nDate: July 9\, 2008 \nLive streaming is becoming increasingly popular. In a study published in January 2008\, Cisco predicted that Internet-to-TV video will account for 30% of all Internet traffic. If all kinds of video traffic are considered\, then it will be 90% of consumer traffic by 2012. We distinguish live streams from on demand streams. Live streams are sent as the data is being generated\, is typically of long duration\, requires high bandwidth and associated with flash crowd behavior. As such\, live streams place tremendous demand on network resources. \nIn this thesis\, we proposed network techniques to improve packet latencies of live streams in wired networks. In particular\, we made the following contributions. First\, we proposed a technique that allows multicasting at the access network\, the proverbial last mile which presents tremendous bandwidth limitations. Second\, we reduced nodal processing by a tunelling scheme based on source routing. Essentially\, using routing computed at source and a novel network encoding scheme\, we eliminated intermediate processing. Third\, we presented a queueing algorithm that schedules packets based on application deadlines\, reduces the number of sorting iterations\, thereby improving performance\, has low complexity\, exhibits good fairness and provides a bounded delay for a single packet that is independent of the number of flows. Finally\, we proposed a variation of QoS routing that works with only partial network state information. URL:https://www.cecs.uci.edu/event/improving-packet-latencies-of-live-streams-in-wired-networks/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080708T150000 DTEND;TZID=America/Los_Angeles:20080708T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14326-1215529200-1215532800@www.cecs.uci.edu SUMMARY:xTune: A Formal Methodology for Cross-layer Tuning of Mobile Real-time Embedded Systems DESCRIPTION:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems\nby Minyoung Kim (Advisor: Prof. Nikil Dutt)\nDate: July 8\, 2008 \nResource limited mobile real-time embedded systems can benefit greatly from  dynamic adaptation of system parameters. This thesis proposes a novel framework  xTune that employs iterative tuning using light-weight formal verification at runtime with feedback for dynamic adaptation. One objective of this approach is to enable tradeoff analysis across multiple layers (for example\, application\, middleware\, operating system) and predict the possible property violations as the system evolves dynamically over time. Specifically\, an executable formal specification is developed for each layer of the mobile real-time system under consideration. The formal specification is then analyzed using statistical model checking and statistical quantitative analysis\, to determine the impact of various resource management policies for achieving desired a variety of end-to-end properties in a quantifiable manner. The integration of formal analysis with dynamic behavior from system execution results in a feedback loop that enables model refinement and further optimization of policies and parameters. Finally\, we propose a composition method for coordinated interaction of optimizers at different layers. The core idea of our approach is that each participating optimizer can restrict its own parameters and exchange refined parameters with its associated layers. We demonstrate the applicability of the proposed methodology to the adaptive provisioning of mobile real-time embedded systems by treating a multimedia case study on resource-limited devices. URL:https://www.cecs.uci.edu/event/xtune-a-formal-methodology-for-cross-layer-tuning-of-mobile-real-time-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080616T150000 DTEND;TZID=America/Los_Angeles:20080616T160000 DTSTAMP:20231011T183918Z CREATED:20231011T183918Z LAST-MODIFIED:20231011T183918Z UID:14327-1213628400-1213632000@www.cecs.uci.edu SUMMARY:A Runtime System for Memory-Constrained Distributed Embedded Systems DESCRIPTION:A Runtime System for Memory-Constrained Distributed Embedded Systems\nby Jiwon Hahn (Advisor: Prof. Pai Chou)\nDate: June 16\, 2008 \nWearable and embedded wireless sensor platforms are often highly constrained in size and power consumption in order to operate in unintrusive ways. To meet these constraints\, the memory is kept as small as possible to reduce area and power\, but at the same time it poses new challenges on programming. To address these problems\, this dissertation proposes \n(1) a framework for synthesis of host-assisted scripting engines\, \n(2) a minimum-overhead yet powerful runtime system based on recursive threaded code\, and \n(3) a host-assisted memory optimization technique that exploits high-level knowledge in models of computation. The benefits are three-fold: first\, the interactive access between programmer and embedded system improve productivity of programmers. Second\, the low runtime overhead and memory requirements enable this runtime system to run on compact platforms while providing high flexibility and composability. Third\, a new memory optimization scheme combined with the dispatching structure expose regularity of dataflow models to enable memory and scheduling optimizations\, sometimes in ways better than manual coding. \nExperimental results show that systems developed using these techniques have unleashed the power of these resource-constrained distributed embedded systems. As memory is currently the limiting factor\, the lightweight runtime system and systematic memory optimization technique presented in this dissertation are enabling technology for a new class of real-world\, ultra-compact distributed embedded systems. URL:https://www.cecs.uci.edu/event/a-runtime-system-for-memory-constrained-distributed-embedded-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080604T150000 DTEND;TZID=America/Los_Angeles:20080604T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14328-1212591600-1212595200@www.cecs.uci.edu SUMMARY:Source Re-coding to Create Parallel and Flexible MPSoC Models for Embedded System Design and Exploration DESCRIPTION:by Pramod Chandraiah\, University of California\, Irvine\nJune 4\, 2008\nview details URL:https://www.cecs.uci.edu/event/source-re-coding-to-create-parallel-and-flexible-mpsoc-models-for-embedded-system-design-and-exploration/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080512T150000 DTEND;TZID=America/Los_Angeles:20080512T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14329-1210604400-1210608000@www.cecs.uci.edu SUMMARY:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip DESCRIPTION:COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip\nby Sudeep Pasricha (advisor: Prof. Nikil Dutt)\nDate: May 12\, 2008 \nWith the increasing performance demands of emerging convergence applications and advances in process technology\, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance\, power\, cost and reliability. Consequently\, the design\, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today. \nIn this dissertation\, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis\, comprehensively and automatically generating both the topology and protocol parameters\, while trading off multiple design constraints such as power\, performance\, area and cost.Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality\, better complexity management\, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs. URL:https://www.cecs.uci.edu/event/commsyn-on-chip-communication-architecture-synthesis-for-multi-processor-systems-on-chip/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20080303T150000 DTEND;TZID=America/Los_Angeles:20080303T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14330-1204556400-1204560000@www.cecs.uci.edu SUMMARY:Analysis and Optimization of Transaction Level Models for Multi-Processor System-on-Chip Design DESCRIPTION:by Gunar Schirner\, University of California\, Irvine\nMarch 3\, 2008\nview details URL:https://www.cecs.uci.edu/event/analysis-and-optimization-of-transaction-level-models-for-multi-processor-system-on-chip-design/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20071206T150000 DTEND;TZID=America/Los_Angeles:20071206T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14331-1196953200-1196956800@www.cecs.uci.edu SUMMARY:Synthesis and Optimization of Low-Power Custom NISC Processors DESCRIPTION:by Bita Gorjiara\, University of California\, Irvine\nDecember 6\, 2007\nview details URL:https://www.cecs.uci.edu/event/synthesis-and-optimization-of-low-power-custom-nisc-processors/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070920T150000 DTEND;TZID=America/Los_Angeles:20070920T160000 DTSTAMP:20231011T184119Z CREATED:20231011T184119Z LAST-MODIFIED:20231011T184119Z UID:14332-1190300400-1190304000@www.cecs.uci.edu SUMMARY:Software Architecture for High Data Rate Wireless Body Sensor Applications DESCRIPTION:Software Architecture for High Data Rate Wireless Body Sensor Applications\nby Seung-Mok Yoo \nFor wireless body area sensor networks\, the wearable nodes are highly constrained by low power\, low cost\, and small size while deliverly high throughput and low latency in a multiple access environment. To accomplish these goals\, the hardware must be kept simple\, and as a result\, the traditional abstractions with separate layers of the protocol stack and application must be merged and made as streamlined as possible. This dissertation identifies and removes two bottlenecks with data transfers: one is between the base station and its sensor nodes\, and the other is within the sensor node. \nFirst\, we propose a thin-server\, fat-client architecture. It supports a pulling protocol that achieves intra-network collision-free multiple access as in TDMA but without the time synchronization overhead. It also achieves high data throughput of air bandwidth and adaptivity of CSMA protocols but without collision or complexity on the node side. \nSecond\, for intra-node transfers\, another known bottleneck is the system bus. We identify the double-transaction problem\, which is common to SPI\, DMA\, and other interfaces. We propose the Master-Handoff Protocol to eliminate the redundant transaction and improve latency significantly\, and it is compatible with existing controllers. It not only halves the data transfer time but also achieves energy reduction. Together\, these techniques enable highly constrained hardware to meet strict size and power constraints for high wearability without sacrificing performance. URL:https://www.cecs.uci.edu/event/software-architecture-for-high-data-rate-wireless-body-sensor-applications/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070918T150000 DTEND;TZID=America/Los_Angeles:20070918T160000 DTSTAMP:20231011T184245Z CREATED:20231011T184245Z LAST-MODIFIED:20231011T184245Z UID:14333-1190127600-1190131200@www.cecs.uci.edu SUMMARY:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract DESCRIPTION:No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract\nby Mehrdad Reshadi \nToday\, depending on the size and complexity of a program\, there are two options for synthesizing a program to hardware: (1) using High Level Synthesis (HLS)\, and (2) using Application-Specific-Instruction-Processor (ASIP). \nTraditional HLS techniques can only support relatively small applications and do not give enough control to the designer over the quality of results. Poor quality of results and limited application domain has prevented the HLS from wide spread usage. \nEmbedded processors often run only one or a few applications in the life-time of the system. Therefore\, they can be customized for the target applications and significantly improve the quality of the embedded system in terms of cost\, performance\, power consumption\, etc. This is the goal in ASIP approaches. Instruction-based architectures limit the customizations because: (a) hardware designer is limited by instruction coding\, size and complexity of the decoder; (b) compilers can support certain class of instructions and hence instructions cannot be very complex; and (c) manually updating compilers to incorporate the custom instructions is not practical and developing compilers that automatically utilize hardware customizations through new custom instructions is very complex. \nIn this talk I present a new design approach called NISC (No-Instruction-Set-Computer) Technology. In NISC\, the datapath and controller are generated in two different phases. First the datapath is generated or selected from a database based on the application behavior. At the core of NISC technology\, there is a cycle-accurate compiler that maps a given application directly on a given datapath and generates the control words (CWs) that control the datapath resources in every clock cycle. The NISC architecture style is similar to the old nanocode machines. However\, instead of using nanocodes inside the process for implementing the microcodes and in turn instructions\, in NISC the nanocode (CWs) are directly used to program the datapath. \nNISC simplifies customization and allows designer to fully control design quality. NISC simplifies ASIP (Application-Specific-Instruction-Processor) approach by removing the complex task of finding and designing “most profitable” custom instructions. In NISC only the datapath needs to be specified and NISC compiler generates code “as if” each basic block of the program is executed with one custom instruction. On the other hand\, NISC improves resource constrained HLS techniques by adding the connectivity constraints\, on top of the traditional resource constraints\, into synthesis process. This enables the designer to control every thing in datapath including wires\, which are becoming increasingly more critical in newer technologies. In fact NISC combines the ASIP and HLS techniques. \nTo realize the NISC Technology design flow\, several challenging categories of problems must be solved. Mainly we need: \n1. Techniques for efficiently designing and customizing a datapath for an application\n2. Techniques for efficiently compiling any application on any given datapath\n3. Techniques for efficiently synthesizing a controller from the output of compiler and then generating synthesizable code for different target implementations. \nIn my thesis\, I focus on the compilation problems to enable practical use of NISC IPs in a system. A working compiler and other NISC tools are available for public use from NISC websitehttps://www.cecs.uci.edu/~nisc/. An online version of the tools can be also directly accessed at this website. URL:https://www.cecs.uci.edu/event/no-instruction-set-computer-nisc-modeling-and-compilation-abstract/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070423T150000 DTEND;TZID=America/Los_Angeles:20070423T160000 DTSTAMP:20231011T184245Z CREATED:20231011T184245Z LAST-MODIFIED:20231011T184245Z UID:14334-1177340400-1177344000@www.cecs.uci.edu SUMMARY:Software for Embedded Systems: Serializing Compilers and Its Applications DESCRIPTION:Software for Embedded Systems: Serializing Compilers and Its  Applications\nby Andre Costi Nacul \nIn order to cope with the complexity of systems\, engineers are  turning to software. In part\, well established programming models\,  highly evolved tool chains\, ease of software reuse\, availability of  open-source software\, and expeditious nature of the design-compile- execute paradigm make developing a new feature in software more  favorable. It is assumed that\, in coming years\, more than 70% of  product features are going to be supported by software.\nIn particular\, the concurrent programming paradigm is an ideal model  of computation for design of embedded systems\, which often encompass  inherent concurrency. The support for concurrent programming is  usually provided by a real-time operating system (RTOS). Usually\, an  RTOS is a generic framework which can be used across a large number  of processors and applications. An RTOS provides coarse grained  timing support\, and is loosely coupled to the running tasks. As a  result\, an RTOS is seldom optimized for any particular application. \nDespite of all the recent enhancements to compiler technology\,  current compilers have a limited understanding of tasks. Generally\,  the compiler is tightly integrated with the platform. Traditional  compilers are efficient in using platform specific resources\, and in  generating an optimized instruction sequence. Current compiler  technology is capable of extracting instruction-level parallelism  (ILP)\, to varying degrees. Traditionally\, ILP comes from optimizing  loops\, and most likely analyzes code at the basic block level. Today\,  there is no compiler that can detect parallelism at the task level.  Parallelism detection is usually restricted to basic block  structures\, or higher level constructs such as loops. Moreover\,  compilers also lack support for timing constraints of real-time  applications. \nIn this thesis\, we propose an alternative to an RTOS based on the  idea of serializing compilers. A serializing compiler is an automated  software synthesis methodology that can transform a multitasking  application into an equivalent and optimized monolithic sequential  code\, to be compiled with the embedded processor’s native optimizing  compiler. The serializing compiler can analyze the tasks at compile  time and generate a fine-tuned\, application specific infrastructure  to support multitasking\, resulting in a more efficient executable  than one that is intended to run on top of a generic RTOS. By having  control over the application execution and context switches\, the  serializing compiler enables the fine grain control of task timing  while enhancing overall performance. Our serializing compiler  technology strengthens existing compilers\, making them timing and  task-aware. \nThe Phantom Compiler\, our implementation of a serializing compiler\,  provides a fully automated mechanism to synthesize a single threaded\,  ANSI C/C++ program from a multithreaded C/C++ (extended with POSIX)  program. The Phantom generated code is highly tuned for the input  application. With a serializing compiler such as the Phantom  Compiler\, it is possible to generate a multitasking infrastructure  that is small in size\, very efficient when context-switching\, and  customized for each specific application. URL:https://www.cecs.uci.edu/event/software-for-embedded-systems-serializing-compilers-and-its-applications/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070411T150000 DTEND;TZID=America/Los_Angeles:20070411T160000 DTSTAMP:20231011T184638Z CREATED:20231011T184638Z LAST-MODIFIED:20231011T184638Z UID:14346-1176303600-1176307200@www.cecs.uci.edu SUMMARY:New Strategies for System-Level Design DESCRIPTION:New Strategies for System-Level Design: Where to Go?\nKeynote Talk \n\n\n\n\nSpeaker\n\n\nProfessor Gajski \nElectrical Engineering and Computer Science\nUniversity of California at Irvine\n\n\n\n \n\n\n \n\n\n\nLocation\n\n\nThe 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems\, Kraków\, Poland\n\n\n\n \n\n\n \n\n\n\nDate\n\n\nApril 11\, 2007\n\n\n\n \n\n\n \n\n\n\nAbstract\n\n\nWith complexities of Systems-on-Chip rising almost daily\, the design community has been searching for new vision that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution\, such as increasing levels of abstraction\, introducing variety of IPs or offering new design languages will not solve the problem but only prolong the present status of inefficiency and confusion. What is needed is a drastic change in design automation for complex systems that consist of software and hardware. In order to design such systems efficiently\, we need a new approach with a new design flow\, with new models with well defined semantics and a new formalism that will support system synthesis and verification of software and hardware. \nIn order to find the solution\, we will look first at the system gap between SW and HW designs and derive requirements for the design flow that includes software as well as hardware. In order to enable new EDA tools for model generation\, simulation\, synthesis and verification\, the design flow has to be well defined with unique abstraction levels\, model semantics and model transformations corresponding to design decisions made by the designers. We will introduce the concept of model algebra that supports this approach and can serve as an enabler for the extreme makeover of EDA. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of complex systems to the basic principles of design science only.\n\n\n\n\n\n\n\n\n\n\nSlides\n\n\nDownload slides\n\n\n\n \n\n\n \n\n\n\nBiography\n\n\n  \n\n \n\nDaniel Gajski\, a leader in the areas of embedded systems\, design methodologies and languages\, headed the research teams that created new design concepts\, methodologies\, tools and languages. He was instrumental in developing formalisms such as Y-chart\, and numerous algorithms for high-level synthesis\, the definition of the control-data-flow-graph (CDFG) and finite-state-machine with data (FSMD)\, system level languages such as SpecCharts and SpecC\, and design tools such as SpecSyn and Embedded-System Environment. Many of these concepts have been adapted by academia and industry in the last 25 years. \nGajski directs the UCI Center for Embedded Computer Systems\, with a research mission to incorporate embedded systems into automotive\, communications\, and medical applications. He has authored over 300 papers and numerous textbooks\, including Principles of Digital Design (Englewood Cliffs\, NJ: Prentice Hall\, 1997) that has been translated into several languages. \nHe holds Dipl. Ing. and M.S. degrees in electrical engineering from the University of Zagreb\, Croatia\, and a doctoral degree in computer and information sciences from the University of Pennsylvania\, Philadelphia. After 10 years as Professor at University of Illinois he has joined UCI\, where he presently holds The Henry Samueli Endowed Chair in Computer System Design. URL:https://www.cecs.uci.edu/event/new-strategies-for-system-level-design/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070305T150000 DTEND;TZID=America/Los_Angeles:20070305T160000 DTSTAMP:20231011T184246Z CREATED:20231011T184246Z LAST-MODIFIED:20231011T184246Z UID:14335-1173106800-1173110400@www.cecs.uci.edu SUMMARY:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems DESCRIPTION:Content Annotation for Power and Quality Trade-Offs in Mobile Multimedia Systems\nby Radu Cornea \nRecent advances in processor\, wireless and graphics technology have fueled a convergence of traditional PDA and cellphone functionality into complex\, media-centric mobile devices. A popular class of applications emerging on these platforms is represented by multimedia\, in particular content streaming (video\, audio). However\, all this added functionality has not come without an expense in one of the most important area for a mobile device: battery life. Multimedia streaming in particular\, with its stringent compu tation\, communication and quality of service requirements further aggravates battery life on these already constrained devices. \nOn the other hand\, multimedia applications have very regular execution patterns\, the only changes being introduced by variations in the data stream itself. This thesis presents a new way to optimize power consumption for multimedia applications\, based on content analysis and annotations. Specifically\, we pre-process the multimedia streams and utilize annotations to capture and carry content-related information to the client device at the receiving end. Annotations allow us to perform more accurate and aggressive optimizations\, with knowledge of the actual content and without relying to less accurate prediction models. \nWe investigate the use of annotation for content-aware optimizations at all level of abstraction (hardware/OS\, network\, application) for the most important system components in a mobile device: CPU/memory\, network interface\, display. Our experimental results show that important energy savings can be achieved for all these components through annotations. Finally\, we integrate the techniques at all levels of abstraction for an increased user experience and battery functionality. We also show how cross-layer trade-offs between power and quality can lead to even higher energy savings with minimal quality degradation. URL:https://www.cecs.uci.edu/event/content-annotation-for-power-and-quality-trade-offs-in-mobile-multimedia-systems/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20070205T150000 DTEND;TZID=America/Los_Angeles:20070205T160000 DTSTAMP:20231011T184246Z CREATED:20231011T184246Z LAST-MODIFIED:20231011T184246Z UID:14336-1170687600-1170691200@www.cecs.uci.edu SUMMARY:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications DESCRIPTION:Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications\nby Ilya Michailovich Issenin \nWith increasing processing power demands of embedded applications and technology advances\, Multiprocessor Systems-on-Chip (MPSoCs) become prevalent in embedded systems. The memory subsystem is a large and critical contributor to both energy and performance of such systems\, requiring system designers to perform exploration of low power memory organizations. In this dissertation we present an automated approach for data memory subsystem customization for streaming applications. Our approach allows modification of the program to use custom scratch pad memory configurations comprising a hierarchical set of buffers for local storage of frequently reused data. Our data reuse analysis technique provides the system designer with a wide range of customized memory hierarchy organizations with different size and energy profiles and enables the system designer to explore feasible memory subsystem solutions that satisfy power and area constraints while still meeting task deadlines\, both for uniprocessor and multiprocessor systems. \nIn modern multiprocessor embedded systems the communication subsystem also plays an important role in determining overall system power consumption and performance. We propose novel approaches that enables energy-aware co-synthesis of both memory and communication architectures for streaming applications targeting hierarchical bus-based and Network-on-Chip communication architectures. Our techniques achieve significant reduction in memory and communication subsystems energy consumption for data dominant applications\, and allow system designers to explore custom scratch pad memory configuration for a range of power and area constraints. \nThesis\nSlides URL:https://www.cecs.uci.edu/event/multiprocessor-system-on-chip-data-memory-customization-for-embedded-array-intensive-applications/ CATEGORIES:PhD Defenses END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Los_Angeles:20060302T150000 DTEND;TZID=America/Los_Angeles:20060302T160000 DTSTAMP:20231011T184246Z CREATED:20231011T184246Z LAST-MODIFIED:20231011T184246Z UID:14337-1141311600-1141315200@www.cecs.uci.edu SUMMARY:Acceleration beyond Memory Barriers in IS-extensible Processors DESCRIPTION:Acceleration beyond Memory Barriers in IS-extensible Processors\nby Partha Biswas \nExtensible processors refer to a class of processors that can be customized for a given application with new designer-defined functional units. One popular feature to extend is the Instruction Set (IS) of the processor—we call such a processor an IS-extensible processor. In an IS-extensible processor\, applications can be accelerated by extending the processor architecture with Application-specific Functional Units (AFUs)\, which execute Instruction Set Extensions (ISEs) in the critical segments of the applications. Automatic identification of such ISEs is the key step in automating the process of processor customization. \nA high-quality ISE identification approach needs to obtain results close to those achieved by experienced designers\, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. This thesis develops an ISE identification algorithm (ISEGEN)\, which identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Traditionally\, synchronization issues have discouraged the inclusion of memory operations in ISEs during the ISE identification step\, causing a “memory barrier”. We show in this thesis that it is possible to go beyond these memory barriers and accelerate the application even more than the traditional ISE identification approaches by eliminating costly memory operations. We present the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively. Finally\, we develop an interface-aware processor customization methodology and use the methodology to realize an IS-extensible-processor-based system on a real platform. \nExperimental results on a number of MediaBench\, EEMBC and cryptographic applications demonstrate that our ISEGEN approach matches the quality of the optimal solution obtained by exhaustive search. We show that our ISEGEN technique is on average 20X faster than a genetic formulation that generates equivalent solutions. We also demonstrate the effectiveness of our approach by incorporating the generated ISEs in the cycle-accurate SimpleScalar simulator. The average speedup on the selected benchmarks increases from 1.4X to 2.8X when the ISE identification process goes beyond memory barriers. Furthermore\, we show a concomitant reduction in energy consumption as a result of reduced cache pollution. In addition to analytical and simulation-based evaluation of the identified ISEs\, we implement our approach in a realistic hardware-software system that allows us to comprehensively study the effect of ISEs on performance\, energy\, power\, and code size using our interface-aware processor customization methodology. Our experiments on a Xilinx Virtex II board—employing the Microblaze soft-core as an extensible processor—show a simultaneous increase in performance\, and reduction in code size\, energy and power consumption with the incorporation of the AFU in the Microblaze soft-core processor. URL:https://www.cecs.uci.edu/event/acceleration-beyond-memory-barriers-in-is-extensible-processors/ CATEGORIES:PhD Defenses END:VEVENT END:VCALENDAR