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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190419Z
CREATED:20231011T190419Z
LAST-MODIFIED:20231011T190419Z
UID:14409-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Exploiting Master-Slave Bus Architecture and Storage Devices to Enable High-Performance\, Low-Power Logging for Sensor Systems
DESCRIPTION:By Eunbae YoonJune 24\, 2013 \nread more
URL:https://www.cecs.uci.edu/event/exploiting-master-slave-bus-architecture-and-storage-devices-to-enable-high-performance-low-power-logging-for-sensor-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14408-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Optimizing Program Performance via Similarity\, Using Feature-aware and Feature-agnostic Characterization Approaches
DESCRIPTION:By Rosario CammarotaMay 31\, 2013 \nread more
URL:https://www.cecs.uci.edu/event/optimizing-program-performance-via-similarity-using-feature-aware-and-feature-agnostic-characterization-approaches/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190344Z
CREATED:20231011T190344Z
LAST-MODIFIED:20231011T190344Z
UID:14402-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Out-of-order Parallel Discrete Event Simulation for Electronic System-Level Design
DESCRIPTION:Date/Time: Thursday\, June 6th\, 10:00 a.m. – 11:00 a.m.Location: CECS Conference Room\, Engineering Hall 3206 \nCommittee Members:Rainer Dömer (Chair)Daniel GajskiBrian Demsky \nAbstractThe large size and complexity of the modern embedded systems poses great challenges to design and validation. At the so called electronic system level (ESL)\, designers start with a specification model of the system and follow a systematic top-down design approach to refine the model to different abstraction levels by adding step-by-step implementation details. ESL models are usually written in C-based System-level Description Languages (SLDLs)\, and contain the essential features such as clear structure and hierarchy\, separate computation and communication\, and explicit parallelism. The validation of ESL models typically relies on simulation. Fast yet accurate simulation is highly desirable for efficient and effective system design. \nThe out-of-order parallel discrete event simulation (OoO PDES) is a novel approach for efficient validation of system-level designs by exploiting the parallel capabilities of todays multi-core PCs for system level description languages. OoO PDES breaks the global simulation-cycle barrier of traditional DE simulation by localizing the simulation time into each thread\, carefully delivering notified events\, and handling a dynamic management of simulation sets. Potential conflicts caused by parallel accesses to shared variables and out-of-order thread scheduling are prevented by an advanced predictive static model analyzer in the compiler. As such\, OoO PDES allows the simulator to effectively exploit the parallel processing capability of the multicore system to achieve fast speed simulation without loss of simulation and timing accuracy. \nWe perform simulation experiments on both highly parallel benchmark examples and real- world embedded applications including a JPEG image encoder\, an edge detector\, a MP3 audio decoder\, a H.264 video decoder\, and a H.264 video encoder. Experimental results show that our approach can achieve significant simulation speedup on multicore simulation hosts with negligible compilation cost. \nBased on our parallel simulation infrastructure\, we then propose a tool flow for dynamic race condition detection to increase the observability for parallel ESL model development. It helps the designer to quickly narrow down the debugging targets in faulty ESL models with par- allelism. This approach helps to reveals a number of risky race conditions in our in- house embedded multi-media application models and enabled us to safely eliminate these hazards. Our experimental results also show very little overhead for race condition diagnosis during compilation and simulation. \nOverall\, our work provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development. It helps the embedded system designers to build better products in shorter time-to-market.
URL:https://www.cecs.uci.edu/event/out-of-order-parallel-discrete-event-simulation-for-electronic-system-level-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130524T150000
DTEND;TZID=America/Los_Angeles:20130524T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14401-1369407600-1369411200@www.cecs.uci.edu
SUMMARY:Designer-in-the-Loop Recoding for Creating Safe and Parallel ESL Models
DESCRIPTION:Date/Time: Thursday\, May 30\, 2013\, 10:00 a.m. – 11:00 a.m.Location: CECS Conference Room\, Engineering Hall 3206 \nCommittee Members:Rainer Dömer (Chair)Daniel GajskiFadi Kurdahi \nAbstractThe design complexity of embedded systems increases as more processors and subsystems integrated on one chip. In order to overcome the design bottlenecks and shorten time to market\, system engineers are motivated to design from a higher abstraction level\, namely Electronic System Level (ESL). ESL design methodology has emerged to address the design complexity by supporting HW/SW co-specification and co-simulation\, system design space exploration and high-level synthesis. \nESL design relies on an input ESL model\, namely the specification model. Creating structured and parallel specification models efficiently is a prerequisite for building cost-effective embedded systems in ESL design. Practically\, application reference code is reused to create the ESL models. However\, the referee models lack the necessary characteristics\, such as explicit parallelism\, structural hierarchy and synthesizability\, for ESL design. It is a time-consuming and error-prone process to manuallyrecode the reference models into desired ESL models. \nThis dissertation addresses on the automation gap of recoding. We follow the design-in-the-loop recoding methodology which efficiently combines the automation tools with designer’s knowledge. Our approach aim to expose parallelism in the ESL model and guarantee that the parallel model is safe from race conditions. \nFirst\, we identifies the essential steps in recoding and defines a recoding design flow to create safe and parallel ESL models.Second\, we contribute three automated recoding operations: variable dependency analysis to provide prompt analysis during model development\, race condition analysis to assist verifying and debugging the parallelism and a high-level transformation function to instantly create loop-level parallelism. Third\, we develop a recoding development platform based on Eclipse tointegrate recoding tools and facilitate the designer-in-the-loop approach. \nThe effectiveness of the recoding functions is shown with experiments on a set of embedded applications. Also\, an classroom experiment with 68 graduate students shows our recoding approach using the Eclipse-based recoding platform increases the productivity and reduces errors in parallel ESL model development.
URL:https://www.cecs.uci.edu/event/designer-in-the-loop-recoding-for-creating-safe-and-parallel-esl-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130520T150000
DTEND;TZID=America/Los_Angeles:20130520T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14410-1369062000-1369065600@www.cecs.uci.edu
SUMMARY:Context-based Service Performance Profile Management System in SOA
DESCRIPTION:Date/Time:  Tuesday\, May 28th\, 2:00 p.m. – 3:00 p.m. \nLocation:  Engineering Hall 4106 \nCommittee Chair:Kwei-Jay Lin \nAbstractService-Oriented Architecture (SOA) is a software paradigm for providing a uniform means to discover\, interact with and use capabilities to produce desired effects consistent withmeasurable preconditions and expectation. SOA also provides a framework for service com-position by putting together of a number of services to make a more complex one to fulfill a business process and service reconfiguration by replacing faulty services with better perform-ing services to have seamless business process execution. In general\, service integration tries to maximize the performance of a business process such as to have a minimum latency\, the shortest response time\, the optimal reliability\, an acceptable level of security and so on. Al-though technology exists to optimize the performance in terms of the above QoS attributes\, it still may not meet the need of all users\, since user may have unique service requirement at some specific context. \nIn order to address this issue\, in this dissertation\, we present an approach to improve over-all performance for the execution of business process by considering context-based serviceperformance profile management through Context Manager. Context Manager is designed to collect service performance feedback from users along with their context data\, maintainservice performance profile data\, distinguish influential context for service performance\, pre-dict how the service would perform under user context and provide most-adaptive service for user context.Our experiment results indicate that context manager system effectively maintains service performance profile data\, clearly understands the influence of some specific context attributes on service performance and provides context-adaptive services as users expect. Moreover\, integrating context-awareness into SOA brings significant performance improvement in terms of lower rate of service failure and reconfiguration\, and more optimal response time between service requester and service provider.
URL:https://www.cecs.uci.edu/event/context-based-service-performance-profile-management-system-in-soa/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130513T150000
DTEND;TZID=America/Los_Angeles:20130513T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14400-1368457200-1368460800@www.cecs.uci.edu
SUMMARY:Embedded Computer Vision Systems for Image Based Motion and Speckle Image Analysis
DESCRIPTION:Date/Time:  Friday\, May 10\, 2013\, 2:00 p.m. – 3: 00p.m.Location:  4011 Donald Bren Hall \nCommittee Members:\nPai H. Chou (Chair)\nBernard Choi\nGlenn Healey\n \nAbstract:  Motion is common in taking images using conventional cameras. If there is motion either on camera or the object or on the both sides during the exposure time\, the image is blurred\, which is called motion blurred image. Motion blurred image is an interesting research subject in several areas including computer vision\, biomedical engineering. In general\, motion is undesirable to acquire clear image. Modern cameras are equipped with the mechanical structure to compensate motion artifact. However\, mechanical structure has limit in compensating huge motion. To compensate huge motion\, computer vision algorithm called motion deblurring is developed. Basically\, it estimates the best latent image from the blurry image using several assumptions (or priors) on the latent image and camera motion. The information included in the motion blur can be useful for biomedical applications. Laser speckle imaging is one good example. When laser light of certain frequency (visible laser is widely used) is illuminated on the skin\, the scattered laser light from the surface has random distribution if there is no motion. With motion\, the speckle pattern is interfered by the motion and no longer random for the region with motion. Since the laser light can penetrate into skin\, it is possible to measure blood perfusion near skin without invasion. Both motion deblurring and laser speckle imaging require huge computation time. That is the reason why they are developed on personal computers or workstations. However\, the physical size\, power consumption\, and cost make them harder to penetrate into wider-range of applications (e.g. A super-fast motion deblurring algorithm that can run on embedded platforms like portable digital cameras or smart phones or portable laser speckle imaging system for an emergency vehicle). Nowadays\, embedded processors become more and more powerful. The CPU clock frequency of those processors have already passed 1Ghz. Some of them use multiple number of cores for processing like x86 processors. However\, even with such high performance processors\, special design considerations are required. In this dissertation\, we suggest embedded hardware and software systems for motion deblurring and laser speckle imaging applications. In the first part of the dissertation\, we will discuss about our motion deblurring systems. We developed an extremely light-weight motion deblurring algorithm to make it fast enough to be suitable for embedded computing platforms. The developed algorithm is up to 100 times faster than the most recent deblurring algorithms. We also developed a hardware/software system for extremely accurate motion deblurring. The hardware system is composed of IMU\, a control board\, and the Microsoft Kinect. Using the hardware system and software algorithm\, our system can reconstruct the relative motion of each pixel during the exposure time with 6-DoF. The second part is about the embedded laser speckle imaging systems that we developed. The mobile LSI (mLSI) system is a battery-powered laser speckle imaging system to meet the portability requirements of special applications (e.g. emergency vehicle\, battle field). We designed the automated power control (APC) circuit based laser diode driver to reduce the power consumption while maintaining the accuracy of the data. We evaluated the pulsed operation of the laser diode with always-on operation using the driver. The mLSI system showed equivalent performance from the evaluation with the clinical LSI system. The small field of view of conventional LSI systems is not adequate to be used for the applications that require fast treatment on large area (e.g. burn wounds). The multi-camera LSI (mcLSI) system was developed to address the requirement. mcLSI shows significant improvement in spatio-temporal resolution over conventional LSI systems. The unit based design enables users to expand the FoV without the sacrifice of the system performance (e.g. average speckle contrast\, spatial/temporal resolution).
URL:https://www.cecs.uci.edu/event/embedded-computer-vision-systems-for-image-based-motion-and-speckle-image-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130508T150000
DTEND;TZID=America/Los_Angeles:20130508T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14399-1368025200-1368028800@www.cecs.uci.edu
SUMMARY:Cooperative Communication for Wireless Physical Layer Security
DESCRIPTION:Date/Time: Friday\, May 10\, 2013\, 11:00 a.m. – 12:00 p.m.Location: 3206 Engineering Hall  \nCommittee Members:Professor A. Lee Swindlehurst (Chair)Professor Ender AyanogluProfessor Ahmed Eltawil \nAbstract:Cooperative communication in relay networks facilitates high spectral efficiency and large wireless transmission coverage. Despite the advances of improved cooperative diversity and flexible node deployment\, the relay network has more transmission nodes exposed in wireless environment than conventional single hop network\, and also extends the area over which the private transmitted signals may be intercepted by unintended receivers or eavesdroppers. Unlike the traditional approach of cryptographic design in the application layer\, in this work we investigate security issues in relay networks from a physical layer perspective. \nWe start with a two-hop multiple-input multiple-output (MIMO) relay network and propose cooperative beamforming and jamming strategies to maximize the secrecy rate. The corresponding power allocation is also optimized via geometric programming. Both cases with known and unknown eavesdropper’s channel state information (ECSI) are considered. Next\, we study a case where the relay is untrusted although it helps with forwarding message to the destination. The exact secrecy outage probability (SOP) is characterized with the impact of the number of antennas at the relay. Antenna selection\, beamforming and node selection schemes are proposed to suppress the wiretapping ability of the untrusted relay. Then we consider utilizing a buffer-aided relay that can dynamically control its receive and transmit phases. A link selection scheme that takes into account both the two-hop transmission efficiency and security constraints is proposed and shown to significantly improve the secrecy throughput. Finally\, we study robust transmit design when the relay acts as a pure cooperative jammer. The ECSI is assumed to be partially known and norm-bounded. The transmit covariance matrices are optimized via semidefinite programming\, based on maximizing the worst-case secrecy rate. Through this work\, we show that by taking advantage of the features of relay networks\, the security performance can be significantly improved in terms of secrecy rate and secrecy outage probability.
URL:https://www.cecs.uci.edu/event/cooperative-communication-for-wireless-physical-layer-security/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130322T150000
DTEND;TZID=America/Los_Angeles:20130322T160000
DTSTAMP:20231011T190322Z
CREATED:20231011T190322Z
LAST-MODIFIED:20231011T190322Z
UID:14398-1363964400-1363968000@www.cecs.uci.edu
SUMMARY:Delft Reconfigurable VLIW Processor
DESCRIPTION:Speaker: Prof. Stephan Wong\, Computer Engineering Laboratory\, Delft University of Technology\, NetherlandsLocation: 2111 Engineering HallDate/Time: Tuesday\, March 26\, 2013\, 2:00pm to 3:00pmView Details 
URL:https://www.cecs.uci.edu/event/delft-reconfigurable-vliw-processor/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20121128T150000
DTEND;TZID=America/Los_Angeles:20121128T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14392-1354114800-1354118400@www.cecs.uci.edu
SUMMARY:Power-Saving Method for DRAM/eDRAM and 3D-DRAM expoliting the process variations\, temperature changes\, device degradation\, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service
DESCRIPTION:Date/Time: Friday\, December 7\, 2012\, 3:30-5:00PM\nLocation: Engineering Hall 3206 \nCommittee Members:\nProfessor Fadi Kurdahi (Chair)\nProfessor Ahmed Eltawil \nAbstract:\nIn this dissertation\, we have devised an innovative approach to dynamically set supply voltages and refresh cycle for Dynamic Random Access Memory (DRAM) and 1T1C embedded Dynamic Random Access Memory (eDRAM). The approach helps us to reduce power consumption. The DRAM/eDRAM is usually designed to sustain the worst operating conditions\, and the chip is very rarely operated under these conditions. We exploit the design slack while operating under more favorable conditions to power consumptions. Simulation results indicate that power consumption can be saved more than 10 times when the chip is normally operated. This keeps the chip cool and the operating temperature will be well under control\, which helps in averting device degradation and ultimate breakdown. In addition\, it is possible to extend the eDRAM data retention time\, which helps to improve the memory availability and system performance. Then a mixed-signal controller that implements our algorithm is presented in detail. Our proposed control circuit dynamically adjusts the supply voltages and the refresh cycle with an awareness of process variations\, temperature changes\, and device degradation to minimize power consumption or maximize memory availability. We use the Predictive Technology Model(PTM) 45nm to design and simulate the controller. The silicon area of the controller is only 0.052 mm2which is equivalent to the area of a 1.5 Megabit memory array. It operates at 100 MHz frequency and consumes about 260µW. Compared to a circuit which is designed to accommodate the worst case scenario\, we can save power consumption or extend the memory availability more than ten times when our chip operates under normal conditions. After that an innovative memory management approach which utilize both 3D-DRAM and external DRAM (ex-DRAM) is presented. Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive\, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads\, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for “latency sensitive”\, “bandwidth sensitive”\, and “insensitive” applications. To improve the performance and satisfy a certain level of QoS\, memory blocks of distinct application types are allocated differently. Compared to the scratchpad memory management mechanism\, the average memory access latency of our approach decreases by 19% and 23%\, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover\, using our approach\, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead\, particularly for applications which have high spatial memory locality. Finally\, we present a power-saving method for 3D-DRAM with an awareness of memory access workload variations. We dynamically and independently adjust supply voltages and refresh cycles of different 3D-DRAM dies to minimize their power consumption in the active and idle states. In fact\, the same power saving method for DRAM/eDRAM\, which exploits the design slack due to process variations and temperature changes\, is applied for 3D-DRAM. In both states\, we can still read/write normally and our method does not cause any performance overhead. The difference between these two states is the mechanism to minimize the power consumption: read/write operations and refresh operations consume the most power in the active and the idle state respectively. In addition\, we implement a memory relocation mechanism so that recently accessed memory blocks are gathered together into common 3D-DRAM dies. That allows the others to be in the idle state to save power consumption. The memory relocation mechanism is also an extension of the proposed heterogeneous memory management approach. The overhead of our memory relocation mechanism is negligible. Our simulation shows that if there is no memory access (all 3D-DRAM dies change into the idle state) our method can save power consumption up to 75%. If the memory access workload is low\, our method can save power consumption by almost 50%.
URL:https://www.cecs.uci.edu/event/power-saving-method-for-dram-edram-and-3d-dram-expoliting-the-process-variations-temperature-changes-device-degradation-and-memory-access-workload-variations-and-innovative-heterogeneous-memory-man/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14308-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Millimeter-Wave Circuits for W-band Applications
DESCRIPTION:Location:Calit2 3355\nDate and Time: March 8th\, 2012\, 10:00AM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Filippo Capolino\nProfessor A. Lee Swindlehurst \nTitle: Silicon-Based Millimeter-Wave Circuits for W-band Applications \nAbstract:\nHistorically\, monolithic microwave integrated circuits (MMICs) have been designed using III-V semiconductor technologies\, such as GaAs and InP. In recent years\, the number of publications reporting silicon-based millimeter-wave (mm-wave) transmitter\, receivers\, and transceivers has grown steadily. For mm-wave applications including gigabit/s point-to-point links (57-64 GHz)\, automative radar (77-81 GHz) and imaging (94 GHz) to reach mainstream market\, the cost\, size and power consumption of silicon-based solution has to be significantly below what is being achieved today using compound seminconductor technology. This dissertation focuses the effort of designing and implementing silicon-based solutions through circuit- and system-level innovation for applications in the W-band frequency band (750110GHz)\, in particular\, 94GHz passive imaging band. \nA W-band front-end receiver in 65nm CMOS based entirely on slow-wave CPW (SW-CPW) with frequency tripler as the LO is designed and measured. The receiver achieves a total gain of 35-dB\, -3dB-BW of 12 GHz\, a NF of 9-dB\, a P1-dB of -40dBM\, a low power consumption of 108mW under 1.2/0.8V. This front-end receiver chipset in conjuction with an analog back-end can be used to form a radiometer. \nLeveraging the work done in 65nm CMOS\, the first integrated 2×2 focal-plane array (FPA) for passive imaging is implemented in a 0.18um SiGE BiCMOS process (ft/fmax=200/180GHz). The FPA incorporates four Dicke-type receivers. Each receiver employs a direct-conversion architecture consisting of an on-chip slot dipole antenna\, an SPDT switch\, a lower noise amplifier\, a single-balanced mixer\, an injection-locked frequency tripler (ILFT)\, a zero-IF variable gain amplifier\, a power detector\, an active bandpass filter and a synchronous demodulator. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four ILFTx. This work demonstrates the highest level of integration of any silicon-based systems in the 94GHz imaging band. \nFinally\, the main design bottleneck of any wireless transceiver system\, the frequency synthesizer/phase-locked loop is investigated. Two monolithically integrated W-band frequency synthesizer are presented. Implemented in a 0.18um SiGe BiCMOS\, both architectures incorporate the same 30.3-33.8GHz PLL core. One sythesizer uses an injection-locked frequency tripler (ILFT) with locking range of 92.8-98.1GHz and the other employ a harmonic-based frequency tripler (HBFT) with 3-dB bandwidth of 10.5GHz from 90.0-101.4GHz\, respectively. The frequency sythesizer is suitable for integration in mm-wave phased array and multi-pixel systems such as W-band radar/imaging and 120GHz Gb/s communication.
URL:https://www.cecs.uci.edu/event/silicon-based-millimeter-wave-circuits-for-w-band-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14307-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging
DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: March 8th\, 2012\, 2:00-3:30PM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Michael Green\nProfessor Peter Burke \nTitle: Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging \nAbstract:\nSilicon technology\, with its superior integration capability and low cost\, has changed the world dramatically during the past few decades and recently has entered the realm of millimeter-wave (MMW) system design that is used to be dominated by III-V compound semiconductor technologies. Benefiting from the continuous feature size scaling of silicon technology\, passive MMW imagers could be built on chip which paves the way for developing low-cost\, compact wafer-scale imagers. This dissertation focuses on the design of fully integrated W-band passive imager and also covers the design of W-band synthesizer which is one of the most critical and challenging building blocks of the imaging receiver. Two chips for 96GHz frequency generation incorporating the same Ka-band PLL and (1) an injection-locked frequency tripler (ILFT); (2) a harmonic-based frequency tripler (HBFT) in 0.18?m SiGe BiCMOS (fT/fmax=200/180GHz) are presented. The ILFT and HBFT preceded by the same Ka-band PPL achieve measured closed-loop phase noise of -93dBc/Hz and -92dBc/Hz at 1MHz offset\, respectively. Both chips are designed under the same power consumption of 14mW from 1.8V/2.5V supplies. This work presents the first implementation of an injection-locked-based frequency multiplier in SiGe BiCMOS process. W-band transformer-based injection-locked frequency tripler (T-ILFT) is also designed and implemented in 65nm standard CMOS technology using a 0.8V supply voltage. THe use of injection locking topology with on-chip transformer provides several advantages over conventional design. A fully integrated W-band 2×2 focal-plane array (FPA) for passive millimeter-wave imaging is demonstrated in 0.18?m SiGe BiCMOS process. The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture with an on-chip slot folded dipole antenna. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. This imaging receiver (without antenna) achievers a measured average responsivity and noise equivalent power of 285MV/W and 8.1fW/Hz1/2\, respectively\, across the 86-106GHz bandwidth\, which results a calculated NETD of 0.48K with a 30ms integration time. The system NETD increases to 3K with on-chip antenna due to its low efficiency at W-band. This work demonstrates the highest integration level of any silicon-based systems in the 94GHz imaging band.
URL:https://www.cecs.uci.edu/event/silicon-based-integrated-circuits-for-w-band-fully-integrated-passive-imaging/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120514T150000
DTEND;TZID=America/Los_Angeles:20120514T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14306-1337007600-1337011200@www.cecs.uci.edu
SUMMARY:Enhancing Quality of Viewing Experience for Future Mobile Video Applications
DESCRIPTION:by Kiarash Amiri May 14\, 2012 view details
URL:https://www.cecs.uci.edu/event/enhancing-quality-of-viewing-experience-for-future-mobile-video-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120223T150000
DTEND;TZID=America/Los_Angeles:20120223T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14309-1330009200-1330012800@www.cecs.uci.edu
SUMMARY:Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures
DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: February 23\, 2012\, 3:30pm – 5:30pm \nCommittee:\nProfessor Ahmed Eltawil (Chair)\nProfessor Ender Ayanoglu\nProfessor Fadi Kurdahi \nTitle: Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures \nAbstract:\nMIMO communication has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. However\, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity. In this thesis\, we present efficient design for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels. We consider that the MIMO detector and the channel decoder are two major blocks and attempt to optimize them in a joint sense. First of all\, we will focus on the design of MIMO detector and propose two approaches. The first design presents a novel algorithm and architecture for K-Best detection. The algorithm examines a much smaller subset of points in the tree structure while still achieving near-optimal performance. The VLSI architecture of the detector is based on a pipelined sorter-free scheme such that high throughput is achieved. The second design demonstrates an algorithm and VLSI architecture of combining the features of classical depth-first and breadth-first methods. Techniques to reduce complexity while providing both hard and soft output detection are also presented. Finally we will present an approach to perform joint detection and decoding for MIMO systems using convolutional codes. The BER performance of this approach is significantly better than that of systems which utilize separate detection and decoding blocks. The proof of concept VLSI architecture is provided and a novel way to reduce memory usage is demonstrated.
URL:https://www.cecs.uci.edu/event/tree-search-based-mimo-detectors-algorithms-and-vlsi-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20111027T150000
DTEND;TZID=America/Los_Angeles:20111027T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14310-1319727600-1319731200@www.cecs.uci.edu
SUMMARY:Energy Harvesting and Power Optimization for Remote Sensing Systems
DESCRIPTION:Energy Harvesting and Power Optimization for Remote Sensing Systems\nby Sehwan Kim \nLocation: Engineering Gateway – CEE Conference Room \nDate and Time: October 27\, 2011 2:00pm \nCommittee:\nProf. Pai Chou (Chair)\nProf. Masanobu Shinozuka\nProf. Maria Feng \nAbstract:\nThe mobile and wireless micro-sensors suffer from short operational lifetimes because they lack space to store the energy that wireless transmission\, signal conditioning\, and monitoring require to operate across time. Energy harvesting capabilities enable totally untethered operation of mobile and wireless micro-sensors for extended periods of time without requiring battery replacement. This paper is to introduce and discuss the design challenges associated with harvesting circuits when harnessing\, conditioning\, and transferring power from ambient energy sources. In addition\, supercapacitors have emerged as an increasingly viable alternative to batteries for micro-solar energy harvesters. To address the problems of high leakage and high unusable residual charge\, previous work proposed multiple supercapacitors with a reconfigurable topology. We propose to optimize such systems by two ways: selection of optimal sizes of the supercapacitors at design time\, and choosing the optimal series or parallel topology at run time. This combination enables the supercapacitor subsystem to maximize the energy storage while minimizing leakage and residual energy\, thereby enabling the maximum utility of the energy storage elements over different operating scenarios.
URL:https://www.cecs.uci.edu/event/energy-harvesting-and-power-optimization-for-remote-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110928T150000
DTEND;TZID=America/Los_Angeles:20110928T160000
DTSTAMP:20231011T183525Z
CREATED:20231011T183525Z
LAST-MODIFIED:20231011T183525Z
UID:14311-1317222000-1317225600@www.cecs.uci.edu
SUMMARY:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures
DESCRIPTION:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures\nby Amir Hossein Gholamipour \nCommittee:\nProf. Fadi Kurdahi (chair)\nProf. Ahmed Eltawil\nProf. Michael Dillencourt \nAn increasing number of digital systems\, from wireless devices to multi-media terminals\, are characterized by their multi-mode operation. This refers to the ability of a system to modify its characteristics or behavior based on user inputs or changes in the operational environment. FIR filters are frequently used in the operation of multi-mode systems due to their inherent stability and linear phase. In majority of such systems implementing a multi-mode FIR filter is the challenge in realizing the multi-mode behavior. FIR filters used for each mode of operation have different sets of parameters (coefficient sets). To implement multi-mode FIR filters\, General Purpose processors are incompetent in delivering the performance while Application Specific Integrated Circuits (ASICs) do not support the required flexibility. On Partially reconfigurable FPGA platforms we can optimize a filter structure based on the fixed parameters of filter and change the mode of operation by reconfiguring the fabric. However the reconfiguration overhead in this approach is not negligible. \nIn this work we introduce an approach which produces a spectrum of filter designs which trade-off area for reconfiguration overhead. In this thesis I prove that the problem of filter optimization can be solved in polynomial time. Furthermore as filter designs in the sequence of reconfiguration have similarities in their parameter sets\, we propose to jointly optimize their designs to further reduce the reconfiguration overhead. We consider the physical limitations of implementing multi-mode filters on FPGAs and propose a placement-aware approach to account for those limitations. Our placement-aware approach is an additional step called /Mapping/ that is introduced before floorplanning the design. In my work\, I show that mapping is an NP-hard problem and I propose ILP formulation and heuristics to solve it. As the result of my research\, I have developed a tool which gets the description of a sequence of filters as an input and generates the RTL design of the filters in VHDL code. It then gives hints on how to map the modules of the design to physical regions on the FPGA chip. This design approach has been tested on a rich set of applications including “preamble detection” unit of OFDMA receivers\, template matching and matched-filter based spectrum sensors. The results show the importance of this approach and the efficiency of the solutions proposed.
URL:https://www.cecs.uci.edu/event/comprehensive-multi-level-joint-optimization-for-multi-mode-fir-like-structures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110903T150000
DTEND;TZID=America/Los_Angeles:20110903T160000
DTSTAMP:20231011T183525Z
CREATED:20231011T183525Z
LAST-MODIFIED:20231011T183525Z
UID:14312-1315062000-1315065600@www.cecs.uci.edu
SUMMARY:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story
DESCRIPTION:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story\nby Houman Homayoun \nLocation: Bren Hall 4011 \nDate and Time: September 3\, 2011 2:30pm \nCommittee:\nProfessor Fadi Kurdahi (Chair)\nProfessor Alex Veidenbaum\,\nProfessor Jean-Luc Gaudiot\,\nProfessor Alex Nicolau. \nAbstract:\nLeakage currents in on-chip SRAMs: caches\, branch predictor\, register files and TLBs\, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines\, making remaining SRAM components\, in particular large drivers\, the primary source of leakage. We proposes an integrated circuit and architectural approach to reduce this source of leakage in all major SRAM-based units of the processor\, controlling them in a uniform way\, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Various low-power modes are defined\, from basic to ultra-low power\, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to be significant for all SRAM units. Resulting temperature reduction\, including the effect of positive feedback between temperature and leakage power\, is evaluated. A significant temperature reduction is achieved in each unit.
URL:https://www.cecs.uci.edu/event/beyond-memory-cells-for-leakage-and-temperature-control-in-sram-based-units-the-peripheral-circuits-story/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20101129T150000
DTEND;TZID=America/Los_Angeles:20101129T160000
DTSTAMP:20231011T183701Z
CREATED:20231011T183701Z
LAST-MODIFIED:20231011T183701Z
UID:14313-1291042800-1291046400@www.cecs.uci.edu
SUMMARY:Aggressive Power Management Utilizing Embedded Memory Fault Tolerant Adaptation For Wireless/Multimedia Systems
DESCRIPTION:Aggressive Power Management Utilizing Embedded Memory Fault Tolerant Adaptation For Wireless/Multimedia Systems\nby Amin Khajeh Djahromi \nLocation: Engineering Hall 2111 \nDate and Time: November 29\, 2010 4:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Stephen Jenks\nProf. Rainer Doemer \nAbstract:\nDesigners of next generation Systems-on-Chip (SoCs) face daunting challenges in generating high yielding architectures that integrate vast amounts of logic and memories in a minimum die size\, while simultaneously minimizing power consumption. Traditional design approaches attempt to guarantee 100% error-free SoCs. However\, advanced manufacturing technologies will make it economically impractical to insist on a 100% error-free SoC in terms of area and power. Fortunately\, many important application domains (e.g.\, communication and multimedia) are inherently error-aware\, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. In such systems\, the share of the SoC that is dedicated to embedded memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoC for most recent advanced wireless standards. Furthermore\, a large portion of the memory is typically used for buffering data that already has a high level of redundancy. \nFinally\, from a network perspective\, buffering memories are transparent across a hierarchy since they do not change the nature of the data stored\, which allows for simple and efficient cross- layer techniques. In my thesis I investigated the effect of voltage over scaling on the embedded memories functionality. Then I proposed fault tolerant adaptive voltage scaling and adaptive body biasing as a mean of reducing power consumption in embedded memories. These techniques tradeoff reliability versus power savings as a function of the time varying quality of the incoming data\, as long as the signal to noise ratio at the decision device is maintained at a desirable level. Moreover\, I addressed the notion of error-awareness across different abstraction layers physical\, application\, network\, and technology for the next generation SoCs. I showed that utilizing proposed techniques on embedded memories (mainly through aggressive ! voltage scaling) will result in a) appreciable power reduction in wire less systems depending on the application\, b) savings in cost and area by reducing or eliminating the need for circuit redundancy\, and c) achieving a higher “effective yield” by tolerating errors at the system level while keeping other parameters constant.
URL:https://www.cecs.uci.edu/event/aggressive-power-management-utilizing-embedded-memory-fault-tolerant-adaptation-for-wireless-multimedia-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100907T150000
DTEND;TZID=America/Los_Angeles:20100907T160000
DTSTAMP:20231011T183701Z
CREATED:20231011T183701Z
LAST-MODIFIED:20231011T183701Z
UID:14314-1283871600-1283875200@www.cecs.uci.edu
SUMMARY:Leveraging Profile-Selected Execution Patterns for Optimized Code Execution in Resource-Constrained Systems
DESCRIPTION:Leveraging Profile-Selected Execution Patterns for Optimized Code Execution in Resource-Constrained Systems\nby Carmen Badea \nLocation: Bren Hall 3013 \nDate and Time: September 7\, 2010 11:00am \nCommittee:\nProf. Alex Nicolau (Chair)\nProf. Alex Veidenbaum\nProf. Nikil Dutt \nAbstract:\nEmbedded systems and related devices have become ubiquitous in today’s world and are expected to proliferate even further. The execution performance for such devices is of paramount importance and is often perceived as the limiting factor w.r.t. both the capabilities of the system\, as well as the user perception. Furthermore\, unlike traditional general-purpose computing systems\, these devices exhibit further inherent constraints due to their nature: memory and energy consumption. \nIn order to overcome the intrinsic drawbacks of Java execution for resource-constrained systems\, we propose to use dynamic profile-selected\, optimized execution patterns in order to build a lightweight Java execution environment\, targeting resource-constrained systems\, that achieves competitive Java runtime performance\, while having negligible impact on memory footprint\, as well as reducing the overall energy consumption. \nMore recently\, with the advancements in the web application technology\, the browser has emerged as the favorite platform for deploying many applications\, in particular for embedded devices such as smartphones. As such\, we investigated whether the use of frequent execution patterns selected as directed by dynamic profiling would be beneficial for browser execution performance. With the use of collected dynamic profiling data indicating the most frequent patterns of execution we were able to develop a browser prototype that delivers significant runtime performance speedups.
URL:https://www.cecs.uci.edu/event/leveraging-profile-selected-execution-patterns-for-optimized-code-execution-in-resource-constrained-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100903T150000
DTEND;TZID=America/Los_Angeles:20100903T160000
DTSTAMP:20231011T183701Z
CREATED:20231011T183701Z
LAST-MODIFIED:20231011T183701Z
UID:14315-1283526000-1283529600@www.cecs.uci.edu
SUMMARY:Framework for Spiking Neural Network Modeling on High-Performance Architectures
DESCRIPTION:Framework for Spiking Neural Network Modeling on High-Performance Architectures\nby Jayram Moorkanikara Nageswaran \nCommittee: \nProf. Nikil Dutt (chair)\nProf. Jeffrey L Krichmar\nProf. Alex Nicolau\nProf. Alex Veidenbaum \nSpiking neural network (SNN) models are emerging as a plausible paradigm for characterizing neural dynamics in the cerebral cortex. Traditionally these SNN models were simulated on large-scale clusters\, super-computers\, or on dedicated VLSI architectures. Alternatively\, Graphics Processing Units (GPUs) can provide a low-cost\, programmable\, and high-performance computing platform for simulation of SNNs. This thesis proposes a systematic framework for modeling and simulation of biologically realistic large-scale spiking neural networks on high-performance graphics processors. \nThe first part of the framework consists of a high-level specification to quickly build arbitrary\, large-scale spiking neural network for different applications. The high-level SNN specification is then converted to a sparse adjacency matrix representation and mapped on the GPUs. Further\, we present a collection of new techniques related to parallelism extraction\, mapping of irregular communication\, and compact adjacency matrix representation for effective simulation of SNNs on GPUs. The last part of the generic framework proposes an evolutionary approach to automate parameter tuning in spiking neural networks. We demonstrate the validity of this framework by applying to three different spike-based computation problems. Significant improvements in modeling\, simulation and parameter tuning time have been achieved by these approaches.
URL:https://www.cecs.uci.edu/event/framework-for-spiking-neural-network-modeling-on-high-performance-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100519T150000
DTEND;TZID=America/Los_Angeles:20100519T160000
DTSTAMP:20231011T183702Z
CREATED:20231011T183702Z
LAST-MODIFIED:20231011T183702Z
UID:14316-1274281200-1274284800@www.cecs.uci.edu
SUMMARY:Code Layout Optimization for Remote Progressive Code Update for Networked Embedded Systems
DESCRIPTION:Code Layout Optimization for Remote Progressive Code Update for Networked Embedded Systems\nby Jinsik Kim \nLocation: Engineering Hall 2111 \nDate and Time: November 18\, 2009 2:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Tony Givargis\nProf. Rainer Doemer \nAbstract:\nMany embedded systems need to have their firmware updated several times over the lifetime of the system after deployment. While those based on binary differencing suffer from unpredictable code shift\, overwriting the entire firmware image may be too costly for those connected by slow\, unreliable\, or expensive data links. In other words\, firmware update over a network connection is an essential but expensive feature for many embedded systems due to the relatively high power consumption and limited bandwidth. \nTo solve these problems\, we propose a new technique by exploiting high-level knowledge about the source program structure in laying out the binary image. Specifically\, we show that by laying out code in order of the cyclomatic complexity of the routines\, the code will evolve with minimal Hamming distance between successive revisions as the code evolves. This code layout technique has the benefits of minimizing bandwidth and power requirements for remote firmware update while also minimizing the wearing of the non-volatile program memory.For another target physical memory\, our work proposes a page-level\, link-time technique that minimizes not only the size of patching scripts but also perturbation to the firmware memory\, over the entire sequence of updates in the system’s lifetime. Experimental results show our technique to reduce the energy consumption of firmware update by 30–42% over the state-of-the-art.
URL:https://www.cecs.uci.edu/event/code-layout-optimization-for-remote-progressive-code-update-for-networked-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20091118T150000
DTEND;TZID=America/Los_Angeles:20091118T160000
DTSTAMP:20231011T183702Z
CREATED:20231011T183702Z
LAST-MODIFIED:20231011T183702Z
UID:14317-1258556400-1258560000@www.cecs.uci.edu
SUMMARY:Low-Complexity and High-Throughput Protocols for Wireless Sensor Networks
DESCRIPTION:Low-Complexity and High-Throughput Protocols for Wireless Sensor Networks\nby Chongjing Chen \nLocation: Engineering Hall 2210 \nDate and Time: November 18\, 2009 2:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Stephen Jenks\nProf. Rainer Doemer \nAbstract:\nWireless technologies have enabled mobility and convenience by eliminating cumbersome wires. Wireless sensor nodes must be made small and low power without sacri?cing performance. In addition to task scheduling\, the densely distributed wireless sensor nodes must run communication protocols to achieve better utilization and reliable communication. While many researchers work on wireless sensor networks that are densely distributed\, they assume low duty cycling and trivial data rate. Unfortunately\, this is a great mismatch with many real-world applications that require the high data rate. Furthermore\, most wireless communication protocols are too complicated to be used on compact wireless sensor nodes with limited RAM and ROM. \nTo address these issues\, we propose a lightweight multiple access control protocol to enable relatively high data rate and densely distributed deployment. It can achieve reliable communication on resource-constrained wireless sensor nodes and minimizes the protocol complexity to reduce the memory footprint. The protocol can also work under high utilization of air bandwidth without collision. While civil engineers are concerned about the sampling rate at 100 Hz for structure monitoring\, our system with this protocol can scale up to 50 wireless sensor nodes and stream real-time data in the same frequency channel at 100 Hz sampling rate. We also propose a compact\, multi-channel protocol with high scalability and small memory footprint. This multiple access control protocol enables wireless sensor nodes to transmit sensing data over multiple frequency channels to achieve a higher throughput than a system with only a single frequency channel. We integrate our protocol with a giant tiled display system\, HIPerWall\, to show the real-time sensing data at a high resolution without downsampling. Last\, we perform a thorough evaluation to study the channel characteristics of a wearable wireless sensor node. We vary several di?erent parameters\, the RF transmission power\, distance\, height\, and angle to observe the packet loss rates. These experimental results can be used for constructing a more reliable wireless communication for wireless sensor networks.
URL:https://www.cecs.uci.edu/event/low-complexity-and-high-throughput-protocols-for-wireless-sensor-networks/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090901T150000
DTEND;TZID=America/Los_Angeles:20090901T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14318-1251817200-1251820800@www.cecs.uci.edu
SUMMARY:Algorithmic Code Optimization Using Conditional Expression Evaluation
DESCRIPTION:Algorithmic Code Optimization Using Conditional Expression Evaluation\nby Mohammad Ali Ghodrat \nLocation: Bren Hall 3011 \nDate and Time: September 1\, 2009 10:30am \nCommittee:\nProfessor Tony Givargis (Chair)\nProfessor Alex Nicolau\nProfessor Nikil Dutt \nAbstract:\nSoftware is becoming a larger fraction of engineering effort. Aggressive compiler optimization\, in particular those that address loops\, can significantly improve the performance of the software\, thus justifying the additional compilation time requirements. This is in particular true in the embedded system domain where software has become a key element of the design process and performance/energy is of a critical concern. A particular area in software optimization\, where little work has been established\, is control flow performance and energy optimization\, which is the main focus of this thesis. \nArithmetic expressions are the fundamental building blocks of hardware and software systems. In this thesis we first propose a method for solving the arithmetic expression equivalence problem using partial evaluation. In our method\, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Using this technique\, we present three novel control flow optimization techniques to improve performance and energy in software. \nIn the first technique\, we present a short-circuit code transformation method to optimize conditional blocks in high-level programs. Specifically\, the transformation takes advantage of the fact that the Boolean value of the conditional expression\, determining the true/false paths\, can be statically analyzed to determine cases when one or the other of the true/false paths are guaranteed to execute. In such cases\, code is generated to bypass the evaluation of the conditional expression. In instances when the bypass code is faster to evaluate than the conditional expression\, a net performance gain is obtained. \nIn the second technique\, we present a loop transformation method to optimize loops containing nested conditional blocks. Results from conditional expression evaluation combined with loop dependency information are used to partition the iteration space of the nested loop. As a result\, the loop nest is decomposed such as to eliminate the conditional test\, thus substantially reducing the execution time. Our technique completely eliminates the conditional from the loops (unlike previous techniques) thus further facilitating the application of traditional optimizations and improving the overall speedup. \nIn the third technique\, we present a method to lower the software energy consumption using the technique mentioned above for loop transformation. In essence\, each of the smaller loops can be executed at a lower voltage/frequency setting\, yielding overall energy reduction. \nApplying the proposed transformation techniques on kernels taken from different application domains\, we measured a substantial performance and energy improvement.
URL:https://www.cecs.uci.edu/event/algorithmic-code-optimization-using-conditional-expression-evaluation/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090709T150000
DTEND;TZID=America/Los_Angeles:20090709T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14319-1247151600-1247155200@www.cecs.uci.edu
SUMMARY:Transducer Synthesis for Heterogeneous Multi-processor Systems
DESCRIPTION:Transducer Synthesis for Heterogeneous Multi-processor Systems\nby Hansu Cho \nLocation: EH 2210 \nDate and Time: July 9\, 2009\, 8:30 AM \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nContemporary system design requires more computational power than ever. To overcome this problem\, MPSoC is widely used\, but design complexity have been increased rapidly. Meanwhile\, short time to market forced system designer to reduce development time. Therefore\, designer raised the level of abstraction into the higher level called transaction level. But\, current high level synthesis tools are dedicated to computational components only. To our best knowledge\, there is no synthesis tool for communication components from the transaction level model down to RTL model. In this dissertation\, we present a component called transducer which can handle heterogeneous MPSoC communication with multiple buses. Also\, we presents a tool for automatic synthesis of transducer. The tool captures the communication parameters in the platform at transaction level and generates transducer in RTL. The design and configuration of the transducer depend on several platform components including heterogeneity of the components\, traffic on the bus\, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the transducer can be automatically derived based on these parameters. \nThe advantage of this approach is that the user may modifies transducer parameters to suit specific optimization goals. In contrast to conventional approaches like IP wrappers\, our approach enables the user to generate an application specific interface between any number of buses for any platform configuration. Therefore\, the system designer is not bound to a set of IPs or protocols for their platform definition. Furthermore\, due to automatic generation\, we provide several orders of magnitude savings in interface development cost. We demonstrate the synthesizability and quality of our automatically generated transducers using Xilinx ISE tools and FPGA board. We use industrial strength design drivers such as an MP3 decoder and JPEG encoder to test our automatically generated transducers for a variety of platforms and compare them to manually designed transducers on different quality metrics. Our experimental results show that performance of automatically generated transducers are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 20X of improvement in development time.
URL:https://www.cecs.uci.edu/event/transducer-synthesis-for-heterogeneous-multi-processor-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090618T150000
DTEND;TZID=America/Los_Angeles:20090618T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14320-1245337200-1245340800@www.cecs.uci.edu
SUMMARY:Automatic Generation and Verification of Transaction Level Models
DESCRIPTION:Automatic Generation and Verification of Transaction Level Models\nby Lochi Yu \nLocation: ET 331 \nDate and Time: June 18\, 2009 10:00am \nCommittee:\nProfessor Daniel Gajski (Chair)\nProfessor Rainer Doemer\nProfessor Ian Harris \nAbstract:\nThe rising complexity in system designs over the past decades poses great challenges to current designers. One way to cope with this challenge has been to raise the level of abstraction of design\, reducing the number of elements and speeding up design decisions. Transaction Level Models (TLM) have emerged as a new alternative to design Multi-Processor System-on-Chips (MPSoC). TLMs express communication among modules at the transaction level\, without simulating the dozens of individual signals in communication elements such as busses. Nevertheless\, several drawbacks exist: TLMs are fast\, but their accuracy is low\, TLMs are being coded manually\, often by the use of a System Level Design Language (SLDL)\, there is no widely-adopted and tool-supported TLM style\, and there has been little work on verifi cation at the System Level. In this dissertation\, we aimed to contribute in different aspects: We defined a modeling style for SystemC TLMs whose modules have a one-to-one relationship with actual synthesized modules in a FPGA. Then\, we defined a data structure\, complete and flexible enough to describe a complete embedded system\, its hardware platform and application\, and developed generation algorithms that would use it to automatically produce an executable TLM in SystemC. Fourth\, we designed new transformation rules for models in Model Algebra (MA) that allows veri cation on pipelined models in MA. With our approach\, we can have automatic generation and verification of Transaction Level Models\, freeing the designer from error-prone manual coding\, and allows him to focus on higher level design decisions\, speeding up the overall design phase.
URL:https://www.cecs.uci.edu/event/automatic-generation-and-verification-of-transaction-level-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090603T150000
DTEND;TZID=America/Los_Angeles:20090603T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14321-1244041200-1244044800@www.cecs.uci.edu
SUMMARY:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors
DESCRIPTION:TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors\nby Ashok Halambi \nLocation: DBH 4013 \nDate and Time: June 3\, 2009 2:00pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Alex Nicolau\nProfessor Alex Viedenbaum \nAbstract:\nEmbedded systems continue to increase in functionality\, complexity and connectivity. Programmable platforms\, consisting of processors programmable in software\, are a popular solution to satisfy the design constraints (such as cost\, performance\, flexibility\, reliability etc.) of such systems. Key challenges in the design of programmable platforms include compiler-in-loop design space exploration (DSE)\, and automatic generation of software toolkit for hardware/software co-design. \nA language-based model of the processor-memory subsystem has several benefits: it serves as a golden reference model for all principals involved in the design; it can be used to drive DSE and automatic software toolkit generation; it can be used to perform top-down (formal) verification and validation; and\, it can be refined down to implementation (register-transfer level). In this dissertation\, we present EXPRESSION\, an architecture description language (ADL) that is designed for DSE of processor-memory sub-system and automatic generation of software toolkit including compiler and cycle-accurate simulator. EXPRESSION has been used to describe various processors from RISC (DLX\, MIPS R4000\, ARM 9)\, VLIW (TI C6x)\, DSP (ST100)\, etc. Our EXPRESSION based DSE methodology permits exploration of a wide range of processor architectures\, and includes compiler-in-loop for accurate analysis of each design configuration. \nTo aid compiler-in-loop DSE\, we developed EXPRESS\, a retargetable\, instruction level parallelizing compiler that accepts programs in “C” and produces assembly code for the target processor described in EXPRESSION. The EXPRESS compiler is capable of handling irregular architectures\, and can adapt to changes in the processor’s instruction-set or micro-architecture. EXPRESS also includes a framework for dynamic customization of the compiler based on the target application and architecture characteristics. These capabilities of EXPRESS make it ideal for use in the DSE of processor-memory subsystems. \nRetargetable compilers suffer from the drawback of poor output code quality as compared to a compiler that is “hand-crafted” for the target processor. Key differences between the two compilers include the presence of target specific optimizations and custom phase ordering of optimization passes in the target specific compiler. In this dissertation\, we propose a framework\, called TransMutations\, that enables dynamic\, run-time customization of a retargetable compiler. It allows for easy integration of optimizations (called mutations) into the compiler and solves the phase ordering problem by applying optimizations in a context-sensitive manner for each region of the application code. The TransMutations framework has been implemented in the EXPRESS compiler and we present results demonstrating the effectiveness of the technique. This framework improves the quality of code generated by retargetable compilers and enables them to be used in accurate compiler-in-loop DSE of programmable embedded systems.
URL:https://www.cecs.uci.edu/event/transmutations-a-framework-for-dynamic-customization-of-retargetable-compilers-for-embedded-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090529T150000
DTEND;TZID=America/Los_Angeles:20090529T160000
DTSTAMP:20231011T183716Z
CREATED:20231011T183716Z
LAST-MODIFIED:20231011T183716Z
UID:14322-1243609200-1243612800@www.cecs.uci.edu
SUMMARY:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement
DESCRIPTION:Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement\nby Aseem Gupta \nLocation: DBH 3011 \nDate and Time: May 29\, 2009 1:30pm \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Fadi Kurdahi\nProfessor Tony Givargis \nAbstract:\nProcess scaling and shrinking device geometries have resulted in chips with greater performance and complexity levels. However\, these advancements have come at the cost of higher power densities and increased operating temperatures. The inability to control the operating temperatures by existing cooling techniques is the principal reason for discontinuation of an increase in frequencies and introduction of multi-core architectures. Apart from operability\, high temperatures have unfavorable consequences such as: increased leakage power\, reduced interconnect life time\, slowing of interconnects and transistors\, need for expensive package and cooling mechanisms\, and increased manufacturing cost and design effort. Traditionally\, thermal issues have been examined only at the post-synthesis stages of the design flow. This thesis attempts to migrate the “thermal awareness” from the physical level design phase to early stages of the VLSI design flow and utilize it to target various design metrics such as power\, performance\, reliability\, and operability. This thesis advances the procedure of leakage power estimation by coupling it with thermal profile estimation and capturing the positive interdependence between temperature and leakage power. It also advances the traditional role of communication architecture to that of an active thermal manager. The proposed communication architecture based thermal manager delays the execution of chosen components by regulating the flow of data over the on-chip communication fabric. This dissertation demonstrates the need of examining the effects of frequency\, supply voltage\, power dissipation\, and temperature on SRAM reliability in a mutually interrelated manner. Our observation contradicts the conventional belief that increasing supply voltage always reduces the failure rate in SRAMs. Because of thermal effects\, an increase in the supply voltage can also lead to increase in the SRAM failure rate. This thesis also extends the procedure of system level floorplanning to manage the leakage power and reliability of the design. The fundamental contribution of this thesis is that it advances the traditional design flow in the direction of incorporating thermal awareness during various stages of the flow.
URL:https://www.cecs.uci.edu/event/temperature-aware-vlsi-design-for-reduced-power-and-reliability-enhancement/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090527T150000
DTEND;TZID=America/Los_Angeles:20090527T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14323-1243436400-1243440000@www.cecs.uci.edu
SUMMARY:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems
DESCRIPTION:Model-based Analysis of Event-driven Distributed Real-time Embedded Systems\nby Gabor Madl \nLocation: DBH 3011 \nDate and Time: May 27\, 2009 10:00am \nCommittee:\nChancellor’s Professor Nikil Dutt (Chair)\nProfessor Tony Givargis\nProfessor Ian Harris \nAbstract:\nAs embedded systems become increasingly networked\, and interact with the physical world\, Distributed Real-time Embedded (DRE) systems emerge. DRE systems range from small-scale Multi-processor Systems-on-Chip (MPSoCs) operating in resource constrained environments such as cell phone platforms\, medical devices and sensor networks all the way to large-scale software-intensive systems of systems used in avionics\, ship computing environments\, and in supervisory control and data acquisition systems managing regional power grids. \nThis dissertation focuses on the model-based analysis of event-driven DRE systems. Event-driven DRE systems are based on a reactive communication paradigm\, where the execution of tasks is triggered asynchronously\, invoked by external events\, interrupts\, or by other tasks. Events can also express time\, providing a common semantic domain for the compositional analysis of time- and event-driven DRE systems. \nThe key technical contributions of this dissertation are (1) the specification of a formal semantic domain for DRE systems\, (2) a model checking method for the real-time verification of non-preemptive DRE systems using timed automata\, (3) a performance estimation method for DRE systems by discrete event simulations\, (4) a conservative approximation method for the verification of preemptive event-driven asynchronous DRE systems by timed automata\, (5) a method for the functional verification and performance estimation of MPSoCs built on an industry standard interconnect\, and (6) a cross-abstraction real-time analysis method for MPSoC designs utilizing bus matrix interconnects. \nThe novelty of our approach lies in combining formal methods and symbolic simulations for the system-level evaluation of DRE designs early in the design flow\, and utilizing multiple abstractions to trade off analysis accuracy in scalability. \nWe implemented the proposed analysis methods in the open-source Distributed Real-time Embedded Analysis Method (DREAM) framework for the model-based real-time verification and performance estimation of DRE systems. DREAM focuses on the practical application of formal analysis methods to automate the verification\, development\, configuration\, and integration of event-driven DRE systems. DREAM is available for download at http://dre.sourceforge.net. We applied the proposed design flow to the domain of software-intensive mission-critical avionics DRE applications\, and the domain of multimedia MPSoCs.
URL:https://www.cecs.uci.edu/event/model-based-analysis-of-event-driven-distributed-real-time-embedded-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20090227T150000
DTEND;TZID=America/Los_Angeles:20090227T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14324-1235746800-1235750400@www.cecs.uci.edu
SUMMARY:Automatic Design and Optimization of Application Specific Processors
DESCRIPTION:Automatic Design and Optimization of Application Specific Processors\nby Jelena Trajkovic \nThe stringent performance and power requirements of modern applications have fueled the need for application specific computing platforms. Conventional general purpose embedded processor do not provide the necessary throughput for meeting the applications’ performance and power needs. On the other hand\, manual hardware design is too expensive and results in inflexible implementation. The short time to market demands also make hardware design prohibitive. Therefore\, there exists a need for automatic design methods and tools that provide a high performance\, programmable and energy-efficient implementation starting from standard application descriptions such as C reference code. High level synthesis and application specific processor tools are a step in this direction\, but suffer from scalability\, quality and controllability issues. In this dissertation\, we present techniques for automatic processor design from C code that are scalable to thousands of lines of C code\, are controllable at each step of the design process and provide quality of results comparable to manual design. \nOur contributions enable a system level design methodology for application specific processors that starts with a reference C code of the application. An initial processor data path is constructed from a database of available components such as function units\, register files and buses. The initial data path is based on the types of operations and available concurrency in the application. The data path is then iteratively refined until an efficient architecture is derived. The key optimization goal is to keep performance within given boundaries while maximizing resource utilization. We further optimize the processor design using a novel algorithm for automatic custom pipelining based on the C code. The pipelining optimization also targets both resource utilization and performance. Our experimental results with large applications such as DCT and MP3 decoder show that automatically generated architectures are comparable to manual designs\, but can be obtained in a matter of few seconds\, leading to significant productivity gains. \nOur final contribution to design methods for embedded systems deals with low power memory design. Typically\, DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high\, exceeding that of the data cache or even that of the processor. We present and evaluate a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small\, cache-like structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption\, 23%\, on average\, and reduction in the energy-delay product\, 44%\, on average. The approach also improves performance: the CPI is reduced by 26%\, on average.
URL:https://www.cecs.uci.edu/event/automatic-design-and-optimization-of-application-specific-processors/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080709T150000
DTEND;TZID=America/Los_Angeles:20080709T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14325-1215615600-1215619200@www.cecs.uci.edu
SUMMARY:Improving Packet Latencies of Live Streams in Wired Networks
DESCRIPTION:Improving Packet Latencies of Live Streams in Wired Networks\nby Arijit Ghosh (Advisor: Prof. Tony Givargis)\nDate: July 9\, 2008 \nLive streaming is becoming increasingly popular. In a study published in January 2008\, Cisco predicted that Internet-to-TV video will account for 30% of all Internet traffic. If all kinds of video traffic are considered\, then it will be 90% of consumer traffic by 2012. We distinguish live streams from on demand streams. Live streams are sent as the data is being generated\, is typically of long duration\, requires high bandwidth and associated with flash crowd behavior. As such\, live streams place tremendous demand on network resources. \nIn this thesis\, we proposed network techniques to improve packet latencies of live streams in wired networks. In particular\, we made the following contributions. First\, we proposed a technique that allows multicasting at the access network\, the proverbial last mile which presents tremendous bandwidth limitations. Second\, we reduced nodal processing by a tunelling scheme based on source routing. Essentially\, using routing computed at source and a novel network encoding scheme\, we eliminated intermediate processing. Third\, we presented a queueing algorithm that schedules packets based on application deadlines\, reduces the number of sorting iterations\, thereby improving performance\, has low complexity\, exhibits good fairness and provides a bounded delay for a single packet that is independent of the number of flows. Finally\, we proposed a variation of QoS routing that works with only partial network state information.
URL:https://www.cecs.uci.edu/event/improving-packet-latencies-of-live-streams-in-wired-networks/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20080708T150000
DTEND;TZID=America/Los_Angeles:20080708T160000
DTSTAMP:20231011T183918Z
CREATED:20231011T183918Z
LAST-MODIFIED:20231011T183918Z
UID:14326-1215529200-1215532800@www.cecs.uci.edu
SUMMARY:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems
DESCRIPTION:xTune: A Formal Methodology for Cross-layer Tuning of  Mobile Real-time Embedded Systems\nby Minyoung Kim (Advisor: Prof. Nikil Dutt)\nDate: July 8\, 2008 \nResource limited mobile real-time embedded systems can benefit greatly from  dynamic adaptation of system parameters. This thesis proposes a novel framework  xTune that employs iterative tuning using light-weight formal verification at runtime with feedback for dynamic adaptation. One objective of this approach is to enable tradeoff analysis across multiple layers (for example\, application\, middleware\, operating system) and predict the possible property violations as the system evolves dynamically over time. Specifically\, an executable formal specification is developed for each layer of the mobile real-time system under consideration. The formal specification is then analyzed using statistical model checking and statistical quantitative analysis\, to determine the impact of various resource management policies for achieving desired a variety of end-to-end properties in a quantifiable manner. The integration of formal analysis with dynamic behavior from system execution results in a feedback loop that enables model refinement and further optimization of policies and parameters. Finally\, we propose a composition method for coordinated interaction of optimizers at different layers. The core idea of our approach is that each participating optimizer can restrict its own parameters and exchange refined parameters with its associated layers. We demonstrate the applicability of the proposed methodology to the adaptive provisioning of mobile real-time embedded systems by treating a multimedia case study on resource-limited devices.
URL:https://www.cecs.uci.edu/event/xtune-a-formal-methodology-for-cross-layer-tuning-of-mobile-real-time-embedded-systems/
CATEGORIES:PhD Defenses
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