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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150515T150000
DTEND;TZID=America/Los_Angeles:20150515T160000
DTSTAMP:20231011T190511Z
CREATED:20231011T190511Z
LAST-MODIFIED:20231011T190511Z
UID:14432-1431702000-1431705600@www.cecs.uci.edu
SUMMARY:Temperature-Aware Design for SoCs using Thermal Gradient Analysis
DESCRIPTION:Name: Jun Yong Shin\nDate: May 18th\, 2015 \nTime: 2:00PM \nLocation: EH2430\, Harut colloquia room \nCommittee Chair: Nikil Dutt \nAbstract: \nOver the last few decades\, chip performance has increased steadily due to continuous and aggressive technology scaling. However\, it leaves chips quite vulnerable to several issues at the same time; high power densities in some particular areas spread across a chip might result in hotspots and thermal gradients\, and these can lead to permanent damage to the chip and also can reduce the reliability of the entire system using the chip. As a result\, a large number of dynamic thermal management solutions have been proposed in recent years for use in multi-core architectures\, and the accurate temperature information over the entire chip area has become indispensable especially for fine-grain dynamic thermal management solutions. Naturally\, on-chip thermal sensors came to play an important role in providing the accurate information on the temperature distribution of a chip\, but there still remain some issues regarding the allocation of on-chip thermal sensors; due to power\, area and routing issues\, it is preferable to limit the number of on-chip thermal sensors on a die\, and their placement needs to be considered carefully in order to increase the accuracy of full-chip thermal profile reconstruction especially when just a small number of sensors can be implemented; due to the limited reading accuracy of low-power\, small-sized on-chip thermal sensors\, it would be better to have some way to improve their reading accuracy. \nIn this work\, an issue will be firstly addressed regarding how to improve the reading accuracy of a low-power\, small-sized on-chip thermal sensor such as Ring-Oscillator (RO) based sensors at runtime on a software level. Secondly\, a question of how to allocate a proper number of sensors on a die in order to get the accurate full-chip scale thermal information on the run is addressed. Additionally\, a temperature-aware routing for global interconnects to minimize the delay and also to reduce the probability of chip failure due to electromigration is presented at the end.
URL:https://www.cecs.uci.edu/event/temperature-aware-design-for-socs-using-thermal-gradient-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150507T150000
DTEND;TZID=America/Los_Angeles:20150507T160000
DTSTAMP:20231011T190510Z
CREATED:20231011T190510Z
LAST-MODIFIED:20231011T190510Z
UID:14430-1431010800-1431014400@www.cecs.uci.edu
SUMMARY:Resilient On-Chip Memory Design in the Nano Era
DESCRIPTION:Final Defense – Abbas Banaiyanmofrad\n\nMay 20\, 2015\n3pm – 5pm\nDonald Bren Hall 3011 Conference Room \nCommittee:\nNikil Dutt (Chair)\, Alex Nicolau\, Alex Veidenbaum \nTitle:\nResilient On-Chip Memory Design in the Nano Era \nAbstract:\nAggressive technology scaling in the nano-scale regime makes chips more susceptible to failures. This causes multiple reliability challenges in the design of modern chips\, including manufacturing defects\, wear-out\, and parametric variations. By increasing the number\, amount\, and hierarchy of on-chip memory blocks in emerging computing systems\, the reliability of the memory sub-system becomes an increasingly challenging design issue. Existing resilient memory design schemes are unable to effectively address the key features of scalability\, interconnect-awareness\, and cost-effectiveness for these platforms. In this thesis\, we propose different approaches to address resilient on-chip memory design in computing systems ranging from traditional single-core processors to emerging many-core platforms. We classify our proposed approaches in five main categories: 1) Flexible and low-cost approaches to protect cache memories in single-core processors against permanent faults and transient errors\, 2) Scalable fault-tolerant approaches to protect last-level caches with non-uniform cache access in chip multiprocessors\, 3) Interconnect-aware cache protection schemes in network-on-chip architectures\, 4) Application-aware memory resiliency for approximate computing era\, and 5) System-level design space exploration\, analysis\, and optimization for redundancy-aware on-chip memory resiliency in many-core platforms. ​  \n In summary\, the premise of this thesis is to provide multiple solutions in different layers of system hierarchy targeting a verity of architectures from embedded single-core microprocessors to emerging large many-core platforms to address cost-efficient error-resiliency of on-chip memory components. \n 
URL:https://www.cecs.uci.edu/event/resilient-on-chip-memory-design-in-the-nano-era/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150416T150000
DTEND;TZID=America/Los_Angeles:20150416T160000
DTSTAMP:20231011T190322Z
CREATED:20231011T190322Z
LAST-MODIFIED:20231011T190322Z
UID:14397-1429196400-1429200000@www.cecs.uci.edu
SUMMARY:Self-stabilizing Java: Tool Support for Building Robust Software
DESCRIPTION:Name: Yong hun EomDate: April 15\, 2015\nTime: 10:00am\nLocation: EH 2430\nCommittee Chair: Professor Demsky\nCommittee members: Prof. Pai Chou and Prof. Rainer Doemer \nTitle: Self-stabilizing Java: Tool Support for Building Robust Software \nAbstract:\nDeveloping robust software systems remains an open research problem. The\ncurrent approaches for improving software reliability mainly focus on\nminimizing the number of software bugs through formal verification or\nextensive testing. Despite such efforts\, it is common that unexpected\nsoftware bugs corrupt a program’s state and cause systems to fail. \nThe motivation for this research is to embrace the fact that it is\ndifficult to guarantee that software is error-free. We present\nSelf-stabilizing Java (SJava) that instead checks that a program\nself-stabilizes. Self-stabilizing programs automatically recover to the\ncorrect state from the corrupted state caused by software bugs and other\nsources. A number of applications are inherently self-stabilizing—such\nprograms typically overwrite all non-constant data with new input data. \nWe have developed a type system and static analyses that together check\nwhether program executions eventually transition from incorrect states\nto the correct state. We combine this with a code-generation strategy\nthat ensures that a program continues executing long enough to\nself-stabilize. Furthermore\, in order to lower the burden of type\nannotations\, we present an annotation inference algorithm that\nautomatically derives an initial set of annotations. \nOur experience using SJava indicates that our system successfully\nchecked that several benchmarks were self-stabilizing and effectively\ninferred annotations for our benchmarks.
URL:https://www.cecs.uci.edu/event/self-stabilizing-java-tool-support-for-building-robust-software/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20150202T150000
DTEND;TZID=America/Los_Angeles:20150202T160000
DTSTAMP:20231011T190459Z
CREATED:20231011T190456Z
LAST-MODIFIED:20231011T190459Z
UID:14421-1422889200-1422892800@www.cecs.uci.edu
SUMMARY:Formal Analysis of Electronic System Level Models using Satisfiability Modulo Theories and Automata Checking
DESCRIPTION:Name:  Che-Wei Chang\nDate/Time:  Wednesday\, January 28\,2015\, 9:00am \nLocation:  EH 3404 \nCommittee Chair: Rainer Doemer \nCommittee Member: Daniel Gajski \nCommittee Member: Pai Chou \nAbstract:  \nFor a system-level design which may be composed of multiple processing elements running\n        in parallel\, various kinds of unwanted consequences may happen if the system\n        is constructed carelessly. For example\, deadlock may happen if improper execution\n        order and communication between processing elements is used in the system. Another\n        problem which may be caused by the concurrent execution is race condition\, as\n        shared variables in the system-level model could be accessed by multiple concurrent\n        threads in parallel. Those unwanted behaviors definitely have negative influence on\n        the functionality of the system. Furthermore\, the functionality is not the only concern\n        in system design as timing constraints are critical as well. If the system cannot\n        finish the job within timing constraints\, it is still considered an unwanted design. To\n        address this issue\, we propose two formal analysis approaches in this dissertation to\n        analyze three types of properties we discussed above\, which are\n        1). liveness\,\n        2). satisfiability of timing constraint\, and\n        3). May-Happen-in-Parallel access.\n        These two approaches are based on Satisfiability Modulo Theories (SMT) and UPPAAL\n        automaton model respectively. We run these two approaches on our in-house\n        system models\, including a JPEG encoder\, MP3 decoder\, AMBA AHB and CAN\n        bus protocol models. The experimental results show our approaches are capable of\n        analyzing those properties meeting our expectation within reasonable analysis time.
URL:https://www.cecs.uci.edu/event/formal-analysis-of-electronic-system-level-models-using-satisfiability-modulo-theories-and-automata-checking/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140923T150000
DTEND;TZID=America/Los_Angeles:20140923T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14418-1411484400-1411488000@www.cecs.uci.edu
SUMMARY:Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture
DESCRIPTION:Title:� Design\, Analysis and Implementation of An Area-Efficient Beam-Steerable Sub-Terahertz Imaging Receiver Array Architecture\nSpeaker:� Francis Caster II \nLocation/Time:� September 23\, 2014\, 3PM\nCommittee Members:\nPayam Heydari\nFilippo Capolino\nH. Kumar Wickramasinghe\nAbstract: Multi-pixel passive imaging arrays are presently fabricated in expensive processes with low integration levels. Imaging arrays designed in inexpensive processes with higher levels of integration would result in cheaper larger arrays. The objective of this work is twofold: 1) to develop a highly integrated silicon-based passive imaging receiver integrating the entire receiver frontend from antenna to detector; and 2) to develop a highly scalable architecture for use in focal plane arrays of arbitrary dimensions\, incorporating new features to address large-array issues while retaining the pixel density of conventional focal plane arrays. A new area-efficient beam-steerable imaging array receiver architecture suitable to integrated circuit realization up to sub-THz frequencies is presented. A direct-detection-based receiver array utilizing the proposed architecture is designed and implemented in an advanced 0.18�m BiCMOS process. The receiver chip achieves a peak measured coherent responsivity of 1\,150MV/W\, a measured incoherent responsivity of 1\,000MV/W\, a minimum NEP of 0.28fW/sqrtHz and a front-end 3-dB bandwidth from 87-108GHz\, while consuming 225mW per receiver element. The measured NETD of the SiGe receiver chip is 0.45K with a 20ms integration time. The proposed architecture uses a new concept of spatial-overlapping super-pixels which results in (1) improved SNR at the pixel level through a reduction of spillover losses\, (2) partially correlated adjacent super-pixels\, (3) a 2�2 window averaging function in the RF domain\, (4) the ability to compensate for the systematic time delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point\, and (5) the ability to compensate for mutual coupling effects among the array elements.
URL:https://www.cecs.uci.edu/event/design-analysis-and-implementation-of-an-area-efficient-beam-steerable-sub-terahertz-imaging-receiver-array-architecture/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140910T150000
DTEND;TZID=America/Los_Angeles:20140910T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14417-1410361200-1410364800@www.cecs.uci.edu
SUMMARY:Self-interference Cancellation in Full-duplex Wireless Systems
DESCRIPTION:Title:  Self-Interference Cancellation in Full-duplex Wireless Systems \nSpeaker:  Elsayed Ahmed \nDate/Time:  August 28\, 2014\, 10:00AM \nLocation:  Engineering Hall 4106 \nCommittee Members:Ahmed Eltawil (Chair)Ender AyanogluA. Lee Wsindlehurst \nAbstract: Due to the tremendous increase in wireless data traffic\, one of the major challenges for future wireless systems is the utilization of the available spectrum to achieve better data rates over limited spectrum. Currently\, systems operate in what is termed “Half Duplex Mode\,” where they are either transmitting or receiving\, but never both using the same temporal and spectral resources. Full-duplex transmission promises to double the spectral efficiency where bidirectional communications is carried out over the same temporal and spectral resources. The main limitation impacting full-duplex transmission is managing the strong self-interference signal imposed by the transmit antenna on the receive antenna within the same transceiver. Several recent publications have demonstrated that the key challenge in practical full-duplex systems is un-cancelled self-interference power caused by a combination of hardware imperfections\, especially Radio Frequency (RF) circuits’ impairments. In this thesis\, we consider the problem of self-interference cancellation in full-duplex systems. The ultimate goal of this work is to design and build a complete\, real-time\, full-duplex system that is capable of achieving wireless full-duplex transmission using practical hardware platforms. Since RF circuits’ impairments are shown to have significant impact on the self-interference cancellation performance\, first\, we present a thorough analysis of the effect of RF impairments on the cancellation performance\, with the aim of identifying the main performance limiting factors and bottlenecks. Second\, the thesis proposes several impairments mitigation techniques to improve the overall self-interference cancellation capability by mitigating most of the transceiver RF impairments. In addition to impairments mitigation\, two novel full-duplex transceiver architectures that achieve significant self-interference cancellation performance are proposed. The performance of the proposed techniques is analytically and experimentally investigated in practical wireless environments. Finally\, the proposed self-interference cancellation techniques are used to build a complete full-duplex system with a 90% experimentally proven full-duplex rate improvement compared to half-duplex systems.
URL:https://www.cecs.uci.edu/event/self-interference-cancellation-in-full-duplex-wireless-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140910T150000
DTEND;TZID=America/Los_Angeles:20140910T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14416-1410361200-1410364800@www.cecs.uci.edu
SUMMARY:Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor Platforms
DESCRIPTION:Title:  Computation Model Based Automatic Design Space Exploration for Heterogeneous Multiprocessor  Platforms \nSpeaker:  Kyoungwon Kim \nDate/Time:  August 28\, 2014\, 2:oopm \nLocation:  Engineering Hall 3206 \nCommittee Members:Daniel Gajski (Chair)Tony Givargis Rainer Doemer \nAbstract:  Embedded system designers continuously face a twofold challenge handling the ever-increasing complexity of design and meeting the ever-shrinking time-to-market timeline. To meet such a challenge\, the system design paradigm has shifted to platform-based design characterized by intensive use of software and aggressive reuse of verified components. More and more designs are turning to heterogeneous platforms to meet design constraints in multiple criteria. However the use of such and heterogeneity generates more challenges for platform-based design. To address the challenges\, system designers must utilize system-level methodologies for specification and design. Here the designers begin the design process by coming up with a computation model that captures the behavior of the system. The computation model is successively refined down to the structural model in the system level. In each refinement\, the designers explore the design space. The design space comprises a set of alternatives concerning hardware/software partitioning\, platform selection\, and mapping. The design space is huge\, however\, necessitating the automation of its exploration. The platform is very often fixed regarding either availability or legacy reasons\, making mapping crucial. This dissertation focuses on the automatic mapping of the computation model for the given heterogeneous platform. This dissertation presents a new automatic mapping technique based on the input computation model. The proposed technique consists of two separate phases: initial mapping and improvement driven by cycle-approximate estimation. Existing mapping techniques depend on early estimation so a dilemma arises from the fact that cycle-approximate estimation cannot precede mapping. The dilemma can be gotten around by our performing initial mapping based on rough estimation and then making iterative improvements based on cycle-approximate estimation. While earlier work has been domain specific\, the mapping techniques in the proposed work are driven by a general computation model that includes hierarchy\, state transitions\, dynamic data-oriented behaviour\, and imperative languages\, while previous work is domain specific.The proposed work also addresses mapping with an awareness of general hierarchy in pipelined applications. The size of the design space explored is limited by the speed of cycle-approximate estimation. Orders of magnitude faster than Simulation-based cycle-approximate estimation\, the new trace-driven estimation presented in this disseration is cycle-approximate and applicable to both software and hardware. The new trace-driven estimation assumes that the execution path of each task depends on data only. As the trace-driven estimation handles a portion of applications\, it complements the existing simulation-based cycle-approximate estimation. We have applied the proposed mapping techniques to multiple multimedia applications and the techniques outperformed in terms of execution time the competitors by proportions ranging from 23.3% through 36.3%.
URL:https://www.cecs.uci.edu/event/computation-model-based-automatic-design-space-exploration-for-heterogeneous-multiprocessor-platforms/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140723T150000
DTEND;TZID=America/Los_Angeles:20140723T160000
DTSTAMP:20231011T190437Z
CREATED:20231011T190437Z
LAST-MODIFIED:20231011T190437Z
UID:14414-1406127600-1406131200@www.cecs.uci.edu
SUMMARY:New Circuit Techniques Enabling Millimeter-Wave and Terahertz Transceivers in Nonoscale Silicon
DESCRIPTION:Title:  New Circuit Techniques Enabling Millimeter-Wave and Terahertz Transceivers in Nonoscale Silicon \nSpeaker:  Zheng Wang \nDate/Time:  Monday\, June 2\, 2014\, 2:00PM \nLocation:  Engineering Hall 2111 \nCommittee Members:Payam Heydari (Chair)Michael GreenEnder Ayaloglu \nAbstract: The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device _fT_/_fmax_\, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. This dissertation mainly focuses on the design of a 210GHz fundamental transceiver and also covers the design of a W-band fully integrated imaging system utilizing a novel concept of spatial-overlapping super pixels.Firstly\, a 210GHz transceiver with OOK modulation in a 32nm SOI CMOS process is presented. The transmitter (TX) employs a 2´2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillator (VCO) at 210GHz with an on-off-keying (OOK) modulator\, a power amplifier (PA) driver\, a novel balun-based differential power distribution network\, four PAs and an on-chip 2´2 dipole antenna array. The non-coherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna\, a low noise amplifier (LNA)\, and a power detector. The VCO generates measured -13.5dBm output power; and the PA shows a measured 15dB gain and 4.6dBm Psat. The LNA exhibits a measured in-band gain of 18dB and minimum in-band noise figure (NF) of 11dB. The TX achieves an EIRP of 5.13dBm at 10dB back-off from saturated power. It achieves an estimated EIRP of 15.2dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200GHz frequency range. \nSecondly\, a W-band direct-detection-based receiver array in an advanced 0.18µm BiCMOS process is presented\, which incorporates a new concept of spatial-overlapping super-pixels for millimeter-wave imaging\napplications. The use of spatial-overlapping super-pixels results in (1) improved SNR at the pixel level through a reduction of spillover losses\, (2) partially correlated adjacent super-pixels\, (3) a 2×2 window\naveraging function in the RF domain\, (4) the ability to compensate for the systematic phase delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point\, and (5)\nthe ability to compensate for mutual coupling effects among the array elements. The receiver chip achieves a measured peak coherent responsivity of 1\,150MV/W\, an incoherent responsivity of 1\,000MV/W\, a\nminimum noise-equivalent power (NEP) of 0.28fW/√Hz and a front-end 3-dB bandwidth from 87-108GHz\, while consuming 225mW per receiver element. The measured noise-equivalent temperature difference (NETD) of the SiGe\nreceiver chip is 0.45K with a 20ms integration time.\n\n 
URL:https://www.cecs.uci.edu/event/new-circuit-techniques-enabling-millimeter-wave-and-terahertz-transceivers-in-nonoscale-silicon/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140723T150000
DTEND;TZID=America/Los_Angeles:20140723T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14413-1406127600-1406131200@www.cecs.uci.edu
SUMMARY:Performance-Optimized Terahertz Signal Sources in Silicon
DESCRIPTION:Title:  Performance-Optimized Terahertz Signal Sources in Silicon \nSpeaker:  Pei-Yuan Chiang \nDate/Time:  Monday\, June 2\, 2014\, 10:00AM \nLocation: Engineering Hall 2111 \nCommittee Members:Payam Heydari (Chair)Michael GreenOzdal Boyraz \nAbstract: Terahertz (THz) and sub-millimeter wave band are known to provide unique applications in spectroscopy\, imaging and high-data-rate wireless communication. An imaging system operating in this frequency region exhibits non-invasive and high-resolution characteristics due to the non-ionized and short-wavelength radiation waves\, which makes it attracting for security surveillance. On the other hand\, the THz wireless transceiver operating in the license-free spectrum is capable of achieving tens of gigabits-per-second by utilizing a simple modulation scheme. All the benefits mentioned above make THz a promising research topic. Towards realization of a high-performance THz system\, one of the most challenging steps is to design a frequency synthesizer. \nA voltage-controlled oscillator (VCO) is one of the important building blocks within a synthesizer. Due to the server performance degradation of varactors and transistors at high frequencies\, new ways of designing VCOs need to be investigated. Here\, two different ideas are proposed. First\, an inductive-tuning mechanism with high quality-factor and wide tuning-range is introduced. This tuning technique is based on a variable inductor seen at the emitter terminal of a base-degenerated transistor. By adding a series RL at the base terminal\, the variable inductor\, exhibiting low loss and high tunability\, improves the VCO output power and phase noise while achieving a wide tuning range. The second idea\, double-stacked cross-coupled VCO\, is to design a strong negative resistance cell to compensate for the server loss of the varactor at THz frequencies. By implementing a source-degenerated negative resistor of a conventional cross-coupled pair\, the overall negative resistance is enhanced. It also reduces the parasitic capacitance\, making it an attracting approach for THz applications. \nFinally\, a novel THz frequency synthesizer is proposed. A 300GHz phase-locked-based synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a three-phase injection locked divider is introduced. The CAV is used to tune the oscillation frequency\, enhance output power\, and buffer the VCO’s fundamental signal. The divider’s locking-range is vastly increased attribute to the three-phase injection. This work demonstrates the highest-frequency synthesizer in silicon.
URL:https://www.cecs.uci.edu/event/performance-optimized-terahertz-signal-sources-in-silicon/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20140712T150000
DTEND;TZID=America/Los_Angeles:20140712T160000
DTSTAMP:20231011T190438Z
CREATED:20231011T190438Z
LAST-MODIFIED:20231011T190438Z
UID:14415-1405177200-1405180800@www.cecs.uci.edu
SUMMARY:New Perspectives on Designing An Effective Management Policy for Multi-level Cache Hierarchy
DESCRIPTION:Date/Time:  February 25\, 2014\, 3:00PM \nLocation:  DBH 3011 \nCommittee Members:Alexander V. Veidenbaum (Chair)Alexandru NicolauTony GivargisRainer Doemer \nAbstract: Designing an effective cache management policy for a multi-level cache hierarchy has been a hot research topic to bridge the gap between the fast microprocessor and the long memory latency. It is becoming critically important in modern microprocessors due to the emerge of new hardware architectures\, new technologies and new applications. However\, it has been shown that this is not an easy task due to the complexity of the inputs that computer architects must take into account. \nThe bottom-up approach has been used in designing such a policy. Rather than tackling the problem with all the possible inputs\, a management policy is broken down into smaller problems\, each targeting a smaller number of inputs. Sub-policies\, such as replacement\, bypass\, migration and partitioning\, are studied for a specific event or configuration. Solutions have been proposed for these individual policies or their combinations. In either case\, the new policies must be shown to work well with existing baseline policies. \nIn this dissertation\, using the bottom-up approach\, we propose new management policies for a multi-level cache hierarchy. Using new ideas about an effective policy or improving existing methods for new hardware architectures\, we further optimize the current state-of-the-art policies. Specifically\, we propose three new sets of management policies. First\, new migration policies are proposed for an L0/L1 cache hierarchy for embedded processors. We propose two new cache designs to enhance operations of the L1 caches. Second\, we propose a new combined replacement\, bypass and partitioning policy for a last-level cache by achieving the balance between cache reuse and pollution. The new policy is shown to reduce pollution due to keeping cache lines too long in the cache\, a problem which was not addressed by prior work. And third\, we propose a new coordinated bypass policy for a multi-level cache hierarchy using the new classifications of cache lines and their reuse probabilities. This policy works well with any existing policies and architectures which allow bypass. \nThe new cache management policies are shown to improve existing policies or optimize the design with an acceptable performance loss. They are shown to work well with the baseline policies. We also present hardware architectures and application classes that each new policy will be applied to. Hardware design is also described and is shown to be feasible and have low overhead.
URL:https://www.cecs.uci.edu/event/new-perspectives-on-designing-an-effective-management-policy-for-multi-level-cache-hierarchy/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130827T150000
DTEND;TZID=America/Los_Angeles:20130827T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14412-1377615600-1377619200@www.cecs.uci.edu
SUMMARY:Cognitive Power Management and Error Resilient Algorithms for Memory Dominated Wireless Communication Systems
DESCRIPTION:Date/Time:  Friday\, August 23\, 2013 \nLocation:  Engineering Hall 4106 \nCommittee Members:Ahmed Eltawil (Chair)Fadi KurdahiA. Lee Swindlehurst \nAbstract: \nAdvanced CMOS technology exhibits increasing variations in performance\, power consumption and reliability parameters. These variations led to extensive overdesigning and increased power consumption to guarantee 100% reliable operation. However\, with the continuous shrinking of device parameters\, future semiconductor industry needs to shift from the assumption of 100% reliable computation to a fault-tolerant approach. Fortunately\, many important application domains such as communication and multimedia are inherently error-aware\, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. Specifically\, embedded memories in communication systems are perfect candidates for exploring error-aware designs\, since the share of the System-on-Chips (SoCs) that is dedicated to memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoCs for wireless standards such as Long-Term Evolution (LTE)\, Digital Video Broadcasting (DVB)\,  and Worldwide Interoperability for Microwave Access (WiMAX). Furthermore\, a large portion of the memory is typically used for buffering data that already has a high level of redundancy (e.g. buffering memories in wireless chips). In the context of wireless communication systems\, given that the incoming buffered data is already corrupted by time varying noise and interference\, there is no need to store the data samples in memories that are error free\, 100% of the time. Rather\, Voltage over-scaling (VoS) techniques can be adopted as an efficient means to achieve energy efficient systems via trading off reliability versus power.  However\, reducing the supply voltage of buffering memory through VoS results in spatially uniform random errors which in turn corrupt the stored data in the buffering memories and increase the noise floor. \nIn this thesis\, the predominance of embedded memories in current and emerging wireless transceivers is utilized as a means to save power via channel state aware voltage scaling. While the wireless channel is a stochastic channel where the designer has little control on its variables\, embedded memories are considered as an extension of the channel where the designer can control its quality via VoS. The thesis presents a unified statistical model that captures both errors in embedded memories due to voltage over-scaling and wireless channel impairments into a single Gaussian distribution model that represents a combination of communication channel noise and hardware noise. The proposed model is used to investigate different cognitive power management policies that capture the performance of the system as a function of both channel and hardware dynamics\, thus creating a much richer design space of power\, performance and reliability. Furthermore\, based on that model\, error-resilient algorithm for Viterbi decoder\, multiple input multiple output (MIMO) detector and memory-based computation are presented.
URL:https://www.cecs.uci.edu/event/cognitive-power-management-and-error-resilient-algorithms-for-memory-dominated-wireless-communication-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130726T150000
DTEND;TZID=America/Los_Angeles:20130726T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14411-1374850800-1374854400@www.cecs.uci.edu
SUMMARY:System Level Approaches for Low Power Wireless Architectures
DESCRIPTION:Date/Time:  Thursday\, August 1\, 2013 \nLocation:  Engineering Hall 4106 \nCommittee Members:Professor Ahmed Eltawil (Chair)Professor Fadi KurdahiProfessor Nikil Dutt \nAbstractThere are emerging needs to build energy efficient platforms to support co-operation between heterogeneous wireless networks. This necessitates building efficient frameworks for reconfigurable platforms that can support seamless reconfiguration among different wireless scenarios. Towards achieving that goal\, this thesis addresses the problem of building energy efficient wireless architectures from two perspectives. First\, we develop a high level framework that generates a reconfigurable MPSoC architecture from a library of heterogeneous processing resources that can be reconfigured to support various modes of operation. The framework proposes joint task and core mapping with system level floorplanning. With the objective of minimizing energy\, we develop an analytical probabilistic model that considers static\, dynamic\, reconfiguration and communication energy components for multiple applications characterized by certain probabilities of execution. Fast and efficient heuristics have been developed that can achieve solutions very close to those obtained via optimal solvers\, with several orders of magnitude speedup. \nWhile\, the first perspective focused on system level solutions\, the second perspective focuses on the block level optimizations. It utilizes the fact that the use of embedded memory in its various forms and implementations for cellular base-stations and mobile handhelds has experienced unprecedented growth recently\, significantly affecting area and power consumption metrics. Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories\, which allows acceptable hardware errors to flow through the processing chain as a cost of considerable power savings. This thesis presents a model that captures the statistics of both channel noise and buffering memory failures. Furthermore\, it introduces modified forward error correction (FEC) decoders that are aware of both the channel errors as well as the buffering memory errors. The decoding maximizes the likelihood of the received data based on the statics of the combined channel and buffering memory noise. The idea is applicable to three widely used FEC decoders; namely Viterbi\, Turbo\, and LDPC decoders. The modified decoders are able to preserve the system performance very close to the hardware error-free case with negligible area overhead in implementation.
URL:https://www.cecs.uci.edu/event/system-level-approaches-for-low-power-wireless-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190419Z
CREATED:20231011T190419Z
LAST-MODIFIED:20231011T190419Z
UID:14409-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Exploiting Master-Slave Bus Architecture and Storage Devices to Enable High-Performance\, Low-Power Logging for Sensor Systems
DESCRIPTION:By Eunbae YoonJune 24\, 2013 \nread more
URL:https://www.cecs.uci.edu/event/exploiting-master-slave-bus-architecture-and-storage-devices-to-enable-high-performance-low-power-logging-for-sensor-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190402Z
CREATED:20231011T190402Z
LAST-MODIFIED:20231011T190402Z
UID:14408-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Optimizing Program Performance via Similarity\, Using Feature-aware and Feature-agnostic Characterization Approaches
DESCRIPTION:By Rosario CammarotaMay 31\, 2013 \nread more
URL:https://www.cecs.uci.edu/event/optimizing-program-performance-via-similarity-using-feature-aware-and-feature-agnostic-characterization-approaches/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130619T150000
DTEND;TZID=America/Los_Angeles:20130619T160000
DTSTAMP:20231011T190344Z
CREATED:20231011T190344Z
LAST-MODIFIED:20231011T190344Z
UID:14402-1371654000-1371657600@www.cecs.uci.edu
SUMMARY:Out-of-order Parallel Discrete Event Simulation for Electronic System-Level Design
DESCRIPTION:Date/Time: Thursday\, June 6th\, 10:00 a.m. – 11:00 a.m.Location: CECS Conference Room\, Engineering Hall 3206 \nCommittee Members:Rainer Dömer (Chair)Daniel GajskiBrian Demsky \nAbstractThe large size and complexity of the modern embedded systems poses great challenges to design and validation. At the so called electronic system level (ESL)\, designers start with a specification model of the system and follow a systematic top-down design approach to refine the model to different abstraction levels by adding step-by-step implementation details. ESL models are usually written in C-based System-level Description Languages (SLDLs)\, and contain the essential features such as clear structure and hierarchy\, separate computation and communication\, and explicit parallelism. The validation of ESL models typically relies on simulation. Fast yet accurate simulation is highly desirable for efficient and effective system design. \nThe out-of-order parallel discrete event simulation (OoO PDES) is a novel approach for efficient validation of system-level designs by exploiting the parallel capabilities of todays multi-core PCs for system level description languages. OoO PDES breaks the global simulation-cycle barrier of traditional DE simulation by localizing the simulation time into each thread\, carefully delivering notified events\, and handling a dynamic management of simulation sets. Potential conflicts caused by parallel accesses to shared variables and out-of-order thread scheduling are prevented by an advanced predictive static model analyzer in the compiler. As such\, OoO PDES allows the simulator to effectively exploit the parallel processing capability of the multicore system to achieve fast speed simulation without loss of simulation and timing accuracy. \nWe perform simulation experiments on both highly parallel benchmark examples and real- world embedded applications including a JPEG image encoder\, an edge detector\, a MP3 audio decoder\, a H.264 video decoder\, and a H.264 video encoder. Experimental results show that our approach can achieve significant simulation speedup on multicore simulation hosts with negligible compilation cost. \nBased on our parallel simulation infrastructure\, we then propose a tool flow for dynamic race condition detection to increase the observability for parallel ESL model development. It helps the designer to quickly narrow down the debugging targets in faulty ESL models with par- allelism. This approach helps to reveals a number of risky race conditions in our in- house embedded multi-media application models and enabled us to safely eliminate these hazards. Our experimental results also show very little overhead for race condition diagnosis during compilation and simulation. \nOverall\, our work provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development. It helps the embedded system designers to build better products in shorter time-to-market.
URL:https://www.cecs.uci.edu/event/out-of-order-parallel-discrete-event-simulation-for-electronic-system-level-design/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130524T150000
DTEND;TZID=America/Los_Angeles:20130524T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14401-1369407600-1369411200@www.cecs.uci.edu
SUMMARY:Designer-in-the-Loop Recoding for Creating Safe and Parallel ESL Models
DESCRIPTION:Date/Time: Thursday\, May 30\, 2013\, 10:00 a.m. – 11:00 a.m.Location: CECS Conference Room\, Engineering Hall 3206 \nCommittee Members:Rainer Dömer (Chair)Daniel GajskiFadi Kurdahi \nAbstractThe design complexity of embedded systems increases as more processors and subsystems integrated on one chip. In order to overcome the design bottlenecks and shorten time to market\, system engineers are motivated to design from a higher abstraction level\, namely Electronic System Level (ESL). ESL design methodology has emerged to address the design complexity by supporting HW/SW co-specification and co-simulation\, system design space exploration and high-level synthesis. \nESL design relies on an input ESL model\, namely the specification model. Creating structured and parallel specification models efficiently is a prerequisite for building cost-effective embedded systems in ESL design. Practically\, application reference code is reused to create the ESL models. However\, the referee models lack the necessary characteristics\, such as explicit parallelism\, structural hierarchy and synthesizability\, for ESL design. It is a time-consuming and error-prone process to manuallyrecode the reference models into desired ESL models. \nThis dissertation addresses on the automation gap of recoding. We follow the design-in-the-loop recoding methodology which efficiently combines the automation tools with designer’s knowledge. Our approach aim to expose parallelism in the ESL model and guarantee that the parallel model is safe from race conditions. \nFirst\, we identifies the essential steps in recoding and defines a recoding design flow to create safe and parallel ESL models.Second\, we contribute three automated recoding operations: variable dependency analysis to provide prompt analysis during model development\, race condition analysis to assist verifying and debugging the parallelism and a high-level transformation function to instantly create loop-level parallelism. Third\, we develop a recoding development platform based on Eclipse tointegrate recoding tools and facilitate the designer-in-the-loop approach. \nThe effectiveness of the recoding functions is shown with experiments on a set of embedded applications. Also\, an classroom experiment with 68 graduate students shows our recoding approach using the Eclipse-based recoding platform increases the productivity and reduces errors in parallel ESL model development.
URL:https://www.cecs.uci.edu/event/designer-in-the-loop-recoding-for-creating-safe-and-parallel-esl-models/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130520T150000
DTEND;TZID=America/Los_Angeles:20130520T160000
DTSTAMP:20231011T190420Z
CREATED:20231011T190420Z
LAST-MODIFIED:20231011T190420Z
UID:14410-1369062000-1369065600@www.cecs.uci.edu
SUMMARY:Context-based Service Performance Profile Management System in SOA
DESCRIPTION:Date/Time:  Tuesday\, May 28th\, 2:00 p.m. – 3:00 p.m. \nLocation:  Engineering Hall 4106 \nCommittee Chair:Kwei-Jay Lin \nAbstractService-Oriented Architecture (SOA) is a software paradigm for providing a uniform means to discover\, interact with and use capabilities to produce desired effects consistent withmeasurable preconditions and expectation. SOA also provides a framework for service com-position by putting together of a number of services to make a more complex one to fulfill a business process and service reconfiguration by replacing faulty services with better perform-ing services to have seamless business process execution. In general\, service integration tries to maximize the performance of a business process such as to have a minimum latency\, the shortest response time\, the optimal reliability\, an acceptable level of security and so on. Al-though technology exists to optimize the performance in terms of the above QoS attributes\, it still may not meet the need of all users\, since user may have unique service requirement at some specific context. \nIn order to address this issue\, in this dissertation\, we present an approach to improve over-all performance for the execution of business process by considering context-based serviceperformance profile management through Context Manager. Context Manager is designed to collect service performance feedback from users along with their context data\, maintainservice performance profile data\, distinguish influential context for service performance\, pre-dict how the service would perform under user context and provide most-adaptive service for user context.Our experiment results indicate that context manager system effectively maintains service performance profile data\, clearly understands the influence of some specific context attributes on service performance and provides context-adaptive services as users expect. Moreover\, integrating context-awareness into SOA brings significant performance improvement in terms of lower rate of service failure and reconfiguration\, and more optimal response time between service requester and service provider.
URL:https://www.cecs.uci.edu/event/context-based-service-performance-profile-management-system-in-soa/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130513T150000
DTEND;TZID=America/Los_Angeles:20130513T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14400-1368457200-1368460800@www.cecs.uci.edu
SUMMARY:Embedded Computer Vision Systems for Image Based Motion and Speckle Image Analysis
DESCRIPTION:Date/Time:  Friday\, May 10\, 2013\, 2:00 p.m. – 3: 00p.m.Location:  4011 Donald Bren Hall \nCommittee Members:\nPai H. Chou (Chair)\nBernard Choi\nGlenn Healey\n \nAbstract:  Motion is common in taking images using conventional cameras. If there is motion either on camera or the object or on the both sides during the exposure time\, the image is blurred\, which is called motion blurred image. Motion blurred image is an interesting research subject in several areas including computer vision\, biomedical engineering. In general\, motion is undesirable to acquire clear image. Modern cameras are equipped with the mechanical structure to compensate motion artifact. However\, mechanical structure has limit in compensating huge motion. To compensate huge motion\, computer vision algorithm called motion deblurring is developed. Basically\, it estimates the best latent image from the blurry image using several assumptions (or priors) on the latent image and camera motion. The information included in the motion blur can be useful for biomedical applications. Laser speckle imaging is one good example. When laser light of certain frequency (visible laser is widely used) is illuminated on the skin\, the scattered laser light from the surface has random distribution if there is no motion. With motion\, the speckle pattern is interfered by the motion and no longer random for the region with motion. Since the laser light can penetrate into skin\, it is possible to measure blood perfusion near skin without invasion. Both motion deblurring and laser speckle imaging require huge computation time. That is the reason why they are developed on personal computers or workstations. However\, the physical size\, power consumption\, and cost make them harder to penetrate into wider-range of applications (e.g. A super-fast motion deblurring algorithm that can run on embedded platforms like portable digital cameras or smart phones or portable laser speckle imaging system for an emergency vehicle). Nowadays\, embedded processors become more and more powerful. The CPU clock frequency of those processors have already passed 1Ghz. Some of them use multiple number of cores for processing like x86 processors. However\, even with such high performance processors\, special design considerations are required. In this dissertation\, we suggest embedded hardware and software systems for motion deblurring and laser speckle imaging applications. In the first part of the dissertation\, we will discuss about our motion deblurring systems. We developed an extremely light-weight motion deblurring algorithm to make it fast enough to be suitable for embedded computing platforms. The developed algorithm is up to 100 times faster than the most recent deblurring algorithms. We also developed a hardware/software system for extremely accurate motion deblurring. The hardware system is composed of IMU\, a control board\, and the Microsoft Kinect. Using the hardware system and software algorithm\, our system can reconstruct the relative motion of each pixel during the exposure time with 6-DoF. The second part is about the embedded laser speckle imaging systems that we developed. The mobile LSI (mLSI) system is a battery-powered laser speckle imaging system to meet the portability requirements of special applications (e.g. emergency vehicle\, battle field). We designed the automated power control (APC) circuit based laser diode driver to reduce the power consumption while maintaining the accuracy of the data. We evaluated the pulsed operation of the laser diode with always-on operation using the driver. The mLSI system showed equivalent performance from the evaluation with the clinical LSI system. The small field of view of conventional LSI systems is not adequate to be used for the applications that require fast treatment on large area (e.g. burn wounds). The multi-camera LSI (mcLSI) system was developed to address the requirement. mcLSI shows significant improvement in spatio-temporal resolution over conventional LSI systems. The unit based design enables users to expand the FoV without the sacrifice of the system performance (e.g. average speckle contrast\, spatial/temporal resolution).
URL:https://www.cecs.uci.edu/event/embedded-computer-vision-systems-for-image-based-motion-and-speckle-image-analysis/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130508T150000
DTEND;TZID=America/Los_Angeles:20130508T160000
DTSTAMP:20231011T190343Z
CREATED:20231011T190343Z
LAST-MODIFIED:20231011T190343Z
UID:14399-1368025200-1368028800@www.cecs.uci.edu
SUMMARY:Cooperative Communication for Wireless Physical Layer Security
DESCRIPTION:Date/Time: Friday\, May 10\, 2013\, 11:00 a.m. – 12:00 p.m.Location: 3206 Engineering Hall  \nCommittee Members:Professor A. Lee Swindlehurst (Chair)Professor Ender AyanogluProfessor Ahmed Eltawil \nAbstract:Cooperative communication in relay networks facilitates high spectral efficiency and large wireless transmission coverage. Despite the advances of improved cooperative diversity and flexible node deployment\, the relay network has more transmission nodes exposed in wireless environment than conventional single hop network\, and also extends the area over which the private transmitted signals may be intercepted by unintended receivers or eavesdroppers. Unlike the traditional approach of cryptographic design in the application layer\, in this work we investigate security issues in relay networks from a physical layer perspective. \nWe start with a two-hop multiple-input multiple-output (MIMO) relay network and propose cooperative beamforming and jamming strategies to maximize the secrecy rate. The corresponding power allocation is also optimized via geometric programming. Both cases with known and unknown eavesdropper’s channel state information (ECSI) are considered. Next\, we study a case where the relay is untrusted although it helps with forwarding message to the destination. The exact secrecy outage probability (SOP) is characterized with the impact of the number of antennas at the relay. Antenna selection\, beamforming and node selection schemes are proposed to suppress the wiretapping ability of the untrusted relay. Then we consider utilizing a buffer-aided relay that can dynamically control its receive and transmit phases. A link selection scheme that takes into account both the two-hop transmission efficiency and security constraints is proposed and shown to significantly improve the secrecy throughput. Finally\, we study robust transmit design when the relay acts as a pure cooperative jammer. The ECSI is assumed to be partially known and norm-bounded. The transmit covariance matrices are optimized via semidefinite programming\, based on maximizing the worst-case secrecy rate. Through this work\, we show that by taking advantage of the features of relay networks\, the security performance can be significantly improved in terms of secrecy rate and secrecy outage probability.
URL:https://www.cecs.uci.edu/event/cooperative-communication-for-wireless-physical-layer-security/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20130322T150000
DTEND;TZID=America/Los_Angeles:20130322T160000
DTSTAMP:20231011T190322Z
CREATED:20231011T190322Z
LAST-MODIFIED:20231011T190322Z
UID:14398-1363964400-1363968000@www.cecs.uci.edu
SUMMARY:Delft Reconfigurable VLIW Processor
DESCRIPTION:Speaker: Prof. Stephan Wong\, Computer Engineering Laboratory\, Delft University of Technology\, NetherlandsLocation: 2111 Engineering HallDate/Time: Tuesday\, March 26\, 2013\, 2:00pm to 3:00pmView Details 
URL:https://www.cecs.uci.edu/event/delft-reconfigurable-vliw-processor/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20121128T150000
DTEND;TZID=America/Los_Angeles:20121128T160000
DTSTAMP:20231011T190308Z
CREATED:20231011T190308Z
LAST-MODIFIED:20231011T190308Z
UID:14392-1354114800-1354118400@www.cecs.uci.edu
SUMMARY:Power-Saving Method for DRAM/eDRAM and 3D-DRAM expoliting the process variations\, temperature changes\, device degradation\, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service
DESCRIPTION:Date/Time: Friday\, December 7\, 2012\, 3:30-5:00PM\nLocation: Engineering Hall 3206 \nCommittee Members:\nProfessor Fadi Kurdahi (Chair)\nProfessor Ahmed Eltawil \nAbstract:\nIn this dissertation\, we have devised an innovative approach to dynamically set supply voltages and refresh cycle for Dynamic Random Access Memory (DRAM) and 1T1C embedded Dynamic Random Access Memory (eDRAM). The approach helps us to reduce power consumption. The DRAM/eDRAM is usually designed to sustain the worst operating conditions\, and the chip is very rarely operated under these conditions. We exploit the design slack while operating under more favorable conditions to power consumptions. Simulation results indicate that power consumption can be saved more than 10 times when the chip is normally operated. This keeps the chip cool and the operating temperature will be well under control\, which helps in averting device degradation and ultimate breakdown. In addition\, it is possible to extend the eDRAM data retention time\, which helps to improve the memory availability and system performance. Then a mixed-signal controller that implements our algorithm is presented in detail. Our proposed control circuit dynamically adjusts the supply voltages and the refresh cycle with an awareness of process variations\, temperature changes\, and device degradation to minimize power consumption or maximize memory availability. We use the Predictive Technology Model(PTM) 45nm to design and simulate the controller. The silicon area of the controller is only 0.052 mm2which is equivalent to the area of a 1.5 Megabit memory array. It operates at 100 MHz frequency and consumes about 260µW. Compared to a circuit which is designed to accommodate the worst case scenario\, we can save power consumption or extend the memory availability more than ten times when our chip operates under normal conditions. After that an innovative memory management approach which utilize both 3D-DRAM and external DRAM (ex-DRAM) is presented. Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive\, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads\, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for “latency sensitive”\, “bandwidth sensitive”\, and “insensitive” applications. To improve the performance and satisfy a certain level of QoS\, memory blocks of distinct application types are allocated differently. Compared to the scratchpad memory management mechanism\, the average memory access latency of our approach decreases by 19% and 23%\, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover\, using our approach\, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead\, particularly for applications which have high spatial memory locality. Finally\, we present a power-saving method for 3D-DRAM with an awareness of memory access workload variations. We dynamically and independently adjust supply voltages and refresh cycles of different 3D-DRAM dies to minimize their power consumption in the active and idle states. In fact\, the same power saving method for DRAM/eDRAM\, which exploits the design slack due to process variations and temperature changes\, is applied for 3D-DRAM. In both states\, we can still read/write normally and our method does not cause any performance overhead. The difference between these two states is the mechanism to minimize the power consumption: read/write operations and refresh operations consume the most power in the active and the idle state respectively. In addition\, we implement a memory relocation mechanism so that recently accessed memory blocks are gathered together into common 3D-DRAM dies. That allows the others to be in the idle state to save power consumption. The memory relocation mechanism is also an extension of the proposed heterogeneous memory management approach. The overhead of our memory relocation mechanism is negligible. Our simulation shows that if there is no memory access (all 3D-DRAM dies change into the idle state) our method can save power consumption up to 75%. If the memory access workload is low\, our method can save power consumption by almost 50%.
URL:https://www.cecs.uci.edu/event/power-saving-method-for-dram-edram-and-3d-dram-expoliting-the-process-variations-temperature-changes-device-degradation-and-memory-access-workload-variations-and-innovative-heterogeneous-memory-man/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14308-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Millimeter-Wave Circuits for W-band Applications
DESCRIPTION:Location:Calit2 3355\nDate and Time: March 8th\, 2012\, 10:00AM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Filippo Capolino\nProfessor A. Lee Swindlehurst \nTitle: Silicon-Based Millimeter-Wave Circuits for W-band Applications \nAbstract:\nHistorically\, monolithic microwave integrated circuits (MMICs) have been designed using III-V semiconductor technologies\, such as GaAs and InP. In recent years\, the number of publications reporting silicon-based millimeter-wave (mm-wave) transmitter\, receivers\, and transceivers has grown steadily. For mm-wave applications including gigabit/s point-to-point links (57-64 GHz)\, automative radar (77-81 GHz) and imaging (94 GHz) to reach mainstream market\, the cost\, size and power consumption of silicon-based solution has to be significantly below what is being achieved today using compound seminconductor technology. This dissertation focuses the effort of designing and implementing silicon-based solutions through circuit- and system-level innovation for applications in the W-band frequency band (750110GHz)\, in particular\, 94GHz passive imaging band. \nA W-band front-end receiver in 65nm CMOS based entirely on slow-wave CPW (SW-CPW) with frequency tripler as the LO is designed and measured. The receiver achieves a total gain of 35-dB\, -3dB-BW of 12 GHz\, a NF of 9-dB\, a P1-dB of -40dBM\, a low power consumption of 108mW under 1.2/0.8V. This front-end receiver chipset in conjuction with an analog back-end can be used to form a radiometer. \nLeveraging the work done in 65nm CMOS\, the first integrated 2×2 focal-plane array (FPA) for passive imaging is implemented in a 0.18um SiGE BiCMOS process (ft/fmax=200/180GHz). The FPA incorporates four Dicke-type receivers. Each receiver employs a direct-conversion architecture consisting of an on-chip slot dipole antenna\, an SPDT switch\, a lower noise amplifier\, a single-balanced mixer\, an injection-locked frequency tripler (ILFT)\, a zero-IF variable gain amplifier\, a power detector\, an active bandpass filter and a synchronous demodulator. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four ILFTx. This work demonstrates the highest level of integration of any silicon-based systems in the 94GHz imaging band. \nFinally\, the main design bottleneck of any wireless transceiver system\, the frequency synthesizer/phase-locked loop is investigated. Two monolithically integrated W-band frequency synthesizer are presented. Implemented in a 0.18um SiGe BiCMOS\, both architectures incorporate the same 30.3-33.8GHz PLL core. One sythesizer uses an injection-locked frequency tripler (ILFT) with locking range of 92.8-98.1GHz and the other employ a harmonic-based frequency tripler (HBFT) with 3-dB bandwidth of 10.5GHz from 90.0-101.4GHz\, respectively. The frequency sythesizer is suitable for integration in mm-wave phased array and multi-pixel systems such as W-band radar/imaging and 120GHz Gb/s communication.
URL:https://www.cecs.uci.edu/event/silicon-based-millimeter-wave-circuits-for-w-band-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120705T150000
DTEND;TZID=America/Los_Angeles:20120705T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14307-1341500400-1341504000@www.cecs.uci.edu
SUMMARY:Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging
DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: March 8th\, 2012\, 2:00-3:30PM \nCommittee:\nProfessor Payam Heydari (Chair)\nProfessor Michael Green\nProfessor Peter Burke \nTitle: Silicon-Based Integrated Circuits for W-Band Fully Integrated Passive Imaging \nAbstract:\nSilicon technology\, with its superior integration capability and low cost\, has changed the world dramatically during the past few decades and recently has entered the realm of millimeter-wave (MMW) system design that is used to be dominated by III-V compound semiconductor technologies. Benefiting from the continuous feature size scaling of silicon technology\, passive MMW imagers could be built on chip which paves the way for developing low-cost\, compact wafer-scale imagers. This dissertation focuses on the design of fully integrated W-band passive imager and also covers the design of W-band synthesizer which is one of the most critical and challenging building blocks of the imaging receiver. Two chips for 96GHz frequency generation incorporating the same Ka-band PLL and (1) an injection-locked frequency tripler (ILFT); (2) a harmonic-based frequency tripler (HBFT) in 0.18?m SiGe BiCMOS (fT/fmax=200/180GHz) are presented. The ILFT and HBFT preceded by the same Ka-band PPL achieve measured closed-loop phase noise of -93dBc/Hz and -92dBc/Hz at 1MHz offset\, respectively. Both chips are designed under the same power consumption of 14mW from 1.8V/2.5V supplies. This work presents the first implementation of an injection-locked-based frequency multiplier in SiGe BiCMOS process. W-band transformer-based injection-locked frequency tripler (T-ILFT) is also designed and implemented in 65nm standard CMOS technology using a 0.8V supply voltage. THe use of injection locking topology with on-chip transformer provides several advantages over conventional design. A fully integrated W-band 2×2 focal-plane array (FPA) for passive millimeter-wave imaging is demonstrated in 0.18?m SiGe BiCMOS process. The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture with an on-chip slot folded dipole antenna. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. This imaging receiver (without antenna) achievers a measured average responsivity and noise equivalent power of 285MV/W and 8.1fW/Hz1/2\, respectively\, across the 86-106GHz bandwidth\, which results a calculated NETD of 0.48K with a 30ms integration time. The system NETD increases to 3K with on-chip antenna due to its low efficiency at W-band. This work demonstrates the highest integration level of any silicon-based systems in the 94GHz imaging band.
URL:https://www.cecs.uci.edu/event/silicon-based-integrated-circuits-for-w-band-fully-integrated-passive-imaging/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120514T150000
DTEND;TZID=America/Los_Angeles:20120514T160000
DTSTAMP:20231011T183355Z
CREATED:20231011T183355Z
LAST-MODIFIED:20231011T183355Z
UID:14306-1337007600-1337011200@www.cecs.uci.edu
SUMMARY:Enhancing Quality of Viewing Experience for Future Mobile Video Applications
DESCRIPTION:by Kiarash Amiri May 14\, 2012 view details
URL:https://www.cecs.uci.edu/event/enhancing-quality-of-viewing-experience-for-future-mobile-video-applications/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20120223T150000
DTEND;TZID=America/Los_Angeles:20120223T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14309-1330009200-1330012800@www.cecs.uci.edu
SUMMARY:Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures
DESCRIPTION:Location: 2111 Engineering Hall\nDate and Time: February 23\, 2012\, 3:30pm – 5:30pm \nCommittee:\nProfessor Ahmed Eltawil (Chair)\nProfessor Ender Ayanoglu\nProfessor Fadi Kurdahi \nTitle: Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures \nAbstract:\nMIMO communication has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. However\, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity. In this thesis\, we present efficient design for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels. We consider that the MIMO detector and the channel decoder are two major blocks and attempt to optimize them in a joint sense. First of all\, we will focus on the design of MIMO detector and propose two approaches. The first design presents a novel algorithm and architecture for K-Best detection. The algorithm examines a much smaller subset of points in the tree structure while still achieving near-optimal performance. The VLSI architecture of the detector is based on a pipelined sorter-free scheme such that high throughput is achieved. The second design demonstrates an algorithm and VLSI architecture of combining the features of classical depth-first and breadth-first methods. Techniques to reduce complexity while providing both hard and soft output detection are also presented. Finally we will present an approach to perform joint detection and decoding for MIMO systems using convolutional codes. The BER performance of this approach is significantly better than that of systems which utilize separate detection and decoding blocks. The proof of concept VLSI architecture is provided and a novel way to reduce memory usage is demonstrated.
URL:https://www.cecs.uci.edu/event/tree-search-based-mimo-detectors-algorithms-and-vlsi-architectures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20111027T150000
DTEND;TZID=America/Los_Angeles:20111027T160000
DTSTAMP:20231011T183524Z
CREATED:20231011T183524Z
LAST-MODIFIED:20231011T183524Z
UID:14310-1319727600-1319731200@www.cecs.uci.edu
SUMMARY:Energy Harvesting and Power Optimization for Remote Sensing Systems
DESCRIPTION:Energy Harvesting and Power Optimization for Remote Sensing Systems\nby Sehwan Kim \nLocation: Engineering Gateway – CEE Conference Room \nDate and Time: October 27\, 2011 2:00pm \nCommittee:\nProf. Pai Chou (Chair)\nProf. Masanobu Shinozuka\nProf. Maria Feng \nAbstract:\nThe mobile and wireless micro-sensors suffer from short operational lifetimes because they lack space to store the energy that wireless transmission\, signal conditioning\, and monitoring require to operate across time. Energy harvesting capabilities enable totally untethered operation of mobile and wireless micro-sensors for extended periods of time without requiring battery replacement. This paper is to introduce and discuss the design challenges associated with harvesting circuits when harnessing\, conditioning\, and transferring power from ambient energy sources. In addition\, supercapacitors have emerged as an increasingly viable alternative to batteries for micro-solar energy harvesters. To address the problems of high leakage and high unusable residual charge\, previous work proposed multiple supercapacitors with a reconfigurable topology. We propose to optimize such systems by two ways: selection of optimal sizes of the supercapacitors at design time\, and choosing the optimal series or parallel topology at run time. This combination enables the supercapacitor subsystem to maximize the energy storage while minimizing leakage and residual energy\, thereby enabling the maximum utility of the energy storage elements over different operating scenarios.
URL:https://www.cecs.uci.edu/event/energy-harvesting-and-power-optimization-for-remote-sensing-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110928T150000
DTEND;TZID=America/Los_Angeles:20110928T160000
DTSTAMP:20231011T183525Z
CREATED:20231011T183525Z
LAST-MODIFIED:20231011T183525Z
UID:14311-1317222000-1317225600@www.cecs.uci.edu
SUMMARY:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures
DESCRIPTION:Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures\nby Amir Hossein Gholamipour \nCommittee:\nProf. Fadi Kurdahi (chair)\nProf. Ahmed Eltawil\nProf. Michael Dillencourt \nAn increasing number of digital systems\, from wireless devices to multi-media terminals\, are characterized by their multi-mode operation. This refers to the ability of a system to modify its characteristics or behavior based on user inputs or changes in the operational environment. FIR filters are frequently used in the operation of multi-mode systems due to their inherent stability and linear phase. In majority of such systems implementing a multi-mode FIR filter is the challenge in realizing the multi-mode behavior. FIR filters used for each mode of operation have different sets of parameters (coefficient sets). To implement multi-mode FIR filters\, General Purpose processors are incompetent in delivering the performance while Application Specific Integrated Circuits (ASICs) do not support the required flexibility. On Partially reconfigurable FPGA platforms we can optimize a filter structure based on the fixed parameters of filter and change the mode of operation by reconfiguring the fabric. However the reconfiguration overhead in this approach is not negligible. \nIn this work we introduce an approach which produces a spectrum of filter designs which trade-off area for reconfiguration overhead. In this thesis I prove that the problem of filter optimization can be solved in polynomial time. Furthermore as filter designs in the sequence of reconfiguration have similarities in their parameter sets\, we propose to jointly optimize their designs to further reduce the reconfiguration overhead. We consider the physical limitations of implementing multi-mode filters on FPGAs and propose a placement-aware approach to account for those limitations. Our placement-aware approach is an additional step called /Mapping/ that is introduced before floorplanning the design. In my work\, I show that mapping is an NP-hard problem and I propose ILP formulation and heuristics to solve it. As the result of my research\, I have developed a tool which gets the description of a sequence of filters as an input and generates the RTL design of the filters in VHDL code. It then gives hints on how to map the modules of the design to physical regions on the FPGA chip. This design approach has been tested on a rich set of applications including “preamble detection” unit of OFDMA receivers\, template matching and matched-filter based spectrum sensors. The results show the importance of this approach and the efficiency of the solutions proposed.
URL:https://www.cecs.uci.edu/event/comprehensive-multi-level-joint-optimization-for-multi-mode-fir-like-structures/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20110903T150000
DTEND;TZID=America/Los_Angeles:20110903T160000
DTSTAMP:20231011T183525Z
CREATED:20231011T183525Z
LAST-MODIFIED:20231011T183525Z
UID:14312-1315062000-1315065600@www.cecs.uci.edu
SUMMARY:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story
DESCRIPTION:Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units\, the Peripheral Circuits Story\nby Houman Homayoun \nLocation: Bren Hall 4011 \nDate and Time: September 3\, 2011 2:30pm \nCommittee:\nProfessor Fadi Kurdahi (Chair)\nProfessor Alex Veidenbaum\,\nProfessor Jean-Luc Gaudiot\,\nProfessor Alex Nicolau. \nAbstract:\nLeakage currents in on-chip SRAMs: caches\, branch predictor\, register files and TLBs\, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines\, making remaining SRAM components\, in particular large drivers\, the primary source of leakage. We proposes an integrated circuit and architectural approach to reduce this source of leakage in all major SRAM-based units of the processor\, controlling them in a uniform way\, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Various low-power modes are defined\, from basic to ultra-low power\, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to be significant for all SRAM units. Resulting temperature reduction\, including the effect of positive feedback between temperature and leakage power\, is evaluated. A significant temperature reduction is achieved in each unit.
URL:https://www.cecs.uci.edu/event/beyond-memory-cells-for-leakage-and-temperature-control-in-sram-based-units-the-peripheral-circuits-story/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20101129T150000
DTEND;TZID=America/Los_Angeles:20101129T160000
DTSTAMP:20231011T183701Z
CREATED:20231011T183701Z
LAST-MODIFIED:20231011T183701Z
UID:14313-1291042800-1291046400@www.cecs.uci.edu
SUMMARY:Aggressive Power Management Utilizing Embedded Memory Fault Tolerant Adaptation For Wireless/Multimedia Systems
DESCRIPTION:Aggressive Power Management Utilizing Embedded Memory Fault Tolerant Adaptation For Wireless/Multimedia Systems\nby Amin Khajeh Djahromi \nLocation: Engineering Hall 2111 \nDate and Time: November 29\, 2010 4:00pm \nCommittee:\nProf. Pai H. Chou (Chair)\nProf. Stephen Jenks\nProf. Rainer Doemer \nAbstract:\nDesigners of next generation Systems-on-Chip (SoCs) face daunting challenges in generating high yielding architectures that integrate vast amounts of logic and memories in a minimum die size\, while simultaneously minimizing power consumption. Traditional design approaches attempt to guarantee 100% error-free SoCs. However\, advanced manufacturing technologies will make it economically impractical to insist on a 100% error-free SoC in terms of area and power. Fortunately\, many important application domains (e.g.\, communication and multimedia) are inherently error-aware\, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. In such systems\, the share of the SoC that is dedicated to embedded memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoC for most recent advanced wireless standards. Furthermore\, a large portion of the memory is typically used for buffering data that already has a high level of redundancy. \nFinally\, from a network perspective\, buffering memories are transparent across a hierarchy since they do not change the nature of the data stored\, which allows for simple and efficient cross- layer techniques. In my thesis I investigated the effect of voltage over scaling on the embedded memories functionality. Then I proposed fault tolerant adaptive voltage scaling and adaptive body biasing as a mean of reducing power consumption in embedded memories. These techniques tradeoff reliability versus power savings as a function of the time varying quality of the incoming data\, as long as the signal to noise ratio at the decision device is maintained at a desirable level. Moreover\, I addressed the notion of error-awareness across different abstraction layers physical\, application\, network\, and technology for the next generation SoCs. I showed that utilizing proposed techniques on embedded memories (mainly through aggressive ! voltage scaling) will result in a) appreciable power reduction in wire less systems depending on the application\, b) savings in cost and area by reducing or eliminating the need for circuit redundancy\, and c) achieving a higher “effective yield” by tolerating errors at the system level while keeping other parameters constant.
URL:https://www.cecs.uci.edu/event/aggressive-power-management-utilizing-embedded-memory-fault-tolerant-adaptation-for-wireless-multimedia-systems/
CATEGORIES:PhD Defenses
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20100907T150000
DTEND;TZID=America/Los_Angeles:20100907T160000
DTSTAMP:20231011T183701Z
CREATED:20231011T183701Z
LAST-MODIFIED:20231011T183701Z
UID:14314-1283871600-1283875200@www.cecs.uci.edu
SUMMARY:Leveraging Profile-Selected Execution Patterns for Optimized Code Execution in Resource-Constrained Systems
DESCRIPTION:Leveraging Profile-Selected Execution Patterns for Optimized Code Execution in Resource-Constrained Systems\nby Carmen Badea \nLocation: Bren Hall 3013 \nDate and Time: September 7\, 2010 11:00am \nCommittee:\nProf. Alex Nicolau (Chair)\nProf. Alex Veidenbaum\nProf. Nikil Dutt \nAbstract:\nEmbedded systems and related devices have become ubiquitous in today’s world and are expected to proliferate even further. The execution performance for such devices is of paramount importance and is often perceived as the limiting factor w.r.t. both the capabilities of the system\, as well as the user perception. Furthermore\, unlike traditional general-purpose computing systems\, these devices exhibit further inherent constraints due to their nature: memory and energy consumption. \nIn order to overcome the intrinsic drawbacks of Java execution for resource-constrained systems\, we propose to use dynamic profile-selected\, optimized execution patterns in order to build a lightweight Java execution environment\, targeting resource-constrained systems\, that achieves competitive Java runtime performance\, while having negligible impact on memory footprint\, as well as reducing the overall energy consumption. \nMore recently\, with the advancements in the web application technology\, the browser has emerged as the favorite platform for deploying many applications\, in particular for embedded devices such as smartphones. As such\, we investigated whether the use of frequent execution patterns selected as directed by dynamic profiling would be beneficial for browser execution performance. With the use of collected dynamic profiling data indicating the most frequent patterns of execution we were able to develop a browser prototype that delivers significant runtime performance speedups.
URL:https://www.cecs.uci.edu/event/leveraging-profile-selected-execution-patterns-for-optimized-code-execution-in-resource-constrained-systems/
CATEGORIES:PhD Defenses
END:VEVENT
END:VCALENDAR